From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7B1E57803CD for ; Mon, 24 Jul 2023 20:15:32 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=W4/KglXZL1lCEPy5rw5un1C+e2vR1oenJhCByTzduy4=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-Received:X-Gm-Message-State:X-Google-Smtp-Source:X-Received:X-Received:From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1690229731; v=1; b=ieImbeWy1iS991Mo621cViERkpJoSA8gkJS45FOCnitjIuSZwNiN/cyeQNkBv9XRNCdA/rwY Q75Z1rBBxNx5n7Zm3/e87SaTVAdfovMNdO0ioJri7lFroBEwIC6wwbv36+edL9DWsAyAe/gqTIe xfPq+FqmOnKb1QhOEmo5m9WE= X-Received: by 127.0.0.2 with SMTP id J1fuYY7687511xwBLUoAcUSy; Mon, 24 Jul 2023 13:15:31 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.4787.1690229730477987254 for ; Mon, 24 Jul 2023 13:15:30 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1b9e93a538dso24805165ad.3 for ; Mon, 24 Jul 2023 13:15:30 -0700 (PDT) X-Gm-Message-State: 6yfBXnMIQFzcohzZr0kq1EDqx7686176AA= X-Google-Smtp-Source: APBJJlGbh8YKzAG/Z//ai6vDGrzqOjGBEvSlyEdaTYtdvbIweHC28c5c4Kql4E7vQttPev2KzZl7Fg== X-Received: by 2002:a17:902:d509:b0:1b9:de67:2870 with SMTP id b9-20020a170902d50900b001b9de672870mr10684661plg.40.1690229729659; Mon, 24 Jul 2023 13:15:29 -0700 (PDT) X-Received: from MININT-0U7P5GU.redmond.corp.microsoft.com ([2001:4898:80e8:0:18a3:9b95:e44:14fd]) by smtp.gmail.com with ESMTPSA id y7-20020a1709029b8700b001b89045ff03sm9398104plp.233.2023.07.24.13.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 13:15:29 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v1 3/3] ArmPkg: ArmGic: Added functionalities to manipulate pending interrupts Date: Mon, 24 Jul 2023 13:15:22 -0700 Message-ID: <20230724201523.852-4-kuqin12@gmail.com> In-Reply-To: <20230724201523.852-1-kuqin12@gmail.com> References: <20230724201523.852-1-kuqin12@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kuqin12@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ieImbeWy; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4466 This change provides additional functionalities to `ArmGicLib` to manipulate pending interrupt related status. The added functions include: - `ArmGicSetPendingInterrupt` - `ArmGicClearPendingInterrupt` - `ArmGicIsInterruptPending` Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Sami Mujawar Signed-off-by: Kun Qin --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 162 ++++++++++++++++++++ ArmPkg/ArmPkg.ci.yaml | 2 + ArmPkg/Include/Library/ArmGicLib.h | 49 ++++++ 3 files changed, 213 insertions(+) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmG= icLib.c index 830d822d2c05..3844dc05e2af 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -33,6 +33,12 @@ #define IPRIORITY_ADDRESS(base, offset) ((base) +\=0D ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))=0D =0D +#define ISPENDR_ADDRESS(base, offset) ((base) +\=0D + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISPENDR + 4 * (offset))=0D +=0D +#define ICPENDR_ADDRESS(base, offset) ((base) +\=0D + ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICPENDR + 4 * (offset))=0D +=0D /**=0D *=0D * Return whether the Source interrupt index refers to a shared interrupt = (SPI)=0D @@ -440,6 +446,162 @@ ArmGicIsInterruptEnabled ( return ((Interrupts & (1 << RegShift)) !=3D 0);=0D }=0D =0D +/**=0D + Set an interrupt to pending state from GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +**/=0D +VOID=0D +EFIAPI=0D +ArmGicSetPendingInterrupt (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + )=0D +{=0D + UINT32 RegOffset;=0D + UINTN RegShift;=0D + ARM_GIC_ARCH_REVISION Revision;=0D + UINTN GicCpuRedistributorBase;=0D +=0D + // Calculate enable register offset and bit position=0D + RegOffset =3D (UINT32)(Source / 32);=0D + RegShift =3D Source % 32;=0D +=0D + Revision =3D ArmGicGetSupportedArchRevision ();=0D + if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) ||=0D + FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||=0D + SourceIsSpi (Source))=0D + {=0D + // Write set-pending register=0D + MmioWrite32 (=0D + GicDistributorBase + ARM_GIC_ICDSPR + (4 * RegOffset),=0D + 1 << RegShift=0D + );=0D + } else {=0D + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (=0D + GicRedistributorBase,=0D + Revision=0D + );=0D + if (GicCpuRedistributorBase =3D=3D 0) {=0D + ASSERT_EFI_ERROR (EFI_NOT_FOUND);=0D + return;=0D + }=0D +=0D + // Write set-enable register=0D + MmioWrite32 (=0D + ISPENDR_ADDRESS (GicCpuRedistributorBase, RegOffset),=0D + 1 << RegShift=0D + );=0D + }=0D +}=0D +=0D +/**=0D + Clear a pending interrupt from GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +**/=0D +VOID=0D +EFIAPI=0D +ArmGicClearPendingInterrupt (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + )=0D +{=0D + UINT32 RegOffset;=0D + UINTN RegShift;=0D + ARM_GIC_ARCH_REVISION Revision;=0D + UINTN GicCpuRedistributorBase;=0D +=0D + // Calculate enable register offset and bit position=0D + RegOffset =3D (UINT32)(Source / 32);=0D + RegShift =3D Source % 32;=0D +=0D + Revision =3D ArmGicGetSupportedArchRevision ();=0D + if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) ||=0D + FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||=0D + SourceIsSpi (Source))=0D + {=0D + // Write clear-enable register=0D + MmioWrite32 (=0D + GicDistributorBase + ARM_GIC_ICDICPR + (4 * RegOffset),=0D + 1 << RegShift=0D + );=0D + } else {=0D + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (=0D + GicRedistributorBase,=0D + Revision=0D + );=0D + if (GicCpuRedistributorBase =3D=3D 0) {=0D + return;=0D + }=0D +=0D + // Write clear-enable register=0D + MmioWrite32 (=0D + ICPENDR_ADDRESS (GicCpuRedistributorBase, RegOffset),=0D + 1 << RegShift=0D + );=0D + }=0D +}=0D +=0D +/**=0D + Check if an interrupt is pending in GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +=0D + @return BOOLEAN TRUE if the interrupt is pending, FALSE otherwise.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmGicIsInterruptPending (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + )=0D +{=0D + UINT32 RegOffset;=0D + UINTN RegShift;=0D + ARM_GIC_ARCH_REVISION Revision;=0D + UINTN GicCpuRedistributorBase;=0D + UINT32 Interrupts;=0D +=0D + // Calculate enable register offset and bit position=0D + RegOffset =3D (UINT32)(Source / 32);=0D + RegShift =3D Source % 32;=0D +=0D + Revision =3D ArmGicGetSupportedArchRevision ();=0D + if ((Revision =3D=3D ARM_GIC_ARCH_REVISION_2) ||=0D + FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||=0D + SourceIsSpi (Source))=0D + {=0D + Interrupts =3D MmioRead32 (=0D + GicDistributorBase + ARM_GIC_ICDSPR + (4 * RegOffset)=0D + );=0D + } else {=0D + GicCpuRedistributorBase =3D GicGetCpuRedistributorBase (=0D + GicRedistributorBase,=0D + Revision=0D + );=0D + if (GicCpuRedistributorBase =3D=3D 0) {=0D + return 0;=0D + }=0D +=0D + // Read set-enable register=0D + Interrupts =3D MmioRead32 (=0D + ISPENDR_ADDRESS (GicCpuRedistributorBase, RegOffset)=0D + );=0D + }=0D +=0D + return ((Interrupts & (1 << RegShift)) !=3D 0);=0D +}=0D +=0D VOID=0D EFIAPI=0D ArmGicDisableDistributor (=0D diff --git a/ArmPkg/ArmPkg.ci.yaml b/ArmPkg/ArmPkg.ci.yaml index 8a8f738437d5..06e31498cf79 100644 --- a/ArmPkg/ArmPkg.ci.yaml +++ b/ArmPkg/ArmPkg.ci.yaml @@ -154,11 +154,13 @@ "icdsgir",=0D "icdspr",=0D "icenabler",=0D + "icpendr",=0D "intid",=0D "ipriority",=0D "irouter",=0D "isenabler",=0D "ishst",=0D + "ispendr",=0D "istatus",=0D "itargets",=0D "lable",=0D diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/Ar= mGicLib.h index 28d58f187d4f..83d52756d61a 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -78,6 +78,8 @@ // GIC SGI & PPI Redistributor frame=0D #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers= =0D #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Register= s=0D +#define ARM_GICR_ISPENDR 0x0200 // Interrupt Set-Pending Registers= =0D +#define ARM_GICR_ICPENDR 0x0280 // Interrupt Clear-Pending Registe= rs=0D =0D // GIC Cpu interface=0D #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register=0D @@ -167,6 +169,53 @@ ArmGicDisableInterruptInterface ( IN UINTN GicInterruptInterfaceBase=0D );=0D =0D +/**=0D + Set an interrupt to pending state from GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +**/=0D +VOID=0D +EFIAPI=0D +ArmGicSetPendingInterrupt (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + );=0D +=0D +/**=0D + Clear a pending interrupt from GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +**/=0D +VOID=0D +EFIAPI=0D +ArmGicClearPendingInterrupt (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + );=0D +=0D +/**=0D + Check if an interrupt is pending in GIC.=0D +=0D + @param GicDistributorBase Base address of platform GIC Distributor.=0D + @param GicRedistributorBase Base address of platform GIC Redistributor.= =0D + @param Source Interrupt source ID.=0D +=0D + @return BOOLEAN TRUE if the interrupt is pending, FALSE otherwise.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmGicIsInterruptPending (=0D + IN UINTN GicDistributorBase,=0D + IN UINTN GicRedistributorBase,=0D + IN UINTN Source=0D + );=0D +=0D VOID=0D EFIAPI=0D ArmGicEnableDistributor (=0D --=20 2.41.0.windows.2 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