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Tue, 25 Jul 2023 02:11:07 -0500 From: "Chang, Abner via groups.io" To: CC: Michael D Kinney , Liming Gao , Zhiguang Liu , "Abdul Lateef Attar" Subject: [edk2-devel] [PATCH 1/5] MdePkg/Include: Update definitions of SPI related header files Date: Tue, 25 Jul 2023 15:10:45 +0800 Message-ID: <20230725071049.12-2-abner.chang@amd.com> In-Reply-To: <20230725071049.12-1-abner.chang@amd.com> References: <20230725071049.12-1-abner.chang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT031:EE_|SN7PR12MB7954:EE_ X-MS-Office365-Filtering-Correlation-Id: c3cc8fd0-6994-4059-ca9b-08db8cde5288 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: 0GmmGE5ypZuqE+IyaMoJPtvnnaEja3LEt/1E/RuVXyAV05lwCi+L/nlxE4/GZiiUdJ/VGEmMIa6HsThThO+wwWN0BtZN4pNNblaE9exSjsY76mgnXi0NoP72kGUcWgyFMI4q3F6yCkC/lvZGwwj0s9/OakwpYj/3nla0sHKDk+fGLXPooakDz7XSNclKyx5XPYTUdQgWkf0F8+xZv3991sNyl/MTsOq2BFr7dz3epSFj5/RAp6zzJ4NZ9kfIN9HlRlTXcITL9ZjBGSiTr8M2SgJXMR9AlQ//pijYDcBGTU5Chi1V57eFfHkV6oRoUQEXf7Gx6aZNWy7yTIiM4nL68HF67k/a8N7l/QutGWdFGpc2C16+32mUDNCCDxmhrCVhMTBzHgtZbVQE4/fmh2rrke6txE0H+v5A643LlXppg8T+G5NxxCU+rhf5RibE2insKB3aYtvwTYL5lp+FiniditiASYA1vptXyHIZII7WxHVtGiACUUR0EyOmq/rUjk7iM6BKGAyKHkaVWYRegk+1dpPMq0Z8PE9kGWokTHS0fp78n7/a6GSjpPNtJK433XLM4anf/4sFniN+k1YFnKXXidBNu1FUR9HUyD0JjFogOO7KHOpp4Rx26nCAWMs0oe76JBagQ9JDKsVQIKv/SUb8J4fcaAS1xK/pZiwqGeXxJxghrxfQvDwcKTJg8eIcZm+vNFyjUJiWJmwMunyG3d6+a0ONQZsqCdBtU8Ox4cIxnkFRQAEyJQGogAo4WJHJgY19yc9iUn2bcMcRT+YnJhvb4A== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2023 07:11:09.7600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3cc8fd0-6994-4059-ca9b-08db8cde5288 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7954 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abner.chang@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: ylDRAumLXjZnx8kLQH7Sb9GVx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=tsHYrSyu; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") From: abnchang BZ#: 4471 Update definitions according to PI spec v1.8 Errata as it is approved in PIWG (Ticket #2394). Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Abdul Lateef Attar --- MdePkg/Include/Protocol/SpiConfiguration.h | 8 ++++++++ MdePkg/Include/Protocol/SpiHc.h | 14 ++++++++++++++ MdePkg/Include/Protocol/SpiIo.h | 10 ++++++++++ 3 files changed, 32 insertions(+) diff --git a/MdePkg/Include/Protocol/SpiConfiguration.h b/MdePkg/Include/Pr= otocol/SpiConfiguration.h index 3f8fb9ff62c..cffdc8e232d 100644 --- a/MdePkg/Include/Protocol/SpiConfiguration.h +++ b/MdePkg/Include/Protocol/SpiConfiguration.h @@ -2,6 +2,7 @@ This file defines the SPI Configuration Protocol. =20 Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -168,6 +169,13 @@ typedef struct _EFI_SPI_BUS { VOID *ClockParameter; } EFI_SPI_BUS; =20 +/// +/// Definitions of SPI Part Attributes. +/// +#define SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +#define SPl_PART_SUPPORTS_4_B1T_DATA_BUS_WIDTH BIT1 +#define SPl_PART_SUPPORTS_8_B1T_DATA_BUS_WIDTH BIT2 + /// /// The EFI_SPI_PERIPHERAL data structure describes how a specific block o= f /// logic which is connected to the SPI bus. This data structure also sele= cts diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiH= c.h index 30128dd5c4d..645bfdefe9b 100644 --- a/MdePkg/Include/Protocol/SpiHc.h +++ b/MdePkg/Include/Protocol/SpiHc.h @@ -2,6 +2,7 @@ This file defines the SPI Host Controller Protocol. =20 Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -121,6 +122,19 @@ typedef EFI_STATUS IN EFI_SPI_BUS_TRANSACTION *BusTransaction ); =20 +/// +/// Definitions of SPI Host Controller Attributes. +/// +#define HC_SUPPORTS_WRITE_ONLY_OPERATIONS BIT0 +#define HC_SUPPORTS_READ_ONLY_OPERATIONS BIT1 +#define HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS BIT2 +#define HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT3 +#define HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT4 +#define HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT5 +#define HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT6 +#define HC_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT7 +#define HC_TRANSFER_SIZE_INCLUDES_OPCODE BIT8 +#define HC_TRANSFER_SIZE_INCLUDES_ADDRESS BIT9 /// /// Support a SPI data transaction between the SPI controller and a SPI ch= ip. /// diff --git a/MdePkg/Include/Protocol/SpiIo.h b/MdePkg/Include/Protocol/SpiI= o.h index b4fc5e03b88..0ea881fd115 100644 --- a/MdePkg/Include/Protocol/SpiIo.h +++ b/MdePkg/Include/Protocol/SpiIo.h @@ -2,6 +2,7 @@ This file defines the SPI I/O Protocol. =20 Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Revision Reference: @@ -223,6 +224,15 @@ typedef struct _EFI_SPI_BUS_TRANSACTION { UINT8 *ReadBuffer; } EFI_SPI_BUS_TRANSACTION; =20 +/// +/// Definitions of SPI I/O Attributes. +/// +#define SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0 +#define SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT1 +#define SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT2 +#define SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE BIT3 +#define SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS BIT4 + /// /// Support managed SPI data transactions between the SPI controller and a= SPI /// chip. --=20 2.37.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107221): https://edk2.groups.io/g/devel/message/107221 Mute This Topic: https://groups.io/mt/100345721/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-