* [edk2-devel] [Patch V7 1/4] UefiCpuPkg: Add SendStartupIpiAllExcludingSelf
2023-07-30 22:44 [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI Yuanhao Xie
@ 2023-07-30 22:44 ` Yuanhao Xie
2023-07-30 22:44 ` [edk2-devel] [Patch V7 2/4] UefiCpuPkg: Add PcdFirstTimeWakeUpAPsBySipi Yuanhao Xie
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Yuanhao Xie @ 2023-07-30 22:44 UTC (permalink / raw)
To: devel; +Cc: Yuanhao Xie, Eric Dong, Rahul Kumar, Gerd Hoffmann, Ray Ni
From: Yuanhao Xie <yuanhao.xie@intel.com>
Add new API SendStartupIpiAllExcludingSelf(), and modify
SendInitSipiSipiAllExcludingSelf() by let it call the new API.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
UefiCpuPkg/Include/Library/LocalApicLib.h | 17 ++++++++++++++++-
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 43 ++++++++++++++++++++++++++++++-------------
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 43 ++++++++++++++++++++++++++++++-------------
3 files changed, 76 insertions(+), 27 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index b55d88b0f5..d7c2ad3f70 100644
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -4,7 +4,7 @@
Local APIC library assumes local APIC is enabled. It does not
handles cases where local APIC is disabled.
- Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -185,6 +185,21 @@ SendInitIpiAllExcludingSelf (
VOID
);
+/**
+ Send a Start-up IPI to all processors excluding self.
+ This function returns after the IPI has been accepted by the target processors.
+ if StartupRoutine >= 1M, then ASSERT.
+ if StartupRoutine is not multiple of 4K, then ASSERT.
+ @param StartupRoutine Points to a start-up routine which is below 1M physical
+ address and 4K aligned.
+**/
+
+VOID
+EFIAPI
+SendStartupIpiAllExcludingSelf (
+ IN UINT32 StartupRoutine
+ );
+
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 008b8a070b..d56c6275cc 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
This local APIC library instance supports xAPIC mode only.
- Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -497,6 +497,33 @@ SendInitIpiAllExcludingSelf (
SendIpi (IcrLow.Uint32, 0);
}
+/**
+ Send a Start-up IPI to all processors excluding self.
+ This function returns after the IPI has been accepted by the target processors.
+ if StartupRoutine >= 1M, then ASSERT.
+ if StartupRoutine is not multiple of 4K, then ASSERT.
+ @param StartupRoutine Points to a start-up routine which is below 1M physical
+ address and 4K aligned.
+**/
+VOID
+EFIAPI
+SendStartupIpiAllExcludingSelf (
+ IN UINT32 StartupRoutine
+ )
+{
+ LOCAL_APIC_ICR_LOW IcrLow;
+
+ ASSERT (StartupRoutine < 0x100000);
+ ASSERT ((StartupRoutine & 0xfff) == 0);
+
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
+ SendIpi (IcrLow.Uint32, 0);
+}
+
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
@@ -551,22 +578,12 @@ SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
-
- ASSERT (StartupRoutine < 0x100000);
- ASSERT ((StartupRoutine & 0xfff) == 0);
-
SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
- IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
- SendIpi (IcrLow.Uint32, 0);
+ SendStartupIpiAllExcludingSelf (StartupRoutine);
if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200);
- SendIpi (IcrLow.Uint32, 0);
+ SendStartupIpiAllExcludingSelf (StartupRoutine);
}
}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 0ba0499631..aa4eb11181 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes.
- Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -736,6 +736,33 @@ SendInitIpiAllExcludingSelf (
SendIpi (IcrLow.Uint32, 0);
}
+/**
+ Send a Start-up IPI to all processors excluding self.
+ This function returns after the IPI has been accepted by the target processors.
+ if StartupRoutine >= 1M, then ASSERT.
+ if StartupRoutine is not multiple of 4K, then ASSERT.
+ @param StartupRoutine Points to a start-up routine which is below 1M physical
+ address and 4K aligned.
+**/
+VOID
+EFIAPI
+SendStartupIpiAllExcludingSelf (
+ IN UINT32 StartupRoutine
+ )
+{
+ LOCAL_APIC_ICR_LOW IcrLow;
+
+ ASSERT (StartupRoutine < 0x100000);
+ ASSERT ((StartupRoutine & 0xfff) == 0);
+
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
+ SendIpi (IcrLow.Uint32, 0);
+}
+
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
@@ -790,22 +817,12 @@ SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
-
- ASSERT (StartupRoutine < 0x100000);
- ASSERT ((StartupRoutine & 0xfff) == 0);
-
SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
- IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
- SendIpi (IcrLow.Uint32, 0);
+ SendStartupIpiAllExcludingSelf (StartupRoutine);
if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200);
- SendIpi (IcrLow.Uint32, 0);
+ SendStartupIpiAllExcludingSelf (StartupRoutine);
}
}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [edk2-devel] [Patch V7 2/4] UefiCpuPkg: Add PcdFirstTimeWakeUpAPsBySipi
2023-07-30 22:44 [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI Yuanhao Xie
2023-07-30 22:44 ` [edk2-devel] [Patch V7 1/4] UefiCpuPkg: Add SendStartupIpiAllExcludingSelf Yuanhao Xie
@ 2023-07-30 22:44 ` Yuanhao Xie
2023-07-30 22:44 ` [edk2-devel] [Patch V7 3/4] OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi Yuanhao Xie
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Yuanhao Xie @ 2023-07-30 22:44 UTC (permalink / raw)
To: devel; +Cc: Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Yuanhao Xie
Add PcdFirstTimeWakeUpAPsBySipi to check if it is in the OVMF environment
and necessary to wake up APs by INIT-SIPI-SIPI.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 +
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 +
UefiCpuPkg/UefiCpuPkg.dec | 11 +++++++++++
3 files changed, 13 insertions(+)
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index 7d45d3ad4d..55e46d4a1f 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -81,6 +81,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr ## CONSUMES
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
index 83e9028d0f..bc3d716aa9 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -66,6 +66,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index e7726a605c..68473fc640 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -214,6 +214,17 @@
# @Prompt Configure the SEV-ES work area base
gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
+ ## Determining APs' first-time wakeup by SIPI or INIT-SIPI-SIPI.
+ # Following a power-up or RESET of an MP system, The APs complete a
+ # minimal self-configuration, then wait for a startup signal (a SIPI
+ # message) from the BSP processor.
+ #
+ # TRUE - Broadcast SIPI.
+ # FALSE - Broadcast INIT-SIPI-SIPI.
+ #
+ # @Prompt BSP Broadcast Method for the first-time wakeup of APs
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|TRUE|BOOLEAN|0x30002007
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
# @Prompt Configure base address of CPU Local APIC
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [edk2-devel] [Patch V7 3/4] OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi.
2023-07-30 22:44 [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI Yuanhao Xie
2023-07-30 22:44 ` [edk2-devel] [Patch V7 1/4] UefiCpuPkg: Add SendStartupIpiAllExcludingSelf Yuanhao Xie
2023-07-30 22:44 ` [edk2-devel] [Patch V7 2/4] UefiCpuPkg: Add PcdFirstTimeWakeUpAPsBySipi Yuanhao Xie
@ 2023-07-30 22:44 ` Yuanhao Xie
2023-08-10 11:18 ` Ard Biesheuvel
2023-07-30 22:44 ` [edk2-devel] [Patch V7 4/4] UefiCpuPkg:Wake up APs after power-up or RESET through SIPI Yuanhao Xie
2023-08-10 12:21 ` [edk2-devel] [Patch V7 0/4] Wake " Ard Biesheuvel
4 siblings, 1 reply; 7+ messages in thread
From: Yuanhao Xie @ 2023-07-30 22:44 UTC (permalink / raw)
To: devel
Cc: Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Ard Biesheuvel,
Jiewen Yao, Jordan Justen, Yuanhao Xie
Disable PcdFirstTimeWakeUpAPsBySipi for OVMF to let BSP wake up APs by
INIT-SIPI-SIPI.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
OvmfPkg/OvmfPkgIa32.dsc | 9 ++++++++-
OvmfPkg/OvmfPkgIa32X64.dsc | 7 +++++++
OvmfPkg/OvmfPkgX64.dsc | 7 +++++++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index ed36935770..80d8e37009 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -1,7 +1,7 @@
## @file
# EFI/Framework Open Virtual Machine Firmware (OVMF) platform
#
-# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
# Copyright (c) Microsoft Corporation.
#
@@ -585,6 +585,13 @@
# Point to the MdeModulePkg/Application/UiApp/UiApp.inf
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ #
+ # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
+ # environment, QEMU lacks a simulation for the INIT process.
+ # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
+ # broadcast INIT-SIPI-SIPI for the first time.
+ #
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
################################################################################
#
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index 919315e4cb..d9757149e3 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -566,6 +566,13 @@
!if $(SOURCE_DEBUG_ENABLE) == TRUE
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
!endif
+ #
+ # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
+ # environment, QEMU lacks a simulation for the INIT process.
+ # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
+ # broadcast INIT-SIPI-SIPI for the first time.
+ #
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
[PcdsFixedAtBuild.IA32]
#
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 823de0d0f9..b12d874daa 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -615,6 +615,13 @@
# Point to the MdeModulePkg/Application/UiApp/UiApp.inf
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ #
+ # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
+ # environment, QEMU lacks a simulation for the INIT process.
+ # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
+ # broadcast INIT-SIPI-SIPI for the first time.
+ #
+ gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
################################################################################
#
--
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [edk2-devel] [Patch V7 3/4] OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi.
2023-07-30 22:44 ` [edk2-devel] [Patch V7 3/4] OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi Yuanhao Xie
@ 2023-08-10 11:18 ` Ard Biesheuvel
0 siblings, 0 replies; 7+ messages in thread
From: Ard Biesheuvel @ 2023-08-10 11:18 UTC (permalink / raw)
To: devel, yuanhao.xie
Cc: Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Ard Biesheuvel,
Jiewen Yao, Jordan Justen
On Mon, 31 Jul 2023 at 00:44, Yuanhao Xie <yuanhao.xie@intel.com> wrote:
>
> Disable PcdFirstTimeWakeUpAPsBySipi for OVMF to let BSP wake up APs by
> INIT-SIPI-SIPI.
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
> Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
> ---
> OvmfPkg/OvmfPkgIa32.dsc | 9 ++++++++-
> OvmfPkg/OvmfPkgIa32X64.dsc | 7 +++++++
> OvmfPkg/OvmfPkgX64.dsc | 7 +++++++
> 3 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
> index ed36935770..80d8e37009 100644
> --- a/OvmfPkg/OvmfPkgIa32.dsc
> +++ b/OvmfPkg/OvmfPkgIa32.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
> #
> -# Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.<BR>
> # (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> # Copyright (c) Microsoft Corporation.
> #
> @@ -585,6 +585,13 @@
>
> # Point to the MdeModulePkg/Application/UiApp/UiApp.inf
> gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> + #
> + # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
> + # environment, QEMU lacks a simulation for the INIT process.
> + # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
> + # broadcast INIT-SIPI-SIPI for the first time.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
>
> ################################################################################
> #
> diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
> index 919315e4cb..d9757149e3 100644
> --- a/OvmfPkg/OvmfPkgIa32X64.dsc
> +++ b/OvmfPkg/OvmfPkgIa32X64.dsc
> @@ -566,6 +566,13 @@
> !if $(SOURCE_DEBUG_ENABLE) == TRUE
> gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
> !endif
> + #
> + # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
> + # environment, QEMU lacks a simulation for the INIT process.
> + # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
> + # broadcast INIT-SIPI-SIPI for the first time.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
>
> [PcdsFixedAtBuild.IA32]
> #
> diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
> index 823de0d0f9..b12d874daa 100644
> --- a/OvmfPkg/OvmfPkgX64.dsc
> +++ b/OvmfPkg/OvmfPkgX64.dsc
> @@ -615,6 +615,13 @@
>
> # Point to the MdeModulePkg/Application/UiApp/UiApp.inf
> gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> + #
> + # INIT is now triggered before BIOS by ucode/hardware. In the OVMF
> + # environment, QEMU lacks a simulation for the INIT process.
> + # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to
> + # broadcast INIT-SIPI-SIPI for the first time.
> + #
> + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE
>
> ################################################################################
> #
> --
> 2.36.1.windows.1
>
>
>
>
>
>
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* [edk2-devel] [Patch V7 4/4] UefiCpuPkg:Wake up APs after power-up or RESET through SIPI.
2023-07-30 22:44 [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI Yuanhao Xie
` (2 preceding siblings ...)
2023-07-30 22:44 ` [edk2-devel] [Patch V7 3/4] OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi Yuanhao Xie
@ 2023-07-30 22:44 ` Yuanhao Xie
2023-08-10 12:21 ` [edk2-devel] [Patch V7 0/4] Wake " Ard Biesheuvel
4 siblings, 0 replies; 7+ messages in thread
From: Yuanhao Xie @ 2023-07-30 22:44 UTC (permalink / raw)
To: devel; +Cc: Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Yuanhao Xie
The implementation of this new behavior aligns with the guidelines
outlined in the Intel SDM.
Following a power-up or RESET of an MP system, system hardware
dynamically selects one of the processors on the system bus as the BSP.
The remaining processors are designated as APs. The APs complete a
minimal self-configuration, then wait for a startup signal (a SIPI
message) from the BSP processor.
Additionally, the MP protocol is executed only after
a power-up or RESET. If the MP protocol has completed and a
BSP is chosen, subsequent INITs (either to a specific processor or
system wide) do not cause the MP protocol to be repeated. Instead, each
logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) to
determine whether it should execute the BIOS boot-strap code (if it is
the BSP) or enter a wait-for-SIPI state (if it is an AP).
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index e7054adbcc..6f1456cfe1 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1294,7 +1294,14 @@ WakeUpAP (
if (CpuMpData->SevSnpIsEnabled && (CpuMpData->InitFlag != ApInitConfig)) {
SevSnpCreateAP (CpuMpData, -1);
} else {
- SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
+ if ((CpuMpData->InitFlag == ApInitConfig) && FixedPcdGetBool (PcdFirstTimeWakeUpAPsBySipi)) {
+ //
+ // SIPI can be used for the first time wake up after reset to reduce boot time.
+ //
+ SendStartupIpiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
+ } else {
+ SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
+ }
}
}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI.
2023-07-30 22:44 [edk2-devel] [Patch V7 0/4] Wake up APs after power-up or RESET through SIPI Yuanhao Xie
` (3 preceding siblings ...)
2023-07-30 22:44 ` [edk2-devel] [Patch V7 4/4] UefiCpuPkg:Wake up APs after power-up or RESET through SIPI Yuanhao Xie
@ 2023-08-10 12:21 ` Ard Biesheuvel
4 siblings, 0 replies; 7+ messages in thread
From: Ard Biesheuvel @ 2023-08-10 12:21 UTC (permalink / raw)
To: devel, yuanhao.xie, Liming Gao (Byosoft address), Michael Kinney
On Mon, 31 Jul 2023 at 00:44, Yuanhao Xie <yuanhao.xie@intel.com> wrote:
>
> The implementation of this new behavior aligns with the
> guidelines outlined in the Intel SDM.
>
> Following a power-up or RESET of an MP system, system hardware
> dynamically selects one of the processors on the system bus as
> the BSP. The remaining processors are designated as APs.
> The APs complete a minimal self-configuration,
> then wait for SIPI from the BSP processor
>
> Yuanhao Xie (1):
> UefiCpuPkg: Add SendStartupIpiAllExcludingSelf
>
> YuanhaoXie (3):
> UefiCpuPkg: Add PcdFirstTimeWakeUpAPsBySipi
> OvmfPkg: Disable PcdFirstTimeWakeUpAPsBySipi.
> UefiCpuPkg:Wake up APs after power-up or RESET through SIPI.
>
This series was reviewed by Ray before the soft freeze, it just lacked
a R-b from an OVMF maintainer (Jiewen or myself).
So unless anyone objects, I would like to merge this asap and include
it in the upcoming stable tag.
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^ permalink raw reply [flat|nested] 7+ messages in thread