From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A0B1F740032 for ; Wed, 23 Aug 2023 11:03:30 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=F1tWGdPUhYTidHUnGOu7U9FkCbudSPdBiqL5a3cO3JY=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1692788609; v=1; b=wjl5Dy5Y86/UNCLnCxmRrTKqUDsyNofiaSdvvlBQJEDi8RXSDA4iKwgBvSpy/gph6/r81Wp3 +58uTd/xaW/e/uS8mOlGJ/sr/ymo2isNV9yeVXz/Y9juleAPdh5aOYDGHoNzhgNTJ/8LZ/3lDyL 4u+Tv+shR9Sm9PLkr1rNCIQE= X-Received: by 127.0.0.2 with SMTP id 3dppYY7687511xvYBdqubsZQ; Wed, 23 Aug 2023 04:03:29 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.8731.1692788608328034864 for ; Wed, 23 Aug 2023 04:03:28 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE27E1042; Wed, 23 Aug 2023 04:04:07 -0700 (PDT) X-Received: from usa.arm.com (a077434.blr.arm.com [10.162.17.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 50AFD3F64C; Wed, 23 Aug 2023 04:03:25 -0700 (PDT) From: "sahil" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar , Sahil Subject: [edk2-devel] [edk2-platforms][PATCH V3 1/1] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG Date: Wed, 23 Aug 2023 16:33:18 +0530 Message-Id: <20230823110318.826467-1-sahil@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sahil@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: POucy4y2dyuDBTaYPzbafz6Fx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=wjl5Dy5Y; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io NT_FW_CONFIG DTB contains platform information passed by Tf-A boot stage. This information is used for Virtual memory map generation during PEI phase and passed on to DXE phase as a HOB, where it is used in ConfigurationManagerDxe. This patch adds a PEI to parse NT_FW_CONFIG and pass it to other PEI modules(as PPI) and DXE modules(as HOB). Signed-off-by: sahil --- Notes: v3: - Fixed code review comments - Added a PEI to parse nt_fw_config Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec = | 8 +- Platform/ARM/N1Sdp/N1SdpPlatform.dsc = | 5 +- Platform/ARM/N1Sdp/N1SdpPlatform.fdf = | 3 +- Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Configurat= ionManagerDxe.inf | 6 +- Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf = | 41 ++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = | 8 +- Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h = | 14 +-- Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Configurat= ionManager.c | 24 ++-- Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c = | 133 ++++++++++++++++++++ Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c = | 12 +- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c = | 33 +++-- Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S = | 4 +- 12 files changed, 255 insertions(+), 36 deletions(-) diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/Neov= erseN1Soc/NeoverseN1Soc.dec index d59f25a5b915..7118da25dce0 100644 --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec @@ -1,7 +1,7 @@ ## @file=0D # Describes the entire platform configuration.=0D #=0D -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
=0D +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -22,6 +22,8 @@ Include # Root include for the package=0D =0D [Guids.common]=0D + # ARM NeoverseN1Soc Platform Info descriptor=0D + gArmNeoverseN1SocPlatformInfoDescriptorGuid =3D { 0x9fa16eb5, 0xce13, 0x= 4d37, { 0x96, 0xf0, 0x0a, 0xb5, 0xf1, 0xab, 0xff, 0x01 } }=0D gArmNeoverseN1SocTokenSpaceGuid =3D { 0xab93eb78, 0x60d7, 0x4099, { 0xac= , 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }=0D =0D [PcdsFixedAtBuild]=0D @@ -83,3 +85,7 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x4000000= 0000|UINT64|0x0000004F=0D gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x4000000= 0000|UINT64|0x00000050=0D gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00= 000051=0D +=0D +[Ppis]=0D + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid =3D { 0x21D04AD4, 0x4D23,= 0x426D, { 0x8D, 0x3E, 0x92, 0x23, 0x3E, 0xF4, 0xB9, 0x5E } }=0D + gArmNeoverseN1SocParameterPpiGuid =3D { 0x4DDD5A72, 0x31AD, 0x4B20, { 0x= 8F, 0x5F, 0xB3, 0xE8, 0x24, 0x6F, 0x80, 0x2B } }=0D diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1Sd= pPlatform.dsc index d04b22d3ef51..691d1af3c25c 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc @@ -4,7 +4,7 @@ # This provides platform specific component descriptions and libraries tha= t=0D # conform to EFI/Framework standards.=0D #=0D -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
=0D +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -228,6 +228,9 @@ # Platform driver=0D Platform/ARM/N1Sdp/Drivers/PlatformDxe/PlatformDxe.inf=0D =0D + # PEI Phase modules=0D + Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf=0D +=0D # Human Interface Support=0D MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D =0D diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1Sd= pPlatform.fdf index e5e24ea50294..baac8a3ef727 100644 --- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf @@ -1,7 +1,7 @@ ## @file=0D # FDF file of N1Sdp=0D #=0D -# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
=0D +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D ##=0D @@ -195,6 +195,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Core/Pei/PeiMain.inf=0D INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf=0D INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf=0D + INF Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf=0D =0D FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {=0D SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE {=0D diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDx= e/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/Con= figurationManagerDxe/ConfigurationManagerDxe.inf index 4f8e7f13021a..242490caf860 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManagerDxe.inf +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManagerDxe.inf @@ -1,7 +1,7 @@ ## @file=0D # Configuration Manager Dxe=0D #=0D -# Copyright (c) 2021, ARM Limited. All rights reserved.
=0D +# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -42,6 +42,7 @@ =0D [LibraryClasses]=0D ArmPlatformLib=0D + HobLib=0D PrintLib=0D UefiBootServicesTableLib=0D UefiDriverEntryPoint=0D @@ -170,5 +171,8 @@ gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation=0D gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber=0D =0D +[Guids]=0D + gArmNeoverseN1SocPlatformInfoDescriptorGuid=0D +=0D [Depex]=0D TRUE=0D diff --git a/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.in= f b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf new file mode 100644 index 000000000000..2eec8c327205 --- /dev/null +++ b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.inf @@ -0,0 +1,41 @@ +## @file=0D +# This PEI module parse the NtFwConfig for N1Sdp platform and produce=0D +# the PPI and HOB.=0D +#=0D +# Copyright (c) 2023, ARM Limited. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001B=0D + BASE_NAME =3D N1SdpNtFwConfigPei=0D + FILE_GUID =3D CE76D56C-D3A5-4763-9138-DF09E1D1B614= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D Load=0D +=0D +[Sources]=0D + NtFwConfigPei.c=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdePkg/MdePkg.dec=0D + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + FdtLib=0D + HobLib=0D + PeimEntryPoint=0D +=0D +[Ppis]=0D + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid=0D + gArmNeoverseN1SocParameterPpiGuid=0D +=0D +[Guids]=0D + gArmNeoverseN1SocPlatformInfoDescriptorGuid=0D +=0D +[Depex]=0D + gArmNeoverseN1SocParameterPpiGuid=0D diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf = b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf index 96e590cdd810..6e7e16b86838 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf @@ -1,7 +1,7 @@ ## @file=0D # Platform Library for N1Sdp.=0D #=0D -# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
=0D +# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -58,8 +58,8 @@ =0D gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D =0D -[Guids]=0D - gEfiHobListGuid ## CONSUMES ## SystemTable=0D -=0D [Ppis]=0D gArmMpCoreInfoPpiGuid=0D + gArmNeoverseN1SocParameterPpiGuid=0D + gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid=0D +=0D diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/AR= M/NeoverseN1Soc/Include/NeoverseN1Soc.h index 097160c7e2d1..2f83d582ccf3 100644 --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h @@ -1,6 +1,6 @@ /** @file=0D *=0D -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.=0D +* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.=0D *=0D * SPDX-License-Identifier: BSD-2-Clause-Patent=0D *=0D @@ -41,11 +41,6 @@ #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000=0D #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000=0D =0D -// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is=0D -// pre-populated by a earlier boot stage=0D -#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SE= CURE_SRAM_BASE + \=0D - 0x00008000)=0D -=0D /*=0D * Platform information structure stored in Non-secure SRAM. Platform=0D * information are passed from the trusted firmware with the below structu= re=0D @@ -55,12 +50,15 @@ typedef struct {=0D /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */=0D UINT8 MultichipMode;=0D - /*! Slave count in C2C mode */=0D - UINT8 SlaveCount;=0D + /*! Secondary chip count in C2C mode */=0D + UINT8 SecondaryChipCount;=0D /*! Local DDR memory size in GigaBytes */=0D UINT8 LocalDdrSize;=0D /*! Remote DDR memory size in GigaBytes */=0D UINT8 RemoteDdrSize;=0D } NEOVERSEN1SOC_PLAT_INFO;=0D =0D +typedef struct {=0D + CONST VOID *NtFwConfig;=0D +} NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI;=0D #endif=0D diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDx= e/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/Configur= ationManagerDxe/ConfigurationManager.c index fa6408a7dd1e..e248826ec925 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManager.c +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Confi= gurationManager.c @@ -1,7 +1,7 @@ /** @file=0D Configuration Manager Dxe=0D =0D - Copyright (c) 2021, ARM Limited. All rights reserved.
=0D + Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -16,6 +16,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -28,6 +29,7 @@ #include "Platform.h"=0D =0D extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;=0D +static NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D =0D /** The platform configuration repository information.=0D */=0D @@ -1242,13 +1244,21 @@ InitializePlatformRepository ( IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo=0D )=0D {=0D - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D UINT64 Dram2Size;=0D UINT64 RemoteDdrSize;=0D + VOID *PlatInfoHob;=0D +=0D + PlatInfoHob =3D GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescripto= rGuid);=0D +=0D + if (PlatInfoHob =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob);= =0D =0D RemoteDdrSize =3D 0;=0D =0D - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE;=0D Dram2Size =3D ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);=0D =0D PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length =3D Dram2Size;=0D @@ -1512,7 +1522,6 @@ GetGicCInfo ( )=0D {=0D EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;=0D - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D UINT32 TotalObjCount;=0D UINT32 ObjIndex;=0D =0D @@ -1523,7 +1532,6 @@ GetGicCInfo ( }=0D =0D PlatformRepo =3D This->PlatRepoInfo;=0D - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE;=0D =0D if (PlatInfo->MultichipMode =3D=3D 1) {=0D TotalObjCount =3D PLAT_CPU_COUNT * 2;=0D @@ -1623,7 +1631,6 @@ GetStandardNameSpaceObject ( {=0D EFI_STATUS Status;=0D EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;=0D - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D UINT32 AcpiTableCount;=0D =0D if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) {=0D @@ -1634,7 +1641,7 @@ GetStandardNameSpaceObject ( =0D Status =3D EFI_NOT_FOUND;=0D PlatformRepo =3D This->PlatRepoInfo;=0D - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE;=0D +=0D AcpiTableCount =3D ARRAY_SIZE (PlatformRepo->CmAcpiTableList);=0D if (PlatInfo->MultichipMode =3D=3D 0)=0D AcpiTableCount -=3D 1;=0D @@ -1697,7 +1704,6 @@ GetArmNameSpaceObject ( {=0D EFI_STATUS Status;=0D EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;=0D - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D UINT32 GicRedistCount;=0D UINT32 GicCpuCount;=0D UINT32 ProcHierarchyInfoCount;=0D @@ -1718,8 +1724,6 @@ GetArmNameSpaceObject ( Status =3D EFI_NOT_FOUND;=0D PlatformRepo =3D This->PlatRepoInfo;=0D =0D - // Probe for multi chip information=0D - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE;=0D if (PlatInfo->MultichipMode =3D=3D 1) {=0D GicRedistCount =3D 2;=0D GicCpuCount =3D PLAT_CPU_COUNT * 2;=0D diff --git a/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c = b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c new file mode 100644 index 000000000000..ff6a6a7933c3 --- /dev/null +++ b/Platform/ARM/N1Sdp/Drivers/N1SdpNtFwConfigPei/NtFwConfigPei.c @@ -0,0 +1,133 @@ +/** @file=0D +=0D + Copyright (c) 2023, ARM Limited. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +STATIC EFI_PEI_PPI_DESCRIPTOR gPpi;=0D +=0D +/**=0D + The entrypoint of the module, parse NtFwConfig and produce the PPI and H= OB.=0D +=0D + @param[in] FileHandle Handle of the file being invoked.=0D + @param[in] PeiServices Describes the list of possible PEI Services.=0D +=0D + @retval EFI_SUCCESS Either no NT_FW_CONFIG was given by EL3 firmwar= e=0D + OR the N1Sdp FDT HOB was successfully created.= =0D + @retval EFI_UNSUPPORTED FDT header sanity check failed.=0D + @retval * Other errors are possible.=0D +**/=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +Load (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + CONST NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI *ParamPpi;=0D + CONST UINT32 *Property;=0D + INT32 Offset;=0D + NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D + INT32 Status;=0D +=0D + PlatInfo =3D BuildGuidHob (=0D + &gArmNeoverseN1SocPlatformInfoDescriptorGuid,=0D + sizeof (*PlatInfo)=0D + );=0D +=0D + if (PlatInfo =3D=3D NULL) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "[%a]: failed to allocate platform info HOB\n",=0D + gEfiCallerBaseName=0D + ));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Status =3D PeiServicesLocatePpi (=0D + &gArmNeoverseN1SocParameterPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **)&ParamPpi=0D + );=0D +=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "[%a]: failed to locate gArmNeoverseN1SocParameterPpiGuid - %r\n",=0D + gEfiCallerBaseName,=0D + Status=0D + ));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if (fdt_check_header (ParamPpi->NtFwConfig) !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", ParamPpi->NtFwCon= fig));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Offset =3D fdt_subnode_offset (ParamPpi->NtFwConfig, 0, "platform-info")= ;=0D + if (Offset =3D=3D -FDT_ERR_NOTFOUND) {=0D + DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n"));= =0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "local-ddr-size"= , NULL);=0D + if (Property =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + PlatInfo->LocalDdrSize =3D fdt32_to_cpu (*Property);=0D +=0D + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "remote-ddr-size= ", NULL);=0D + if (Property =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + PlatInfo->RemoteDdrSize =3D fdt32_to_cpu (*Property);=0D +=0D + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "secondary-chip-= count", NULL);=0D + if (Property =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + PlatInfo->SecondaryChipCount =3D fdt32_to_cpu (*Property);=0D +=0D + Property =3D fdt_getprop (ParamPpi->NtFwConfig, Offset, "multichip-mode"= , NULL);=0D + if (Property =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + PlatInfo->MultichipMode =3D fdt32_to_cpu (*Property);=0D +=0D + gPpi.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI=0D + | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;=0D + gPpi.Guid =3D &gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid;=0D + gPpi.Ppi =3D PlatInfo;=0D +=0D + Status =3D PeiServicesInstallPpi (&gPpi);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "[%a]: failed to install PEI service - %r\n",=0D + gEfiCallerBaseName,=0D + Status=0D + ));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/= Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c index c0effd37f333..52ee6299b3fe 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c @@ -1,6 +1,6 @@ /** @file=0D =0D - Copyright (c) 2018-2021, ARM Limited. All rights reserved.
=0D + Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -8,8 +8,12 @@ =0D #include =0D #include =0D +#include =0D #include =0D =0D +UINT64 gArgNtFwConfigDtPtr;=0D +STATIC NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI mNeoverseN1SocParameterPpi;= =0D +=0D STATIC ARM_CORE_INFO mCoreInfoTable[] =3D {=0D { 0x0, 0x0 }, // Cluster 0, Core 0=0D { 0x0, 0x1 }, // Cluster 0, Core 1=0D @@ -46,6 +50,7 @@ ArmPlatformInitialize ( IN UINTN MpId=0D )=0D {=0D + mNeoverseN1SocParameterPpi.NtFwConfig =3D (VOID *)gArgNtFwConfigDtPtr;=0D return RETURN_SUCCESS;=0D }=0D =0D @@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { EFI_PEI_PPI_DESCRIPTOR_PPI,=0D &gArmMpCoreInfoPpiGuid,=0D &mMpCoreInfoPpi=0D + },=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI,=0D + &gArmNeoverseN1SocParameterPpiGuid,=0D + &mNeoverseN1SocParameterPpi=0D }=0D };=0D =0D diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c index 9e8a1efc557d..d6ef92677231 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c @@ -1,6 +1,6 @@ /** @file=0D =0D - Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
=0D + Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -10,6 +10,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D =0D // The total number of descriptors, including the final "end-of-table" des= criptor.=0D @@ -30,15 +31,31 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap=0D )=0D {=0D - UINTN Index;=0D - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;=0D - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D - NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D - UINT64 DramBlock2Size;=0D - UINT64 RemoteDdrSize;=0D + UINTN Index;=0D + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;=0D + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D + CONST NEOVERSEN1SOC_PLAT_INFO *PlatInfo;=0D + UINT64 DramBlock2Size;=0D + UINT64 RemoteDdrSize;=0D + EFI_STATUS Status;=0D =0D Index =3D 0;=0D - PlatInfo =3D (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_B= ASE;=0D +=0D + Status =3D PeiServicesLocatePpi (=0D + &gArmNeoverseN1SocPlatformInfoDescriptorPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **)&PlatInfo=0D + );=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "[%a]: failed to locate gArmNeoverseN1SocPlatformInfoDescriptorPpiGu= id - %r\n",=0D + gEfiCallerBaseName,=0D + Status=0D + ));=0D + }=0D +=0D DramBlock2Size =3D ((UINT64)(PlatInfo->LocalDdrSize -=0D NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *= =0D (UINT64)SIZE_1GB);=0D diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S= b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S index 8d2069dea837..cbbe7aae9858 100644 --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S @@ -1,6 +1,6 @@ /** @file=0D *=0D -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.=0D +* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved.=0D *=0D * SPDX-License-Identifier: BSD-2-Clause-Patent=0D *=0D @@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) // the UEFI firmware through the CPU registers.=0D //=0D ASM_PFX(ArmPlatformPeiBootAction):=0D + adr x10, gArgNtFwConfigDtPtr=0D + str x0, [x10]=0D ret=0D =0D //=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107975): https://edk2.groups.io/g/devel/message/107975 Mute This Topic: https://groups.io/mt/100912169/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-