From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 818DC7803D9 for ; Wed, 4 Oct 2023 18:34:36 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=u/M0dEyMTa8/735+EMO9sogYsnPAHo+Q5MAMrElzNKc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1696444475; v=1; b=lHvWVRbGcd6hD7d3BtNSBmv/qAW+GSb/l1vQJFYREisldq7bxIRY4RP8T/u7w06yYaJcm8G9 3rsxIv33nvvwkz8pr1dPyN7dDfrID+GQrWx0QmGRXArf7/UdFKZ49FCVYhorTemaLKwEpfeT1dX BlIXif0y8zc0NsG1JBTvRAmM= X-Received: by 127.0.0.2 with SMTP id zm2mYY7687511x4DcYlSaKIS; Wed, 04 Oct 2023 11:34:35 -0700 X-Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) by mx.groups.io with SMTP id smtpd.web11.1422.1696444474413029117 for ; Wed, 04 Oct 2023 11:34:34 -0700 X-Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-692b2bdfce9so77807b3a.3 for ; Wed, 04 Oct 2023 11:34:34 -0700 (PDT) X-Gm-Message-State: 9jzFim5J5CGwQPTTryAsuDmWx7686176AA= X-Google-Smtp-Source: AGHT+IGzLCOW1DpSFyu6jRkPAlSW6cHV/YjE15BmfzWGCMoIy1ERlVUtHSpHE2qoBXKpdlIu6waZ6g== X-Received: by 2002:a17:90a:4ec3:b0:274:84a2:f0d8 with SMTP id v3-20020a17090a4ec300b0027484a2f0d8mr3148167pjl.25.1696444473355; Wed, 04 Oct 2023 11:34:33 -0700 (PDT) X-Received: from localhost.localdomain (c-76-20-53-72.hsd1.ca.comcast.net. [76.20.53.72]) by smtp.gmail.com with ESMTPSA id b8-20020a17090a010800b00256799877ffsm2026752pjb.47.2023.10.04.11.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:34:32 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, eric.dong@intel.com, kraxel@redhat.com, rahul1.kumar@intel.com, ray.ni@intel.com, Tuan Phan , Dhaval Sharma Subject: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Date: Wed, 4 Oct 2023 11:34:26 -0700 Message-Id: <20231004183426.5803-1-tphan@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=lHvWVRbG; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Introduce a PCD to control the maximum SATP mode that MMU allowed to use. This PCD helps RISC-V platform set bare or minimum SATP mode during bring up to debug memory map issue. Signed-off-by: Tuan Phan Reviewed-by: Dhaval Sharma --- Changes: V2 - Changed default mode to SV57=20 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpu= Pkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c index 9cca5fc128af..826a1d32a1d4 100644 --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c @@ -36,7 +36,7 @@ #define PTE_PPN_SHIFT 10=0D #define RISCV_MMU_PAGE_SHIFT 12=0D =0D -STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MO= DE_SV39 };=0D +STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MO= DE_SV39, SATP_MODE_OFF };=0D STATIC UINTN mMaxRootTableLevel;=0D STATIC UINTN mBitPerLevel;=0D STATIC UINTN mTableEntryCount;=0D @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( UINTN Index;=0D EFI_STATUS Status;=0D =0D + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D switch (SatpMode) {=0D case SATP_MODE_OFF:=0D return EFI_SUCCESS;=0D diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiC= puPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf index 9b28a98cb346..51ebe1750e97 100644 --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf @@ -25,3 +25,6 @@ =0D [LibraryClasses]=0D BaseLib=0D +=0D +[Pcd]=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES=0D diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 68473fc640e6..0b5431dbf70a 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -396,6 +396,14 @@ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime = and ACPI NVS type after SmmReadyToLock.=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0= x3213210F=0D =0D +[PcdsFixedAtBuild.RISCV64]=0D + ## Indicate the maximum SATP mode allowed.=0D + # 0 - Bare mode.=0D + # 8 - 39bit mode.=0D + # 9 - 48bit mode.=0D + # 10 - 57bit mode.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021= =0D +=0D [PcdsDynamic, PcdsDynamicEx]=0D ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DA= TA.=0D # @Prompt The pointer to a CPU S3 data buffer.=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109330): https://edk2.groups.io/g/devel/message/109330 Mute This Topic: https://groups.io/mt/101761642/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-