* [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register
@ 2023-10-19 2:30 John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: John Chew @ 2023-10-19 2:30 UTC (permalink / raw)
To: devel
Cc: mindachen1987, Ard Biesheuvel, Leif Lindholm, Sunil V L, Li Yong,
John Chew
From: mindachen1987 <minda.chen@starfivetech.com>
Remove DMA enable in CTRL register
Added DMA polling handling for RX/TX
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Li Yong <yong.li@intel.com>
Co-authored-by: John Chew <yuinyee.chew@starfivetech.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h | 6 +++
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c | 52 ++++++++++++++++++--
2 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
index 09ad9b8428c4..3347418006c7 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
@@ -129,4 +129,10 @@
#define DWEMMC_GET_HDATA_WIDTH(x) (((x) >> 7) & 0x7)
+/* Internal IDMAC interrupt defines */
+#define DWMCI_IDINTEN_RI (1 << 1)
+#define DWMCI_IDINTEN_TI (1 << 0)
+
+#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_RI | DWMCI_IDINTEN_TI)
+
#endif // __DWEMMC_H__
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
index 39b1ea4346dc..7ac286c5f361 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
@@ -215,6 +215,7 @@ DwEmmcNotifyState (
do {
Data = MmioRead32 (DWEMMC_BMOD);
} while (Data & DWEMMC_IDMAC_SWRESET);
+ MmioWrite32 (DWEMMC_IDINTEN, 0x3);
break;
case MmcIdleState:
break;
@@ -463,6 +464,14 @@ PrepareDmaData (
)
{
UINTN Cnt, Blks, Idx, LastIdx;
+ UINT32 Data; /* flag, cnt */
+
+ MmioWrite32 (DWEMMC_CTRL, DWEMMC_CTRL_FIFO_RESET);
+ do {
+ /* Wait until reset operation finished */
+ Data = MmioRead32 (DWEMMC_CTRL);
+ } while (Data & DWEMMC_CTRL_RESET_ALL);
+ MmioWrite32 (DWEMMC_IDSTS, 0xffffffff);
Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
@@ -487,9 +496,7 @@ PrepareDmaData (
(IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
(LastIdx * DWEMMC_DMA_BUF_SIZE));
/* Set the Next field of Last Descriptor */
- (IdmacDesc + LastIdx)->Des3 = 0;
MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
-
return EFI_SUCCESS;
}
@@ -501,7 +508,7 @@ StartDma (
UINT32 Data;
Data = MmioRead32 (DWEMMC_CTRL);
- Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
+ Data |= DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
MmioWrite32 (DWEMMC_CTRL, Data);
Data = MmioRead32 (DWEMMC_BMOD);
Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
@@ -511,6 +518,41 @@ StartDma (
MmioWrite32 (DWEMMC_BYTCNT, Length);
}
+STATIC
+EFI_STATUS
+DwEmmcWaitDmaComplete (
+ IN EFI_MMC_HOST_PROTOCOL *This,
+ IN UINT32 Read
+ )
+{
+ UINT32 Mask, Ctrl, Timeout = 1000000;
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ Mask = (Read) ? DWMCI_IDINTEN_RI : DWMCI_IDINTEN_TI;
+
+ do {
+ Ctrl = MmioRead32 (DWEMMC_IDSTS);
+ if (Ctrl & Mask) {
+ break;
+ }
+ Timeout--;
+ gBS->Stall(1);
+ } while (Timeout);
+
+ if (!Timeout) {
+ DEBUG ((DEBUG_INFO, "%a, DMA waiting timeout...\n", __func__));
+ Status = EFI_DEVICE_ERROR;
+ }
+ MmioWrite32 (DWEMMC_IDSTS, DWMCI_IDINTEN_MASK);
+ Ctrl = MmioRead32(DWEMMC_CTRL);
+ Ctrl &= ~(DWEMMC_CTRL_DMA_EN);
+ Ctrl = MmioWrite32(DWEMMC_CTRL, Ctrl);
+
+ gBS->Stall(100);
+
+ return Status;
+}
+
EFI_STATUS
DwEmmcReadBlockData (
IN EFI_MMC_HOST_PROTOCOL *This,
@@ -544,6 +586,8 @@ DwEmmcReadBlockData (
DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
goto out;
}
+ Status = DwEmmcWaitDmaComplete(This, 1);
+
out:
// Restore Tpl
gBS->RestoreTPL (Tpl);
@@ -583,6 +627,8 @@ DwEmmcWriteBlockData (
DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
goto out;
}
+ Status = DwEmmcWaitDmaComplete(This, 0);
+
out:
// Restore Tpl
gBS->RestoreTPL (Tpl);
--
2.34.1
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* [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option
2023-10-19 2:30 [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
@ 2023-10-19 2:30 ` John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 3/4] DesignWare/DwEmmcDxe: Remove ARM dependency library John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 4/4] DesignWare/DwEmmcDxe: Add handling for SDMMC John Chew
2 siblings, 0 replies; 4+ messages in thread
From: John Chew @ 2023-10-19 2:30 UTC (permalink / raw)
To: devel
Cc: mindachen1987, Ard Biesheuvel, Leif Lindholm, Sunil V L, Li Yong,
mindachen1987, John Chew
From: mindachen1987 <minda.chen@starfivetech.com>
Add PCD for little endian CPU. During RX, the endianess of data receive
via DMA will be swap.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Li Yong <yong.li@intel.com>
Co-authored-by: mindachen1987 <mindachen1986@starfivetech.com>
Signed-off-by: John Chew <yuinyee.chew@starfivetech.com>
---
Silicon/Synopsys/DesignWare/DesignWare.dec | 1 +
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c | 5 +++++
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf | 1 +
3 files changed, 7 insertions(+)
diff --git a/Silicon/Synopsys/DesignWare/DesignWare.dec b/Silicon/Synopsys/DesignWare/DesignWare.dec
index f7ec7927543c..751370a8b1af 100755
--- a/Silicon/Synopsys/DesignWare/DesignWare.dec
+++ b/Silicon/Synopsys/DesignWare/DesignWare.dec
@@ -31,3 +31,4 @@ [PcdsFixedAtBuild.common]
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000003
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|0x0|UINT32|0x00000004
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|0x0|UINT32|0x00000005
+ gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|FALSE|BOOLEAN|0x00000008
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
index 7ac286c5f361..edda28a45d7c 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
@@ -588,6 +588,11 @@ DwEmmcReadBlockData (
}
Status = DwEmmcWaitDmaComplete(This, 1);
+ if (DWMCI_SD_READ_MASK(mDwEmmcArgument) && (FixedPcdGetBool (PcdDwEmmcDxeCPULittleEndian))) {
+ Buffer[3] = SwapBytes32(Buffer[3]);
+ Buffer[4] = SwapBytes32(Buffer[4]);
+ }
+
out:
// Restore Tpl
gBS->RestoreTPL (Tpl);
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
index 7f70fe1e2a38..18c84a4172f9 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
@@ -51,6 +51,7 @@ [Pcd]
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth
gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers
+ gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian
[Depex]
TRUE
--
2.34.1
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* [edk2-devel] [PATCH v1 3/4] DesignWare/DwEmmcDxe: Remove ARM dependency library
2023-10-19 2:30 [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
@ 2023-10-19 2:30 ` John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 4/4] DesignWare/DwEmmcDxe: Add handling for SDMMC John Chew
2 siblings, 0 replies; 4+ messages in thread
From: John Chew @ 2023-10-19 2:30 UTC (permalink / raw)
To: devel; +Cc: mindachen1987, Ard Biesheuvel, Leif Lindholm, Sunil V L, Li Yong
From: mindachen1987 <minda.chen@starfivetech.com>
This driver do not have dependency on ArmLib. It will cause compilation
error when compile with risv architecture.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Li Yong <yong.li@intel.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf | 1 -
1 file changed, 1 deletion(-)
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
index 18c84a4172f9..0bd78d5a05ad 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
@@ -30,7 +30,6 @@ [Packages]
Silicon/Synopsys/DesignWare/DesignWare.dec
[LibraryClasses]
- ArmLib
BaseLib
BaseMemoryLib
CacheMaintenanceLib
--
2.34.1
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* [edk2-devel] [PATCH v1 4/4] DesignWare/DwEmmcDxe: Add handling for SDMMC
2023-10-19 2:30 [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 3/4] DesignWare/DwEmmcDxe: Remove ARM dependency library John Chew
@ 2023-10-19 2:30 ` John Chew
2 siblings, 0 replies; 4+ messages in thread
From: John Chew @ 2023-10-19 2:30 UTC (permalink / raw)
To: devel
Cc: mindachen1987, Ard Biesheuvel, Leif Lindholm, Sunil V L, Li Yong,
John Chew
From: mindachen1987 <minda.chen@starfivetech.com>
Add base address PCD for eMMC and SDMMC
Add application command for SDMMC
Add PCD for Ultra High Speed (UHS) option
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Li Yong <yong.li@intel.com>
Co-authored-by: John Chew <yuinyee.chew@starfivetech.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
Silicon/Synopsys/DesignWare/DesignWare.dec | 2 +
Silicon/Synopsys/DesignWare/DesignWare.dsc | 1 +
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h | 64 +++----
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c | 183 +++++++++++++-------
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf | 1 +
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/{DwEmmcDxe.inf => DwSdmmcDxe.inf} | 9 +-
6 files changed, 158 insertions(+), 102 deletions(-)
diff --git a/Silicon/Synopsys/DesignWare/DesignWare.dec b/Silicon/Synopsys/DesignWare/DesignWare.dec
index 751370a8b1af..91aca7568b08 100755
--- a/Silicon/Synopsys/DesignWare/DesignWare.dec
+++ b/Silicon/Synopsys/DesignWare/DesignWare.dec
@@ -31,4 +31,6 @@ [PcdsFixedAtBuild.common]
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000003
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|0x0|UINT32|0x00000004
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|0x0|UINT32|0x00000005
+ gDesignWareTokenSpaceGuid.PcdDwSdDxeBaseAddress|0x0|UINT32|0x00000006
+ gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn|TRUE|BOOLEAN|0x00000007
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|FALSE|BOOLEAN|0x00000008
diff --git a/Silicon/Synopsys/DesignWare/DesignWare.dsc b/Silicon/Synopsys/DesignWare/DesignWare.dsc
index b5a7b38e142e..7ebec358851e 100755
--- a/Silicon/Synopsys/DesignWare/DesignWare.dsc
+++ b/Silicon/Synopsys/DesignWare/DesignWare.dsc
@@ -43,3 +43,4 @@ [LibraryClasses]
[Components]
Silicon/Synopsys/DesignWare/Drivers/DwEmacSnpDxe/DwEmacSnpDxe.inf
Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+ Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
index 3347418006c7..5d2e6d4055a4 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
@@ -18,38 +18,38 @@
#include <Protocol/EmbeddedGpio.h>
// DW MMC Registers
-#define DWEMMC_CTRL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x000)
-#define DWEMMC_PWREN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x004)
-#define DWEMMC_CLKDIV ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x008)
-#define DWEMMC_CLKSRC ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x00c)
-#define DWEMMC_CLKENA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x010)
-#define DWEMMC_TMOUT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x014)
-#define DWEMMC_CTYPE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x018)
-#define DWEMMC_BLKSIZ ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x01c)
-#define DWEMMC_BYTCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x020)
-#define DWEMMC_INTMASK ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x024)
-#define DWEMMC_CMDARG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x028)
-#define DWEMMC_CMD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x02c)
-#define DWEMMC_RESP0 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x030)
-#define DWEMMC_RESP1 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x034)
-#define DWEMMC_RESP2 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x038)
-#define DWEMMC_RESP3 ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x03c)
-#define DWEMMC_RINTSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x044)
-#define DWEMMC_STATUS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x048)
-#define DWEMMC_FIFOTH ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x04c)
-#define DWEMMC_TCBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x05c)
-#define DWEMMC_TBBCNT ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x060)
-#define DWEMMC_DEBNCE ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x064)
-#define DWEMMC_HCON ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x070)
-#define DWEMMC_UHSREG ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x074)
-#define DWEMMC_BMOD ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x080)
-#define DWEMMC_DBADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x088)
-#define DWEMMC_IDSTS ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x08c)
-#define DWEMMC_IDINTEN ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x090)
-#define DWEMMC_DSCADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x094)
-#define DWEMMC_BUFADDR ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0x098)
-#define DWEMMC_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X100)
-#define DWEMMC_DATA ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress) + 0X200)
+#define DWEMMC_CTRL ((PcdDwDxeBaseAddress) + 0x000)
+#define DWEMMC_PWREN ((PcdDwDxeBaseAddress) + 0x004)
+#define DWEMMC_CLKDIV ((PcdDwDxeBaseAddress) + 0x008)
+#define DWEMMC_CLKSRC ((PcdDwDxeBaseAddress) + 0x00c)
+#define DWEMMC_CLKENA ((PcdDwDxeBaseAddress) + 0x010)
+#define DWEMMC_TMOUT ((PcdDwDxeBaseAddress) + 0x014)
+#define DWEMMC_CTYPE ((PcdDwDxeBaseAddress) + 0x018)
+#define DWEMMC_BLKSIZ ((PcdDwDxeBaseAddress) + 0x01c)
+#define DWEMMC_BYTCNT ((PcdDwDxeBaseAddress) + 0x020)
+#define DWEMMC_INTMASK ((PcdDwDxeBaseAddress) + 0x024)
+#define DWEMMC_CMDARG ((PcdDwDxeBaseAddress) + 0x028)
+#define DWEMMC_CMD ((PcdDwDxeBaseAddress) + 0x02c)
+#define DWEMMC_RESP0 ((PcdDwDxeBaseAddress) + 0x030)
+#define DWEMMC_RESP1 ((PcdDwDxeBaseAddress) + 0x034)
+#define DWEMMC_RESP2 ((PcdDwDxeBaseAddress) + 0x038)
+#define DWEMMC_RESP3 ((PcdDwDxeBaseAddress) + 0x03c)
+#define DWEMMC_RINTSTS ((PcdDwDxeBaseAddress) + 0x044)
+#define DWEMMC_STATUS ((PcdDwDxeBaseAddress) + 0x048)
+#define DWEMMC_FIFOTH ((PcdDwDxeBaseAddress) + 0x04c)
+#define DWEMMC_TCBCNT ((PcdDwDxeBaseAddress) + 0x05c)
+#define DWEMMC_TBBCNT ((PcdDwDxeBaseAddress) + 0x060)
+#define DWEMMC_DEBNCE ((PcdDwDxeBaseAddress) + 0x064)
+#define DWEMMC_HCON ((PcdDwDxeBaseAddress) + 0x070)
+#define DWEMMC_UHSREG ((PcdDwDxeBaseAddress) + 0x074)
+#define DWEMMC_BMOD ((PcdDwDxeBaseAddress) + 0x080)
+#define DWEMMC_DBADDR ((PcdDwDxeBaseAddress) + 0x088)
+#define DWEMMC_IDSTS ((PcdDwDxeBaseAddress) + 0x08c)
+#define DWEMMC_IDINTEN ((PcdDwDxeBaseAddress) + 0x090)
+#define DWEMMC_DSCADDR ((PcdDwDxeBaseAddress) + 0x094)
+#define DWEMMC_BUFADDR ((PcdDwDxeBaseAddress) + 0x098)
+#define DWEMMC_CARDTHRCTL ((PcdDwDxeBaseAddress) + 0X100)
+#define DWEMMC_DATA ((PcdDwDxeBaseAddress) + 0X200)
#define CMD_UPDATE_CLK 0x80202000
#define CMD_START_BIT (1 << 31)
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
index edda28a45d7c..39e4d994fcd4 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
@@ -25,12 +25,18 @@
#include <Protocol/MmcHost.h>
+#ifdef CONFIG_DWEMMC
+#define PcdDwDxeBaseAddress ((UINT32)PcdGet32 (PcdDwEmmcDxeBaseAddress))
+#elif CONFIG_DWSDMMC
+#define PcdDwDxeBaseAddress ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress))
+#endif
#include "DwEmmc.h"
-#define DWEMMC_DESC_PAGE 1
-#define DWEMMC_BLOCK_SIZE 512
-#define DWEMMC_DMA_BUF_SIZE (512 * 8)
-#define DWEMMC_MAX_DESC_PAGES 512
+#define DWEMMC_DESC_PAGE 1
+#define DWEMMC_BLOCK_SIZE 512
+#define DWEMMC_DMA_BUF_SIZE (512 * 8)
+#define DWEMMC_MAX_DESC_PAGES 512
+#define DWMCI_SD_READ_MASK(X) ((0xFFFFF0&X) == 0xFFFFF0)
typedef struct {
UINT32 Des0;
@@ -44,6 +50,7 @@ DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc;
EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
STATIC UINT32 mDwEmmcCommand;
STATIC UINT32 mDwEmmcArgument;
+STATIC UINT32 LastExecutedCommand = (UINT32) -1;
EFI_STATUS
DwEmmcReadBlockData (
@@ -204,6 +211,7 @@ DwEmmcNotifyState (
ASSERT (!EFI_ERROR (Status));
// Wait clock stable
MicroSecondDelay (100);
+ MmioWrite32 (DWEMMC_CTYPE, 0);
MmioWrite32 (DWEMMC_RINTSTS, ~0);
MmioWrite32 (DWEMMC_INTMASK, 0);
@@ -314,68 +322,106 @@ DwEmmcSendCommand (
UINT32 Cmd = 0;
EFI_STATUS Status = EFI_SUCCESS;
- switch (MMC_GET_INDX(MmcCmd)) {
- case MMC_INDX(0):
- Cmd = BIT_CMD_SEND_INIT;
- break;
- case MMC_INDX(1):
- Cmd = BIT_CMD_RESPONSE_EXPECT;
- break;
- case MMC_INDX(2):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
- BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
- break;
- case MMC_INDX(3):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_SEND_INIT;
- break;
- case MMC_INDX(7):
- if (Argument)
+ if (LastExecutedCommand == MMC_INDX(55)) {
+ switch (MMC_GET_INDX(MmcCmd)) {
+ case MMC_INDX(1):
+ Cmd = BIT_CMD_RESPONSE_EXPECT;
+ break;
+ // Application command
+ case MMC_INDX(6):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+ break;
+ case MMC_INDX(41):
+ Cmd = BIT_CMD_RESPONSE_EXPECT;
+ break;
+ case MMC_INDX(51):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ break;
+ default:
+ DEBUG ((DEBUG_ERROR, "%a: Unrecognized App command: %d\n", __func__, MMC_GET_INDX(MmcCmd)));
+ break;
+ }
+ } else {
+ switch (MMC_GET_INDX(MmcCmd)) {
+ case MMC_INDX(0):
+ Cmd = BIT_CMD_SEND_INIT;
+ break;
+ case MMC_INDX(1):
+ Cmd = BIT_CMD_RESPONSE_EXPECT;
+ break;
+ case MMC_INDX(2):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
+ BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
+ break;
+ case MMC_INDX(3):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_SEND_INIT;
+ break;
+ case MMC_INDX(7):
+ if (Argument) {
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+ } else {
+ Cmd = 0;
+ }
+ break;
+ case MMC_INDX(8):
+ if (Argument) {
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ } else {
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ }
+ break;
+ case MMC_INDX(9):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_LONG_RESPONSE;
+ break;
+ case MMC_INDX(12):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_STOP_ABORT_CMD;
+ break;
+ case MMC_INDX(13):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ break;
+ case MMC_INDX(16):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ /* BIT_CMD_DATA_EXPECTED | BIT_CMD_READ | */
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ break;
+ case MMC_INDX(6):
+ if DWMCI_SD_READ_MASK(Argument) {
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ } else {
Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
- else
- Cmd = 0;
- break;
- case MMC_INDX(8):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
- BIT_CMD_WAIT_PRVDATA_COMPLETE;
- break;
- case MMC_INDX(9):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_LONG_RESPONSE;
- break;
- case MMC_INDX(12):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_STOP_ABORT_CMD;
- break;
- case MMC_INDX(13):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_WAIT_PRVDATA_COMPLETE;
- break;
- case MMC_INDX(16):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
- BIT_CMD_WAIT_PRVDATA_COMPLETE;
- break;
- case MMC_INDX(17):
- case MMC_INDX(18):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
- BIT_CMD_WAIT_PRVDATA_COMPLETE;
- break;
- case MMC_INDX(24):
- case MMC_INDX(25):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
- BIT_CMD_WAIT_PRVDATA_COMPLETE;
- break;
- case MMC_INDX(30):
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
- BIT_CMD_DATA_EXPECTED;
- break;
- default:
- Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
- break;
+ }
+ break;
+ case MMC_INDX(17):
+ case MMC_INDX(18):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ break;
+ case MMC_INDX(24):
+ case MMC_INDX(25):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
+ BIT_CMD_WAIT_PRVDATA_COMPLETE;
+ break;
+ case MMC_INDX(30):
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
+ BIT_CMD_DATA_EXPECTED;
+ break;
+ default:
+ Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
+ break;
+ }
}
Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
@@ -385,6 +431,9 @@ DwEmmcSendCommand (
} else {
Status = SendCommand (Cmd, Argument);
}
+
+ LastExecutedCommand = MMC_GET_INDX(MmcCmd);
+
return Status;
}
@@ -475,7 +524,6 @@ PrepareDmaData (
Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
- Length = DWEMMC_BLOCK_SIZE * Blks;
for (Idx = 0; Idx < Cnt; Idx++) {
(IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
@@ -660,6 +708,9 @@ DwEmmcSetIos (
switch (TimingMode) {
case EMMCHS52DDR1V2:
case EMMCHS52DDR1V8:
+ if (!FixedPcdGetBool (PcdDwEmmcDxeUHSEn)) {
+ return EFI_UNSUPPORTED;
+ }
Data |= 1 << 16;
break;
case EMMCHS52:
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
index 0bd78d5a05ad..4e8dd7bcd7dc 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
@@ -51,6 +51,7 @@ [Pcd]
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth
gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian
+ gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn
[Depex]
TRUE
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf
similarity index 77%
copy from Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
copy to Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf
index 0bd78d5a05ad..efbf3bff56bd 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf
@@ -1,5 +1,5 @@
#/** @file
-# INF file for the eMMC Host Protocol implementation for the DesignWare MMC.
+# INF file for the SdMMC Host Protocol implementation for the DesignWare MMC.
#
# WARNING:
# This driver fails to follow the UEFI driver model without a good
@@ -14,8 +14,8 @@
[Defines]
INF_VERSION = 0x00010019
- BASE_NAME = DwEmmcDxe
- FILE_GUID = b549f005-4bd4-4020-a0cb-06f42bda68c3
+ BASE_NAME = DwSdmmcDxe
+ FILE_GUID = b549f005-4bd4-4020-a0cb-06f5478a68c3
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
@@ -45,11 +45,12 @@ [Protocols]
gEmbeddedMmcHostProtocolGuid
[Pcd]
- gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress
+ gDesignWareTokenSpaceGuid.PcdDwSdDxeBaseAddress
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth
gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers
+ gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian
[Depex]
--
2.34.1
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end of thread, other threads:[~2023-10-19 2:30 UTC | newest]
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-- links below jump to the message on this page --
2023-10-19 2:30 [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 3/4] DesignWare/DwEmmcDxe: Remove ARM dependency library John Chew
2023-10-19 2:30 ` [edk2-devel] [PATCH v1 4/4] DesignWare/DwEmmcDxe: Add handling for SDMMC John Chew
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