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* [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register
@ 2023-10-19  2:30 John Chew
  2023-10-19  2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: John Chew @ 2023-10-19  2:30 UTC (permalink / raw)
  To: devel
  Cc: mindachen1987, Ard Biesheuvel, Leif Lindholm, Sunil V L, Li Yong,
	John Chew

From: mindachen1987 <minda.chen@starfivetech.com>

Remove DMA enable in CTRL register
Added DMA polling handling for RX/TX

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Li Yong <yong.li@intel.com>
Co-authored-by: John Chew <yuinyee.chew@starfivetech.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
 Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h    |  6 +++
 Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c | 52 ++++++++++++++++++--
 2 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
index 09ad9b8428c4..3347418006c7 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h
@@ -129,4 +129,10 @@
 
 #define DWEMMC_GET_HDATA_WIDTH(x)               (((x) >> 7) & 0x7)
 
+/* Internal IDMAC interrupt defines */
+#define DWMCI_IDINTEN_RI                        (1 << 1)
+#define DWMCI_IDINTEN_TI                        (1 << 0)
+
+#define DWMCI_IDINTEN_MASK                      (DWMCI_IDINTEN_RI | DWMCI_IDINTEN_TI)
+
 #endif  // __DWEMMC_H__
diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
index 39b1ea4346dc..7ac286c5f361 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
@@ -215,6 +215,7 @@ DwEmmcNotifyState (
     do {
       Data = MmioRead32 (DWEMMC_BMOD);
     } while (Data & DWEMMC_IDMAC_SWRESET);
+    MmioWrite32 (DWEMMC_IDINTEN, 0x3);
     break;
   case MmcIdleState:
     break;
@@ -463,6 +464,14 @@ PrepareDmaData (
   )
 {
   UINTN  Cnt, Blks, Idx, LastIdx;
+  UINT32 Data; /* flag, cnt */
+
+  MmioWrite32 (DWEMMC_CTRL, DWEMMC_CTRL_FIFO_RESET);
+  do {
+    /* Wait until reset operation finished */
+    Data = MmioRead32 (DWEMMC_CTRL);
+  } while (Data & DWEMMC_CTRL_RESET_ALL);
+  MmioWrite32 (DWEMMC_IDSTS, 0xffffffff);
 
   Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
   Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
@@ -487,9 +496,7 @@ PrepareDmaData (
   (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
                                                       (LastIdx * DWEMMC_DMA_BUF_SIZE));
   /* Set the Next field of Last Descriptor */
-  (IdmacDesc + LastIdx)->Des3 = 0;
   MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
-
   return EFI_SUCCESS;
 }
 
@@ -501,7 +508,7 @@ StartDma (
   UINT32 Data;
 
   Data = MmioRead32 (DWEMMC_CTRL);
-  Data |= DWEMMC_CTRL_INT_EN | DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
+  Data |= DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
   MmioWrite32 (DWEMMC_CTRL, Data);
   Data = MmioRead32 (DWEMMC_BMOD);
   Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
@@ -511,6 +518,41 @@ StartDma (
   MmioWrite32 (DWEMMC_BYTCNT, Length);
 }
 
+STATIC
+EFI_STATUS
+DwEmmcWaitDmaComplete (
+  IN EFI_MMC_HOST_PROTOCOL     *This,
+  IN UINT32 Read
+  )
+{
+  UINT32 Mask, Ctrl, Timeout = 1000000;
+  EFI_STATUS Status = EFI_SUCCESS;
+
+  Mask = (Read) ? DWMCI_IDINTEN_RI : DWMCI_IDINTEN_TI;
+
+  do {
+    Ctrl = MmioRead32 (DWEMMC_IDSTS);
+    if (Ctrl & Mask) {
+      break;
+    }
+    Timeout--;
+    gBS->Stall(1);
+  } while (Timeout);
+
+  if (!Timeout) {
+    DEBUG ((DEBUG_INFO, "%a, DMA waiting timeout...\n", __func__));
+    Status = EFI_DEVICE_ERROR;
+  }
+  MmioWrite32 (DWEMMC_IDSTS, DWMCI_IDINTEN_MASK);
+  Ctrl = MmioRead32(DWEMMC_CTRL);
+  Ctrl &= ~(DWEMMC_CTRL_DMA_EN);
+  Ctrl = MmioWrite32(DWEMMC_CTRL, Ctrl);
+
+  gBS->Stall(100);
+
+  return Status;
+}
+
 EFI_STATUS
 DwEmmcReadBlockData (
   IN EFI_MMC_HOST_PROTOCOL     *This,
@@ -544,6 +586,8 @@ DwEmmcReadBlockData (
     DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
     goto out;
   }
+  Status = DwEmmcWaitDmaComplete(This, 1);
+
 out:
   // Restore Tpl
   gBS->RestoreTPL (Tpl);
@@ -583,6 +627,8 @@ DwEmmcWriteBlockData (
     DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
     goto out;
   }
+  Status = DwEmmcWaitDmaComplete(This, 0);
+
 out:
   // Restore Tpl
   gBS->RestoreTPL (Tpl);
-- 
2.34.1



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^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-10-19  2:30 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-19  2:30 [edk2-devel] [PATCH v1 1/4] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
2023-10-19  2:30 ` [edk2-devel] [PATCH v1 2/4] DesignWare/DwEmmcDxe: Add CPU little endian option John Chew
2023-10-19  2:30 ` [edk2-devel] [PATCH v1 3/4] DesignWare/DwEmmcDxe: Remove ARM dependency library John Chew
2023-10-19  2:30 ` [edk2-devel] [PATCH v1 4/4] DesignWare/DwEmmcDxe: Add handling for SDMMC John Chew

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