From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A5BCD941B3B for ; Sat, 21 Oct 2023 17:33:28 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=GgPJFHciowovB4nsA3z6vGrT1BwBlUahqDk4VLsnSzI=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1697909607; v=1; b=P7+s8adTPh9b/X2PqY+ViBYRVAhtA27wXw8GJlmt1zrtrOxCJXbd7mBOB2ZavXT5QJn7zDaB ADUutodL/tTP+idSYY3JOv0Kz48gkng3c0epejT7ZxTOHA04Ja5RrKPosFL1KA4LrcBwtsQBkXp 7db8HE08Kqc2BCG59sRZQvTM= X-Received: by 127.0.0.2 with SMTP id JNSnYY7687511x2nVxp5y8Kf; Sat, 21 Oct 2023 10:33:27 -0700 X-Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) by mx.groups.io with SMTP id smtpd.web10.83800.1697909606614791285 for ; Sat, 21 Oct 2023 10:33:26 -0700 X-Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1c9e95aa02dso14138935ad.0 for ; Sat, 21 Oct 2023 10:33:26 -0700 (PDT) X-Gm-Message-State: hqK3yveBo8P535eoTafv6dzZx7686176AA= X-Google-Smtp-Source: AGHT+IGH4v0bdjvluvO51WkvNfQc8Vfm7BUZK8x7r1Af8irBNjwXgB/qXwdzvGVHcIc3FEOwKuXh4A== X-Received: by 2002:a17:902:dac5:b0:1c0:cbaf:6954 with SMTP id q5-20020a170902dac500b001c0cbaf6954mr7737003plx.25.1697909605922; Sat, 21 Oct 2023 10:33:25 -0700 (PDT) X-Received: from dhaval.. ([2401:4900:1c80:4a26:3248:430a:4718:b9e6]) by smtp.gmail.com with ESMTPSA id jc15-20020a17090325cf00b001c746b986e5sm3433158plb.45.2023.10.21.10.33.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 10:33:25 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v6 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Date: Sat, 21 Oct 2023 23:03:10 +0530 Message-Id: <20231021173314.19363-2-dhaval@rivosinc.com> In-Reply-To: <20231021173314.19363-1-dhaval@rivosinc.com> References: <20231021173314.19363-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=P7+s8adT; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma --- Notes: V5: - Move cache management function declaration in baselib where it belongs MdePkg/Include/Library/BaseLib.h | 20 +++++++++++++++++= +++ MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 -----------------= --- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 5d7067ee854e..7142bbfa42f2 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt ( VOID=0D );=0D =0D +/**=0D + RISC-V invalidate instruction cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateInstCacheAsm (=0D + VOID=0D + );=0D +=0D +/**=0D + RISC-V invalidate data cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateDataCacheAsm (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D #if defined (MDE_CPU_LOONGARCH64)=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..d5efcf49a4bf 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -10,26 +10,6 @@ #include =0D #include =0D =0D -/**=0D - RISC-V invalidate instruction cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateInstCacheAsm (=0D - VOID=0D - );=0D -=0D -/**=0D - RISC-V invalidate data cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateDataCacheAsm (=0D - VOID=0D - );=0D -=0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D calling CPU.=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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