From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 247FC740038 for ; Sat, 21 Oct 2023 17:33:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=CZnKwPF78SCcdfbCm+LfwF4GQ9uqiRuEpuzpgflrU2w=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1697909613; v=1; b=MUkbfI3FGH/jhswdcq93dBopjQTFDY8OHZpCu88QT9GJintxwAY7+lX42xSd4nHROaPWr38y xz2KjrfzozBJByMLs0Y2nIzM1MXPQ6nEspouquJCelg0Ou0uC2eNdQwDjj+OXtkB9QKOnfeQ7hQ D60oOgxqCOa069rElCTqTYcQ= X-Received: by 127.0.0.2 with SMTP id r5BNYY7687511xQuZRQPsLer; Sat, 21 Oct 2023 10:33:33 -0700 X-Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mx.groups.io with SMTP id smtpd.web10.83802.1697909613170389131 for ; Sat, 21 Oct 2023 10:33:33 -0700 X-Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1c9daca2b85so14007795ad.1 for ; Sat, 21 Oct 2023 10:33:33 -0700 (PDT) X-Gm-Message-State: I3qYetCgvTBaISGED35HQwFmx7686176AA= X-Google-Smtp-Source: AGHT+IGTZc/rTo4HYCUYIz7q0ZHqxn5DQyoc4T2LRD1lojo555gJ5Z5Fq60B+teZxhuhOgwPHUkZFA== X-Received: by 2002:a17:902:da91:b0:1c6:de7:add9 with SMTP id j17-20020a170902da9100b001c60de7add9mr6596685plx.19.1697909612466; Sat, 21 Oct 2023 10:33:32 -0700 (PDT) X-Received: from dhaval.. ([2401:4900:1c80:4a26:3248:430a:4718:b9e6]) by smtp.gmail.com with ESMTPSA id jc15-20020a17090325cf00b001c746b986e5sm3433158plb.45.2023.10.21.10.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 10:33:32 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek Subject: [edk2-devel] [PATCH v6 3/5] MdePkg: Implement RISC-V Cache Management Operations Date: Sat, 21 Oct 2023 23:03:12 +0530 Message-Id: <20231021173314.19363-4-dhaval@rivosinc.com> In-Reply-To: <20231021173314.19363-1-dhaval@rivosinc.com> References: <20231021173314.19363-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=MUkbfI3F; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Sunil V L Cc: Daniel Schaefer Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma --- Notes: V1: - Implement Cache management instructions in Baselib MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Library/BaseLib.h | 33 +++= +++++++++++++++++ MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++= ++++++++ MdePkg/Library/BaseLib/RiscV64/{FlushCache.S =3D> RiscVCacheMgmt.S} | 17 += +++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC=0D RiscV64/RiscVCpuPause.S | GCC=0D RiscV64/RiscVInterrupt.S | GCC=0D - RiscV64/FlushCache.S | GCC=0D + RiscV64/RiscVCacheMgmt.S | GCC=0D RiscV64/CpuScratch.S | GCC=0D RiscV64/ReadTimer.S | GCC=0D RiscV64/RiscVMmu.S | GCC=0D diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index d4b56a9601da..60d60602b876 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence ( VOID=0D );=0D =0D +/**=0D + RISC-V flush cache block. Atomically perform a clean operation=0D + followed by an invalidate operation=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheFlushAsmCbo (=0D + IN UINTN=0D + );=0D +=0D +/**=0D +Perform a write transfer to another cache or to memory if the=0D +data in the copy of the cache block have been modified by a store=0D +operation=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheCleanAsmCbo (=0D + IN UINTN=0D + );=0D +=0D +/**=0D +Deallocate the copy of the cache block=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheInvalAsmCbo (=0D + IN UINTN=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D #if defined (MDE_CPU_LOONGARCH64)=0D diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/R= iscVasm.inc new file mode 100644 index 000000000000..6f418232d507 --- /dev/null +++ b/MdePkg/Include/RiscV64/RiscVasm.inc @@ -0,0 +1,19 @@ +/*=0D + *=0D + * RISC-V cache operation encoding.=0D + * Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + *=0D + */=0D +=0D +.macro RISCVCBOFLSH=0D + .word 0x25200f=0D +.endm=0D +=0D +.macro RISCVCBOINVD=0D + .word 0x05200f=0D +.endm=0D +=0D +.macro RISCVCBOCLEN=0D + .word 0x15200f=0D +.endm=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/RiscVCacheMgmt.S similarity index 57% rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S index e0eea0b5fb25..fe3943ae3f7c 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -3,10 +3,12 @@ // RISC-V cache operation.=0D //=0D // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D //------------------------------------------------------------------------= ------=0D +.include "RiscVasm.inc"=0D =0D .align 3=0D ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)=0D @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence): ASM_PFX(RiscVInvalidateDataCacheAsmFence):=0D fence=0D ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCbo)=0D +ASM_PFX (RiscVCpuCacheFlushAsmCbo):=0D + RISCVCBOFLSH=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCbo)=0D +ASM_PFX (RiscVCpuCacheCleanAsmCbo):=0D + RISCVCBOCLEN=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCbo)=0D +ASM_PFX (RiscVCpuCacheInvalAsmCbo):=0D + RISCVCBOINVD=0D + ret=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109878): https://edk2.groups.io/g/devel/message/109878 Mute This Topic: https://groups.io/mt/102103780/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-