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From: "John Chew" <yuinyee.chew@starfivetech.com>
To: <devel@edk2.groups.io>
Cc: mindachen1987 <minda.chen@starfivetech.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	"Cc : Li Yong" <yong.li@intel.com>,
	mindachen1987 <mindachen1986@starfivetech.com>,
	"John Chew" <yuinyee.chew@starfivetech.com>
Subject: [edk2-devel] [PATCH v2 2/5] DesignWare/DwEmmcDxe: Add CPU little endian option
Date: Mon, 23 Oct 2023 15:17:12 +0800	[thread overview]
Message-ID: <20231023071715.777-3-yuinyee.chew@starfivetech.com> (raw)
In-Reply-To: <20231023071715.777-1-yuinyee.chew@starfivetech.com>

From: mindachen1987 <minda.chen@starfivetech.com>

Add PCD for little endian CPU. During RX, the endianess of data receive
via DMA will be swap.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Cc: Li Yong <yong.li@intel.com>
Co-authored-by: mindachen1987 <mindachen1986@starfivetech.com>
Signed-off-by: John Chew <yuinyee.chew@starfivetech.com>
---
 Silicon/Synopsys/DesignWare/DesignWare.dec                  | 1 +
 Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c   | 5 +++++
 Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf | 1 +
 3 files changed, 7 insertions(+)

diff --git a/Silicon/Synopsys/DesignWare/DesignWare.dec b/Silicon/Synopsys/DesignWare/DesignWare.dec
index f7ec7927543c..751370a8b1af 100755
--- a/Silicon/Synopsys/DesignWare/DesignWare.dec
+++ b/Silicon/Synopsys/DesignWare/DesignWare.dec
@@ -31,3 +31,4 @@ [PcdsFixedAtBuild.common]
   gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|0x0|UINT32|0x00000003

   gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|0x0|UINT32|0x00000004

   gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|0x0|UINT32|0x00000005

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|FALSE|BOOLEAN|0x00000008

diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
index 7ac286c5f361..edda28a45d7c 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c
@@ -588,6 +588,11 @@ DwEmmcReadBlockData (
   }

   Status = DwEmmcWaitDmaComplete(This, 1);

 

+  if (DWMCI_SD_READ_MASK(mDwEmmcArgument) && (FixedPcdGetBool (PcdDwEmmcDxeCPULittleEndian))) {

+    Buffer[3] = SwapBytes32(Buffer[3]);

+    Buffer[4] = SwapBytes32(Buffer[4]);

+  }

+

 out:

   // Restore Tpl

   gBS->RestoreTPL (Tpl);

diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
index 7f70fe1e2a38..18c84a4172f9 100644
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
@@ -51,6 +51,7 @@ [Pcd]
   gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz

   gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth

   gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian

 

 [Depex]

   TRUE

-- 
2.34.1



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  parent reply	other threads:[~2023-10-23  7:18 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23  7:17 [edk2-devel] [PATCH v2 0/5] Designware MMCDXE changes and enhancement John Chew
2023-10-23  7:17 ` [edk2-devel] [PATCH v2 1/5] DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register John Chew
2023-10-23  7:17 ` John Chew [this message]
2023-10-23  7:17 ` [edk2-devel] [PATCH v2 3/5] DesignWare/DwEmmcDxe: Remove ARM dependency library John Chew
2023-10-23  7:17 ` [edk2-devel] [PATCH v2 4/5] DesignWare/DwEmmcDxe: Add handling for SDMMC John Chew
2023-10-23  7:17 ` [edk2-devel] [PATCH v2 5/5] DesignWare/DwEmmcDxe: Force DMA buffer to allocate below 4GB John Chew

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