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* [edk2-devel] [PATCH v2 1/1] StarFive/VisionFive2: Add VisionFive 2 platform
@ 2023-10-23  8:01 John Chew
  2023-10-26 13:47 ` Sunil V L
  0 siblings, 1 reply; 5+ messages in thread
From: John Chew @ 2023-10-23  8:01 UTC (permalink / raw)
  To: devel
  Cc: mindachen1987, Sunil V L, Leif Lindholm, Michael D Kinney,
	Li Yong, John Chew

From: mindachen1987 <minda.chen@starfivetech.com>

v2:
  - Change PlatformBootManagerLib to:
      Platform/RISC-V/PlatformPkg/.../PlatformBootManagerLib.inf
    [Sunil]
  - Added PCIE PCDs
    PcdPciBusMin, PcdPciBusMax, PcdPciIoBase, PcdPciIoSize
    PcdPciIoOffset, PcdPci0Mmio32Base, PcdPci0Mmio32Size
    PcdPci0Mmio64Base, PcdPci0Mmio64Size, PcdPci1Mmio32Base
    PcdPci1Mmio32Size, PcdPci1Mmio64Base, PcdPci1Mmio64Size
    [John Chew]

v1:
  - Added new platform support for VisionFive2 SBC.
  - Boot flow in VF2 using EDK2 as bootloader:
    BootROM -> U-Boot SPL -> OpenSBI -> EDK2 -> Linux -> OS

  - Supported boot source for Linux from EDK2:
      - SD Card
      - eMMC
      - NVMe
      - USB

Reference branch:
  https://github.com/johnchewyy/edkii-platforms/tree/vf2_jh7110_devel_upstream

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Li Yong <yong.li@intel.com>
Co-authored-by: John Chew <yuinyee.chew@starfivetech.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
 Platform/StarFive/VisionFive2/DeviceTree/Gpio.h                    |   42 +
 Platform/StarFive/VisionFive2/DeviceTree/Irq.h                     |   20 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h            |  398 +++++
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h            |   57 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h           |   68 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h           | 1573 +++++++++++++++++
 Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h             |   22 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h               |  228 +++
 Platform/StarFive/VisionFive2/DeviceTree/Led.h                     |   90 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi          |  130 ++
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi         |   28 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi       | 1812 ++++++++++++++++++++
 Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi       |   26 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts   |  211 +++
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi  |  838 +++++++++
 Platform/StarFive/VisionFive2/DeviceTree/Thermal.h                 |   16 +
 Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf |   36 +
 Platform/StarFive/VisionFive2/VarStore.fdf.inc                     |   77 +
 Platform/StarFive/VisionFive2/VisionFive2.dsc                      |  596 +++++++
 Platform/StarFive/VisionFive2/VisionFive2.fdf                      |  284 +++
 Platform/StarFive/VisionFive2/VisionFive2.fdf.inc                  |   48 +
 21 files changed, 6600 insertions(+)

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h b/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h
new file mode 100644
index 000000000000..89f4c44eaec0
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h
@@ -0,0 +1,42 @@
+/** @file
+  This header provide all the general purpose input/output device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_GPIO_H__
+#define __DT_BINDINGS_GPIO_H__
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH  0
+#define GPIO_ACTIVE_LOW   1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL     0
+#define GPIO_SINGLE_ENDED  2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE  0
+#define GPIO_LINE_OPEN_DRAIN   4
+
+/*
+ * Open Drain/Collector is the combination of single-ended open drain interface.
+ * Open Source/Emitter is the combination of single-ended open source interface.
+ */
+#define GPIO_OPEN_DRAIN   (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE  (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT  0
+#define GPIO_TRANSITORY  8
+
+/* Bit 4 express pull up */
+#define GPIO_PULL_UP  16
+
+/* Bit 5 express pull down */
+#define GPIO_PULL_DOWN  32
+
+#endif /* __DT_BINDINGS_GPIO_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Irq.h b/Platform/StarFive/VisionFive2/DeviceTree/Irq.h
new file mode 100644
index 000000000000..19d08bc4a816
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Irq.h
@@ -0,0 +1,20 @@
+/** @file
+  This header provide all the interrupt device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__
+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__
+
+#define IRQ_TYPE_NONE          0
+#define IRQ_TYPE_EDGE_RISING   1
+#define IRQ_TYPE_EDGE_FALLING  2
+#define IRQ_TYPE_EDGE_BOTH     (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH    4
+#define IRQ_TYPE_LEVEL_LOW     8
+
+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h
new file mode 100644
index 000000000000..475967eff848
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h
@@ -0,0 +1,398 @@
+/** @file
+  This header provide all JH7110 clock generator device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_CLK_GEN_H__
+#define __DT_BINDINGS_JH7110_CLK_GEN_H__
+
+/* sys regisger */
+#define JH7110_CPU_ROOT                     0
+#define JH7110_CPU_CORE                     1
+#define JH7110_CPU_BUS                      2
+#define JH7110_GPU_ROOT                     3
+#define JH7110_PERH_ROOT                    4
+#define JH7110_BUS_ROOT                     5
+#define JH7110_NOCSTG_BUS                   6
+#define JH7110_AXI_CFG0                     7
+#define JH7110_STG_AXIAHB                   8
+#define JH7110_AHB0                         9
+#define JH7110_AHB1                         10
+#define JH7110_APB_BUS_FUNC                 11
+#define JH7110_APB0                         12
+#define JH7110_PLL0_DIV2                    13
+#define JH7110_PLL1_DIV2                    14
+#define JH7110_PLL2_DIV2                    15
+#define JH7110_AUDIO_ROOT                   16
+#define JH7110_MCLK_INNER                   17
+#define JH7110_MCLK                         18
+#define JH7110_MCLK_OUT                     19
+#define JH7110_ISP_2X                       20
+#define JH7110_ISP_AXI                      21
+#define JH7110_GCLK0                        22
+#define JH7110_GCLK1                        23
+#define JH7110_GCLK2                        24
+#define JH7110_U7_CORE_CLK                  25
+#define JH7110_U7_CORE_CLK1                 26
+#define JH7110_U7_CORE_CLK2                 27
+#define JH7110_U7_CORE_CLK3                 28
+#define JH7110_U7_CORE_CLK4                 29
+#define JH7110_U7_DEBUG_CLK                 30
+#define JH7110_U7_RTC_TOGGLE                31
+#define JH7110_U7_TRACE_CLK0                32
+#define JH7110_U7_TRACE_CLK1                33
+#define JH7110_U7_TRACE_CLK2                34
+#define JH7110_U7_TRACE_CLK3                35
+#define JH7110_U7_TRACE_CLK4                36
+#define JH7110_U7_TRACE_COM_CLK             37
+#define JH7110_NOC_BUS_CLK_CPU_AXI          38
+#define JH7110_NOC_BUS_CLK_AXICFG0_AXI      39
+#define JH7110_OSC_DIV2                     40
+#define JH7110_PLL1_DIV4                    41
+#define JH7110_PLL1_DIV8                    42
+#define JH7110_DDR_BUS                      43
+#define JH7110_DDR_CLK_AXI                  44
+#define JH7110_GPU_CORE                     45
+#define JH7110_GPU_CORE_CLK                 46
+#define JH7110_GPU_SYS_CLK                  47
+#define JH7110_GPU_CLK_APB                  48
+#define JH7110_GPU_RTC_TOGGLE               49
+#define JH7110_NOC_BUS_CLK_GPU_AXI          50
+#define JH7110_ISP_TOP_CLK_ISPCORE_2X       51
+#define JH7110_ISP_TOP_CLK_ISP_AXI          52
+#define JH7110_NOC_BUS_CLK_ISP_AXI          53
+#define JH7110_HIFI4_CORE                   54
+#define JH7110_HIFI4_AXI                    55
+#define JH7110_AXI_CFG1_DEC_CLK_MAIN        56
+#define JH7110_AXI_CFG1_DEC_CLK_AHB         57
+#define JH7110_VOUT_SRC                     58
+#define JH7110_VOUT_AXI                     59
+#define JH7110_NOC_BUS_CLK_DISP_AXI         60
+#define JH7110_VOUT_TOP_CLK_VOUT_AHB        61
+#define JH7110_VOUT_TOP_CLK_VOUT_AXI        62
+#define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK    63
+#define JH7110_VOUT_TOP_CLK_MIPIPHY_REF     64
+#define JH7110_JPEGC_AXI                    65
+#define JH7110_CODAJ12_CLK_AXI              66
+#define JH7110_CODAJ12_CLK_CORE             67
+#define JH7110_CODAJ12_CLK_APB              68
+#define JH7110_VDEC_AXI                     69
+#define JH7110_WAVE511_CLK_AXI              70
+#define JH7110_WAVE511_CLK_BPU              71
+#define JH7110_WAVE511_CLK_VCE              72
+#define JH7110_WAVE511_CLK_APB              73
+#define JH7110_VDEC_JPG_ARB_JPGCLK          74
+#define JH7110_VDEC_JPG_ARB_MAINCLK         75
+#define JH7110_NOC_BUS_CLK_VDEC_AXI         76
+#define JH7110_VENC_AXI                     77
+#define JH7110_WAVE420L_CLK_AXI             78
+#define JH7110_WAVE420L_CLK_BPU             79
+#define JH7110_WAVE420L_CLK_VCE             80
+#define JH7110_WAVE420L_CLK_APB             81
+#define JH7110_NOC_BUS_CLK_VENC_AXI         82
+#define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV    83
+#define JH7110_AXI_CFG0_DEC_CLK_MAIN        84
+#define JH7110_AXI_CFG0_DEC_CLK_HIFI4       85
+#define JH7110_AXIMEM2_128B_CLK_AXI         86
+#define JH7110_QSPI_CLK_AHB                 87
+#define JH7110_QSPI_CLK_APB                 88
+#define JH7110_QSPI_REF_SRC                 89
+#define JH7110_QSPI_CLK_REF                 90
+#define JH7110_SDIO0_CLK_AHB                91
+#define JH7110_SDIO1_CLK_AHB                92
+#define JH7110_SDIO0_CLK_SDCARD             93
+#define JH7110_SDIO1_CLK_SDCARD             94
+#define JH7110_USB_125M                     95
+#define JH7110_NOC_BUS_CLK_STG_AXI          96
+#define JH7110_GMAC5_CLK_AHB                97
+#define JH7110_GMAC5_CLK_AXI                98
+#define JH7110_GMAC_SRC                     99
+#define JH7110_GMAC1_GTXCLK                 100
+#define JH7110_GMAC1_RMII_RTX               101
+#define JH7110_GMAC5_CLK_PTP                102
+#define JH7110_GMAC5_CLK_RX                 103
+#define JH7110_GMAC5_CLK_RX_INV             104
+#define JH7110_GMAC5_CLK_TX                 105
+#define JH7110_GMAC5_CLK_TX_INV             106
+#define JH7110_GMAC1_GTXC                   107
+#define JH7110_GMAC0_GTXCLK                 108
+#define JH7110_GMAC0_PTP                    109
+#define JH7110_GMAC_PHY                     110
+#define JH7110_GMAC0_GTXC                   111
+#define JH7110_SYS_IOMUX_PCLK               112
+#define JH7110_MAILBOX_CLK_APB              113
+#define JH7110_INT_CTRL_CLK_APB             114
+#define JH7110_CAN0_CTRL_CLK_APB            115
+#define JH7110_CAN0_CTRL_CLK_TIMER          116
+#define JH7110_CAN0_CTRL_CLK_CAN            117
+#define JH7110_CAN1_CTRL_CLK_APB            118
+#define JH7110_CAN1_CTRL_CLK_TIMER          119
+#define JH7110_CAN1_CTRL_CLK_CAN            120
+#define JH7110_PWM_CLK_APB                  121
+#define JH7110_DSKIT_WDT_CLK_APB            122
+#define JH7110_DSKIT_WDT_CLK_WDT            123
+#define JH7110_TIMER_CLK_APB                124
+#define JH7110_TIMER_CLK_TIMER0             125
+#define JH7110_TIMER_CLK_TIMER1             126
+#define JH7110_TIMER_CLK_TIMER2             127
+#define JH7110_TIMER_CLK_TIMER3             128
+#define JH7110_TEMP_SENSOR_CLK_APB          129
+#define JH7110_TEMP_SENSOR_CLK_TEMP         130
+#define JH7110_SPI0_CLK_APB                 131
+#define JH7110_SPI1_CLK_APB                 132
+#define JH7110_SPI2_CLK_APB                 133
+#define JH7110_SPI3_CLK_APB                 134
+#define JH7110_SPI4_CLK_APB                 135
+#define JH7110_SPI5_CLK_APB                 136
+#define JH7110_SPI6_CLK_APB                 137
+#define JH7110_I2C0_CLK_APB                 138
+#define JH7110_I2C1_CLK_APB                 139
+#define JH7110_I2C2_CLK_APB                 140
+#define JH7110_I2C3_CLK_APB                 141
+#define JH7110_I2C4_CLK_APB                 142
+#define JH7110_I2C5_CLK_APB                 143
+#define JH7110_I2C6_CLK_APB                 144
+#define JH7110_UART0_CLK_APB                145
+#define JH7110_UART0_CLK_CORE               146
+#define JH7110_UART1_CLK_APB                147
+#define JH7110_UART1_CLK_CORE               148
+#define JH7110_UART2_CLK_APB                149
+#define JH7110_UART2_CLK_CORE               150
+#define JH7110_UART3_CLK_APB                151
+#define JH7110_UART3_CLK_CORE               152
+#define JH7110_UART4_CLK_APB                153
+#define JH7110_UART4_CLK_CORE               154
+#define JH7110_UART5_CLK_APB                155
+#define JH7110_UART5_CLK_CORE               156
+#define JH7110_PWMDAC_CLK_APB               157
+#define JH7110_PWMDAC_CLK_CORE              158
+#define JH7110_SPDIF_CLK_APB                159
+#define JH7110_SPDIF_CLK_CORE               160
+#define JH7110_I2STX0_4CHCLK_APB            161
+#define JH7110_I2STX_4CH0_BCLK_MST          162
+#define JH7110_I2STX_4CH0_BCLK_MST_INV      163
+#define JH7110_I2STX_4CH0_LRCK_MST          164
+#define JH7110_I2STX0_4CHBCLK               165
+#define JH7110_I2STX0_4CHBCLK_N             166
+#define JH7110_I2STX0_4CHLRCK               167
+#define JH7110_I2STX1_4CHCLK_APB            168
+#define JH7110_I2STX_4CH1_BCLK_MST          169
+#define JH7110_I2STX_4CH1_BCLK_MST_INV      170
+#define JH7110_I2STX_4CH1_LRCK_MST          171
+#define JH7110_I2STX1_4CHBCLK               172
+#define JH7110_I2STX1_4CHBCLK_N             173
+#define JH7110_I2STX1_4CHLRCK               174
+#define JH7110_I2SRX0_3CH_CLK_APB           175
+#define JH7110_I2SRX_3CH_BCLK_MST           176
+#define JH7110_I2SRX_3CH_BCLK_MST_INV       177
+#define JH7110_I2SRX_3CH_LRCK_MST           178
+#define JH7110_I2SRX0_3CH_BCLK              179
+#define JH7110_I2SRX0_3CH_BCLK_N            180
+#define JH7110_I2SRX0_3CH_LRCK              181
+#define JH7110_PDM_CLK_DMIC                 182
+#define JH7110_PDM_CLK_APB                  183
+#define JH7110_TDM_CLK_AHB                  184
+#define JH7110_TDM_CLK_APB                  185
+#define JH7110_TDM_INTERNAL                 186
+#define JH7110_TDM_CLK_TDM                  187
+#define JH7110_TDM_CLK_TDM_N                188
+#define JH7110_JTAG_CERTIFICATION_TRNG_CLK  189
+
+#define JH7110_CLK_SYS_REG_END  190
+
+/* stg regisger */
+#define JH7110_HIFI4_CLK_CORE          190
+#define JH7110_USB0_CLK_USB_APB        191
+#define JH7110_USB0_CLK_UTMI_APB       192
+#define JH7110_USB0_CLK_AXI            193
+#define JH7110_USB0_CLK_LPM            194
+#define JH7110_USB0_CLK_STB            195
+#define JH7110_USB0_CLK_APP_125        196
+#define JH7110_USB0_REFCLK             197
+#define JH7110_PCIE0_CLK_AXI_MST0      198
+#define JH7110_PCIE0_CLK_APB           199
+#define JH7110_PCIE0_CLK_TL            200
+#define JH7110_PCIE1_CLK_AXI_MST0      201
+#define JH7110_PCIE1_CLK_APB           202
+#define JH7110_PCIE1_CLK_TL            203
+#define JH7110_PCIE01_SLV_DEC_MAINCLK  204
+#define JH7110_SEC_HCLK                205
+#define JH7110_SEC_MISCAHB_CLK         206
+#define JH7110_STG_MTRX_GRP0_CLK_MAIN  207
+#define JH7110_STG_MTRX_GRP0_CLK_BUS   208
+#define JH7110_STG_MTRX_GRP0_CLK_STG   209
+#define JH7110_STG_MTRX_GRP1_CLK_MAIN  210
+#define JH7110_STG_MTRX_GRP1_CLK_BUS   211
+#define JH7110_STG_MTRX_GRP1_CLK_STG   212
+#define JH7110_STG_MTRX_GRP1_CLK_HIFI  213
+#define JH7110_E2_RTC_CLK              214
+#define JH7110_E2_CLK_CORE             215
+#define JH7110_E2_CLK_DBG              216
+#define JH7110_DMA1P_CLK_AXI           217
+#define JH7110_DMA1P_CLK_AHB           218
+
+#define JH7110_CLK_STG_REG_END  219
+
+/* aon regisger */
+#define JH7110_OSC_DIV4             219
+#define JH7110_AON_APB_FUNC         220
+#define JH7110_U0_GMAC5_CLK_AHB     221
+#define JH7110_U0_GMAC5_CLK_AXI     222
+#define JH7110_GMAC0_RMII_RTX       223
+#define JH7110_U0_GMAC5_CLK_TX      224
+#define JH7110_U0_GMAC5_CLK_TX_INV  225
+#define JH7110_U0_GMAC5_CLK_RX      226
+#define JH7110_U0_GMAC5_CLK_RX_INV  227
+#define JH7110_OTPC_CLK_APB         228
+#define JH7110_RTC_HMS_CLK_APB      229
+#define JH7110_RTC_INTERNAL         230
+#define JH7110_RTC_HMS_CLK_OSC32K   231
+#define JH7110_RTC_HMS_CLK_CAL      232
+
+#define JH7110_CLK_REG_END  233
+
+/* sys other */
+#define JH7110_PLL0_OUT                      233
+#define JH7110_PLL1_OUT                      234
+#define JH7110_PLL2_OUT                      235
+#define JH7110_AON_APB                       236
+#define JH7110_RESET1_CTRL_CLK_SRC           237
+#define JH7110_DDR_ROOT                      238
+#define JH7110_VDEC_ROOT                     239
+#define JH7110_VENC_ROOT                     240
+#define JH7110_VOUT_ROOT                     241
+#define JH7110_GMACUSB_ROOT                  242
+#define JH7110_PCLK2_MUX_FUNC_PCLK           243
+#define JH7110_PCLK2_MUX_BIST_PCLK           244
+#define JH7110_APB_BUS                       245
+#define JH7110_APB12                         246
+#define JH7110_AXI_CFG1                      247
+#define JH7110_PLL_WRAP_CRG_GCLK0            248
+#define JH7110_PLL_WRAP_CRG_GCLK1            249
+#define JH7110_PLL_WRAP_CRG_GCLK2            250
+#define JH7110_JTAG2APB_PCLK                 251
+#define JH7110_U7_BUS_CLK                    252
+#define JH7110_U7_IRQ_SYNC_BUS_CLK           253
+#define JH7110_NOC_BUS_CLK2_CPU_AXI          254
+#define JH7110_NOC_BUS_CLK_APB_BUS           255
+#define JH7110_NOC_BUS_CLK2_APB_BUS          256
+#define JH7110_NOC_BUS_CLK2_AXICFG0_AXI      257
+#define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS     258
+#define JH7110_DDR_CLK_OSC                   259
+#define JH7110_DDR_CLK_APB                   260
+#define JH7110_NOC_BUS_CLK_DDRC              261
+#define JH7110_NOC_BUS_CLK2_DDRC             262
+#define JH7110_SYS_AHB_DEC_CLK_AHB           263
+#define JH7110_STG_AHB_DEC_CLK_AHB           264
+#define JH7110_NOC_BUS_CLK2_GPU_AXI          265
+#define JH7110_ISP_TOP_CLK_DVP               266
+#define JH7110_NOC_BUS_CLK2_ISP_AXI          267
+#define JH7110_ISP_TOP_CLK_BIST_APB          268
+#define JH7110_NOC_BUS_CLK2_DISP_AXI         269
+#define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK     270
+#define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS    271
+#define JH7110_VOUT_TOP_CLK_HDMIPHY_REF      272
+#define JH7110_VOUT_TOP_BIST_PCLK            273
+#define JH7110_AXIMEM0_128B_CLK_AXI          274
+#define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI     275
+#define JH7110_NOC_BUS_CLK2_VDEC_AXI         276
+#define JH7110_AXIMEM1_128B_CLK_AXI          277
+#define JH7110_VENC_INTSRAM_CLK_VENC_AXI     278
+#define JH7110_NOC_BUS_CLK2_VENC_AXI         279
+#define JH7110_SRAM_CLK_ROM                  280
+#define JH7110_NOC_BUS_CLK2_STG_AXI          281
+#define JH7110_GMAC5_CLK_RMII                282
+#define JH7110_AON_AHB                       283
+#define JH7110_SYS_CRG_PCLK                  284
+#define JH7110_SYS_SYSCON_PCLK               285
+#define JH7110_SPI0_CLK_CORE                 286
+#define JH7110_SPI1_CLK_CORE                 287
+#define JH7110_SPI2_CLK_CORE                 288
+#define JH7110_SPI3_CLK_CORE                 289
+#define JH7110_SPI4_CLK_CORE                 290
+#define JH7110_SPI5_CLK_CORE                 291
+#define JH7110_SPI6_CLK_CORE                 292
+#define JH7110_I2C0_CLK_CORE                 293
+#define JH7110_I2C1_CLK_CORE                 294
+#define JH7110_I2C2_CLK_CORE                 295
+#define JH7110_I2C3_CLK_CORE                 296
+#define JH7110_I2C4_CLK_CORE                 297
+#define JH7110_I2C5_CLK_CORE                 298
+#define JH7110_I2C6_CLK_CORE                 299
+#define JH7110_I2STX_BCLK_MST                300
+#define JH7110_I2STX_LRCK_MST                301
+#define JH7110_I2SRX_BCLK_MST                302
+#define JH7110_I2SRX_LRCK_MST                303
+#define JH7110_PDM_CLK_DMIC0_BCLK_SLV        304
+#define JH7110_PDM_CLK_DMIC0_LRCK_SLV        305
+#define JH7110_PDM_CLK_DMIC1_BCLK_SLV        306
+#define JH7110_PDM_CLK_DMIC1_LRCK_SLV        307
+#define JH7110_TDM_CLK_MST                   308
+#define JH7110_AHB2APB_CLK_AHB               309
+#define JH7110_P2P_ASYNC_CLK_APBS            310
+#define JH7110_P2P_ASYNC_CLK_APBM            311
+#define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK     312
+#define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK  313
+#define JH7110_E2_DEBUG_SYSTEMJTAG_TCK       314
+#define JH7110_JTAG_CERTIFICATION_TCK        315
+#define JH7110_SEC_SKP_CLK                   316
+#define JH7110_U2_PCLK_MUX_PCLK              317
+
+#define JH7110_CLK_SYS_END  318
+
+/* stg other */
+#define JH7110_PCIE0_CLK_AXI_SLV0    318
+#define JH7110_PCIE0_CLK_AXI_SLV     319
+#define JH7110_PCIE0_CLK_OSC         320
+#define JH7110_PCIE1_CLK_AXI_SLV0    321
+#define JH7110_PCIE1_CLK_AXI_SLV     322
+#define JH7110_PCIE1_CLK_OSC         323
+#define JH7110_E2_IRQ_SYNC_CLK_CORE  324
+#define JH7110_STG_CRG_PCLK          325
+#define JH7110_STG_SYSCON_PCLK       326
+
+#define JH7110_CLK_STG_END  327
+
+/* aon other */
+#define JH7110_U0_GMAC5_CLK_PTP      327
+#define JH7110_U0_GMAC5_CLK_RMII     328
+#define JH7110_AON_SYSCON_PCLK       329
+#define JH7110_AON_IOMUX_PCLK        330
+#define JH7110_AON_CRG_PCLK          331
+#define JH7110_PMU_CLK_APB           332
+#define JH7110_PMU_CLK_WKUP          333
+#define JH7110_RTC_HMS_CLK_OSC32K_G  334
+#define JH7110_32K_OUT               335
+#define JH7110_RESET0_CTRL_CLK_SRC   336
+/* aon other and source */
+#define JH7110_PCLK_MUX_FUNC_PCLK  337
+#define JH7110_PCLK_MUX_BIST_PCLK  338
+
+#define JH7110_CLK_END  339
+
+/* sys external clocks */
+#define JH7110_OSC               (JH7110_CLK_END + 0)
+#define JH7110_GMAC1_RMII_REFIN  (JH7110_CLK_END + 1)
+#define JH7110_GMAC1_RGMII_RXIN  (JH7110_CLK_END + 2)
+#define JH7110_I2STX_BCLK_EXT    (JH7110_CLK_END + 3)
+#define JH7110_I2STX_LRCK_EXT    (JH7110_CLK_END + 4)
+#define JH7110_I2SRX_BCLK_EXT    (JH7110_CLK_END + 5)
+#define JH7110_I2SRX_LRCK_EXT    (JH7110_CLK_END + 6)
+#define JH7110_TDM_EXT           (JH7110_CLK_END + 7)
+#define JH7110_MCLK_EXT          (JH7110_CLK_END + 8)
+#define JH7110_JTAG_TCK_INNER    (JH7110_CLK_END + 9)
+#define JH7110_BIST_APB          (JH7110_CLK_END + 10)
+
+/* stg external clocks */
+#define JH7110_STG_APB  (JH7110_CLK_END + 11)
+
+/* aon external clocks */
+#define JH7110_GMAC0_RMII_REFIN  (JH7110_CLK_END + 12)
+#define JH7110_GMAC0_RGMII_RXIN  (JH7110_CLK_END + 13)
+#define JH7110_CLK_RTC           (JH7110_CLK_END + 14)
+
+#endif /* __DT_BINDINGS_JH7110_CLK_GEN_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h
new file mode 100644
index 000000000000..756c51529a3a
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h
@@ -0,0 +1,57 @@
+/** @file
+  This header provide all JH7110 clock isp device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_CLK_ISP_H__
+#define __DT_BINDINGS_JH7110_CLK_ISP_H__
+
+/* register */
+#define JH7110_DOM4_APB_FUNC               0
+#define JH7110_MIPI_RX0_PXL                1
+#define JH7110_DVP_INV                     2
+#define JH7110_U0_M31DPHY_CFGCLK_IN        3
+#define JH7110_U0_M31DPHY_REFCLK_IN        4
+#define JH7110_U0_M31DPHY_TXCLKESC_LAN0    5
+#define JH7110_U0_VIN_PCLK                 6
+#define JH7110_U0_VIN_SYS_CLK              7
+#define JH7110_U0_VIN_PIXEL_CLK_IF0        8
+#define JH7110_U0_VIN_PIXEL_CLK_IF1        9
+#define JH7110_U0_VIN_PIXEL_CLK_IF2        10
+#define JH7110_U0_VIN_PIXEL_CLK_IF3        11
+#define JH7110_U0_VIN_CLK_P_AXIWR          12
+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C  13
+
+#define JH7110_CLK_ISP_REG_END  14
+
+/* other */
+#define JH7110_U3_PCLK_MUX_FUNC_PCLK                14
+#define JH7110_U3_PCLK_MUX_BIST_PCLK                15
+#define JH7110_DOM4_APB                             16
+#define JH7110_U0_VIN_PCLK_FREE                     17
+#define JH7110_U0_VIN_CLK_P_AXIRD                   18
+#define JH7110_U0_VIN_ACLK                          19
+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN  20
+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2      21
+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP         22
+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P           23
+#define JH7110_U0_CRG_PCLK                          24
+#define JH7110_U0_SYSCON_PCLK                       25
+#define JH7110_U0_M31DPHY_APBCFG_PCLK               26
+#define JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB       27
+#define JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK    28
+#define JH7110_U3_PCLK_MUX_PCLK                     29
+
+#define JH7110_CLK_ISP_END  30
+
+/* external clocks */
+#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN  (JH7110_CLK_ISP_END + 0)
+#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN     (JH7110_CLK_ISP_END + 1)
+#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN    (JH7110_CLK_ISP_END + 2)
+#define JH7110_ISP_TOP_CLK_DVP_CLKGEN         (JH7110_CLK_ISP_END + 3)
+
+#endif /* __DT_BINDINGS_JH7110_CLK_ISP_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h
new file mode 100644
index 000000000000..9775d9eadbdd
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h
@@ -0,0 +1,68 @@
+/** @file
+  This header provide all JH7110 clock vout device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_CLK_VOUT_H__
+#define __DT_BINDINGS_JH7110_CLK_VOUT_H__
+
+/* register */
+#define JH7110_APB                       0
+#define JH7110_DC8200_PIX0               1
+#define JH7110_DSI_SYS                   2
+#define JH7110_TX_ESC                    3
+#define JH7110_U0_DC8200_CLK_AXI         4
+#define JH7110_U0_DC8200_CLK_CORE        5
+#define JH7110_U0_DC8200_CLK_AHB         6
+#define JH7110_U0_DC8200_CLK_PIX0        7
+#define JH7110_U0_DC8200_CLK_PIX1        8
+#define JH7110_DOM_VOUT_TOP_LCD_CLK      9
+#define JH7110_U0_CDNS_DSITX_CLK_APB     10
+#define JH7110_U0_CDNS_DSITX_CLK_SYS     11
+#define JH7110_U0_CDNS_DSITX_CLK_DPI     12
+#define JH7110_U0_CDNS_DSITX_CLK_TXESC   13
+#define JH7110_U0_MIPITX_DPHY_CLK_TXESC  14
+#define JH7110_U0_HDMI_TX_CLK_MCLK       15
+#define JH7110_U0_HDMI_TX_CLK_BCLK       16
+#define JH7110_U0_HDMI_TX_CLK_SYS        17
+
+#define JH7110_CLK_VOUT_REG_END  18
+
+/* other */
+#define JH7110_DISP_ROOT     18
+#define JH7110_DISP_AXI      19
+#define JH7110_DISP_AHB      20
+#define JH7110_HDMI_PHY_REF  21
+#define JH7110_HDMITX0_MCLK  22
+#define JH7110_HDMITX0_SCK   23
+
+#define JH7110_MIPI_DPHY_REF                          24
+#define JH7110_U0_PCLK_MUX_BIST_PCLK                  25
+#define JH7110_DISP_APB                               26
+#define JH7110_U0_PCLK_MUX_FUNC_PCLK                  27
+#define JH7110_U0_DOM_VOUT_CRG_PCLK                   28
+#define JH7110_U0_DOM_VOUT_SYSCON_PCLK                29
+#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB  30
+#define JH7110_U0_AHB2APB_CLK_AHB                     31
+#define JH7110_U0_P2P_ASYNC_CLK_APBS                  32
+#define JH7110_U0_CDNS_DSITX_CLK_RXESC                33
+#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS             34
+#define JH7110_U0_MIPITX_DPHY_CLK_SYS                 35
+#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF            36
+#define JH7110_U0_MIPITX_APBIF_PCLK                   37
+#define JH7110_HDMI_TX_CLK_REF                        38
+#define JH7110_U0_DC8200_CLK_PIX0_OUT                 39
+#define JH7110_U0_DC8200_CLK_PIX1_OUT                 40
+
+#define JH7110_CLK_VOUT_END  41
+
+/* external clocks */
+#define JH7110_HDMITX0_PIXELCLK      (JH7110_CLK_VOUT_END + 0)
+#define JH7110_MIPITX_DPHY_RXESC     (JH7110_CLK_VOUT_END + 1)
+#define JH7110_MIPITX_DPHY_TXBYTEHS  (JH7110_CLK_VOUT_END + 2)
+
+#endif /* __DT_BINDINGS_JH7110_CLK_VOUT_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h
new file mode 100755
index 000000000000..0df2e6991548
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h
@@ -0,0 +1,1573 @@
+/** @file
+  This header provide all JH7110 pin control device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_PIN_CTRL_H__
+#define __DT_BINDINGS_JH7110_PIN_CTRL_H__
+
+/************************aon_iomux***************************/
+// aon_iomux pin
+#define PAD_TESTEN      0
+#define PAD_RGPIO0      1
+#define PAD_RGPIO1      2
+#define PAD_RGPIO2      3
+#define PAD_RGPIO3      4
+#define PAD_RSTN        5
+#define PAD_GMAC0_MDC   6
+#define PAD_GMAC0_MDIO  7
+#define PAD_GMAC0_RXD0  8
+#define PAD_GMAC0_RXD1  9
+#define PAD_GMAC0_RXD2  10
+#define PAD_GMAC0_RXD3  11
+#define PAD_GMAC0_RXDV  12
+#define PAD_GMAC0_RXC   13
+#define PAD_GMAC0_TXD0  14
+#define PAD_GMAC0_TXD1  15
+#define PAD_GMAC0_TXD2  16
+#define PAD_GMAC0_TXD3  17
+#define PAD_GMAC0_TXEN  18
+#define PAD_GMAC0_TXC   19
+
+// aon_iomux dout
+#define GPO_AON_IOMUX_U0_AON_CRG_CLK_32K_OUT  2
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_4    3
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_5    4
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_6    5
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_7    6
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK0    7
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK1    8
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK2    9
+// aon_iomux doen
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_4  2
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_5  3
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_6  4
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_7  5
+// aon_iomux gin
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0  0
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1  1
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2  2
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3  3
+
+// ===============================GPIO_OUT_SELECT=======================================
+// gpio_out config:
+// every define below is a couple of signal and signal idx
+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_out
+// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOUT_CFG([signal])
+// e.g. SET_AON_IOMUX_GPO0_DOUT_CFG(__LOW)
+// =====================================================================================
+#define __LOW                   0
+#define __HIGH                  1
+#define U0_AON_CRG_CLK_32K_OUT  2
+#define U0_PWM_8CH_PTC_PWM_4    3
+#define U0_PWM_8CH_PTC_PWM_5    4
+#define U0_PWM_8CH_PTC_PWM_6    5
+#define U0_PWM_8CH_PTC_PWM_7    6
+#define U0_SYS_CRG_CLK_GCLK0    7
+#define U0_SYS_CRG_CLK_GCLK1    8
+#define U0_SYS_CRG_CLK_GCLK2    9
+
+// ===============================GPIO_OEN_SELECT=======================================
+// gpio_oen config:
+// every define below is a couple of signal and signal idx
+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_oen
+// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOEN_CFG([signal])
+// e.g. SET_AON_IOMUX_GPO0_DOEN_CFG(__LOW)
+// =====================================================================================
+#define __LOW                  0
+#define __HIGH                 1
+#define U0_PWM_8CH_PTC_OE_N_4  2
+#define U0_PWM_8CH_PTC_OE_N_5  3
+#define U0_PWM_8CH_PTC_OE_N_6  4
+#define U0_PWM_8CH_PTC_OE_N_7  5
+
+// aon_iomux gmac0 syscon
+#define AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR   (0x58U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR   (0x5cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR   (0x60U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR  (0x64U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR  (0x68U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR  (0x6cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR  (0x70U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR  (0x74U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR  (0x78U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR  (0x7cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR  (0x80U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR  (0x84U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR  (0x88U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR  (0x8cU)
+
+#define PADCFG_PAD_GMAC0_MDC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR
+#define PADCFG_PAD_GMAC0_MDIO_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR
+#define PADCFG_PAD_GMAC0_RXD0_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR
+#define PADCFG_PAD_GMAC0_RXD1_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR
+#define PADCFG_PAD_GMAC0_RXD2_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR
+#define PADCFG_PAD_GMAC0_RXD3_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR
+#define PADCFG_PAD_GMAC0_RXDV_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR
+#define PADCFG_PAD_GMAC0_RXC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR
+#define PADCFG_PAD_GMAC0_TXD0_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR
+#define PADCFG_PAD_GMAC0_TXD1_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR
+#define PADCFG_PAD_GMAC0_TXD2_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR
+#define PADCFG_PAD_GMAC0_TXD3_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR
+#define PADCFG_PAD_GMAC0_TXEN_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR
+#define PADCFG_PAD_GMAC0_TXC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR
+
+// aon_iomux func sel
+#define AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR  (0x90U)
+#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT        0x0U
+#define PAD_GMAC0_RXC_FUNC_SEL_MASK         0x3U
+
+#define PAD_GMAC0_RXC_FUNC_SEL             \
+        AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR \
+        PAD_GMAC0_RXC_FUNC_SEL_SHIFT       \
+        PAD_GMAC0_RXC_FUNC_SEL_MASK
+/************************aon_iomux***************************/
+
+/************************sys_iomux***************************/
+// sys_iomux pin
+#define PAD_GPIO0       0
+#define PAD_GPIO1       1
+#define PAD_GPIO2       2
+#define PAD_GPIO3       3
+#define PAD_GPIO4       4
+#define PAD_GPIO5       5
+#define PAD_GPIO6       6
+#define PAD_GPIO7       7
+#define PAD_GPIO8       8
+#define PAD_GPIO9       9
+#define PAD_GPIO10      10
+#define PAD_GPIO11      11
+#define PAD_GPIO12      12
+#define PAD_GPIO13      13
+#define PAD_GPIO14      14
+#define PAD_GPIO15      15
+#define PAD_GPIO16      16
+#define PAD_GPIO17      17
+#define PAD_GPIO18      18
+#define PAD_GPIO19      19
+#define PAD_GPIO20      20
+#define PAD_GPIO21      21
+#define PAD_GPIO22      22
+#define PAD_GPIO23      23
+#define PAD_GPIO24      24
+#define PAD_GPIO25      25
+#define PAD_GPIO26      26
+#define PAD_GPIO27      27
+#define PAD_GPIO28      28
+#define PAD_GPIO29      29
+#define PAD_GPIO30      30
+#define PAD_GPIO31      31
+#define PAD_GPIO32      32
+#define PAD_GPIO33      33
+#define PAD_GPIO34      34
+#define PAD_GPIO35      35
+#define PAD_GPIO36      36
+#define PAD_GPIO37      37
+#define PAD_GPIO38      38
+#define PAD_GPIO39      39
+#define PAD_GPIO40      40
+#define PAD_GPIO41      41
+#define PAD_GPIO42      42
+#define PAD_GPIO43      43
+#define PAD_GPIO44      44
+#define PAD_GPIO45      45
+#define PAD_GPIO46      46
+#define PAD_GPIO47      47
+#define PAD_GPIO48      48
+#define PAD_GPIO49      49
+#define PAD_GPIO50      50
+#define PAD_GPIO51      51
+#define PAD_GPIO52      52
+#define PAD_GPIO53      53
+#define PAD_GPIO54      54
+#define PAD_GPIO55      55
+#define PAD_GPIO56      56
+#define PAD_GPIO57      57
+#define PAD_GPIO58      58
+#define PAD_GPIO59      59
+#define PAD_GPIO60      60
+#define PAD_GPIO61      61
+#define PAD_GPIO62      62
+#define PAD_GPIO63      63
+#define PAD_SD0_CLK     64
+#define PAD_SD0_CMD     65
+#define PAD_SD0_DATA0   66
+#define PAD_SD0_DATA1   67
+#define PAD_SD0_DATA2   68
+#define PAD_SD0_DATA3   69
+#define PAD_SD0_DATA4   70
+#define PAD_SD0_DATA5   71
+#define PAD_SD0_DATA6   72
+#define PAD_SD0_DATA7   73
+#define PAD_SD0_STRB    74
+#define PAD_GMAC1_MDC   75
+#define PAD_GMAC1_MDIO  76
+#define PAD_GMAC1_RXD0  77
+#define PAD_GMAC1_RXD1  78
+#define PAD_GMAC1_RXD2  79
+#define PAD_GMAC1_RXD3  80
+#define PAD_GMAC1_RXDV  81
+#define PAD_GMAC1_RXC   82
+#define PAD_GMAC1_TXD0  83
+#define PAD_GMAC1_TXD1  84
+#define PAD_GMAC1_TXD2  85
+#define PAD_GMAC1_TXD3  86
+#define PAD_GMAC1_TXEN  87
+#define PAD_GMAC1_TXC   88
+#define PAD_QSPI_SCLK   89
+#define PAD_QSPI_CSn0   90
+#define PAD_QSPI_DATA0  91
+#define PAD_QSPI_DATA1  92
+#define PAD_QSPI_DATA2  93
+#define PAD_QSPI_DATA3  94
+
+// oen and out idx is for chosen, in idx is for reg offset
+#define GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT                    2
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_STBY                            3
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT                    4
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT                5
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TXD                             6
+#define GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO                    7
+#define GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1                           8
+#define GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO                        9
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT  10
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT  11
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT  12
+#define GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES                        13
+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A                      14
+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A                     15
+#define GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER                   16
+#define GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN                    17
+#define GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N              18
+#define GPO_SYS_IOMUX_U0_DW_SDIO_RST_N                            19
+#define GPO_SYS_IOMUX_U0_DW_UART_SOUT                             20
+#define GPO_SYS_IOMUX_U0_HIFI4_JTDO                               21
+#define GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO                   22
+#define GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK                       23
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0                        24
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1                        25
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2                        26
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3                        27
+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT                28
+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT               29
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT                        30
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT                        31
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD                           32
+#define GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY                     33
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST                   34
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST                   35
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST                   36
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST                   37
+#define GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT                         38
+#define GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST                      39
+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT                    40
+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD                        41
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0       42
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1       43
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2       44
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3       45
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF          46
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_STBY                            47
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT                    48
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT                49
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TXD                             50
+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A                      51
+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A                     52
+#define GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER                   53
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN                    54
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT                         55
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N              56
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT                         57
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0                      58
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1                      59
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2                      60
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3                      61
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4                      62
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5                      63
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6                      64
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7                      65
+#define GPO_SYS_IOMUX_U1_DW_SDIO_RST_N                            66
+#define GPO_SYS_IOMUX_U1_DW_UART_RTS_N                            67
+#define GPO_SYS_IOMUX_U1_DW_UART_SOUT                             68
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0                           69
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1                           70
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2                           71
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3                           72
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT                        73
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT                        74
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD                           75
+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A                      76
+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A                     77
+#define GPO_SYS_IOMUX_U2_DW_UART_RTS_N                            78
+#define GPO_SYS_IOMUX_U2_DW_UART_SOUT                             79
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT                        80
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT                        81
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD                           82
+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A                      83
+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A                     84
+#define GPO_SYS_IOMUX_U3_DW_UART_SOUT                             85
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT                        86
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT                        87
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD                           88
+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A                      89
+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A                     90
+#define GPO_SYS_IOMUX_U4_DW_UART_RTS_N                            91
+#define GPO_SYS_IOMUX_U4_DW_UART_SOUT                             92
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT                        93
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT                        94
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD                           95
+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A                      96
+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A                     97
+#define GPO_SYS_IOMUX_U5_DW_UART_RTS_N                            98
+#define GPO_SYS_IOMUX_U5_DW_UART_SOUT                             99
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT                        100
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT                        101
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD                           102
+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A                      103
+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A                     104
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT                        105
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT                        106
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD                           107
+
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN  2
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN  3
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN  4
+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE                         5
+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE                        6
+#define GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN                             7
+#define GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE                8
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0                       9
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1                       10
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2                       11
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3                       12
+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE                        13
+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE                           14
+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE                    15
+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE                     16
+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE                         17
+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE                        18
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN                      19
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0                   20
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1                   21
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2                   22
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3                   23
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4                   24
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5                   25
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6                   26
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7                   27
+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE                        28
+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE                           29
+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE                         30
+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE                        31
+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE                        32
+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE                           33
+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE                         34
+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE                        35
+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE                        36
+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE                           37
+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE                         38
+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE                        39
+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE                        40
+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE                           41
+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE                         42
+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE                        43
+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE                        44
+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE                           45
+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE                         46
+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE                        47
+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE                        48
+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE                           49
+
+#define GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN                    0
+#define GPI_SYS_IOMUX_U0_CAN_CTRL_RXD                            1
+#define GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO                2
+#define GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI                       3
+#define GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN            4
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN  5
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN  6
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN  7
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD         8
+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A                      9
+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A                     10
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N                   11
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N                      12
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT                  13
+#define GPI_SYS_IOMUX_U0_DW_UART_SIN                             14
+#define GPI_SYS_IOMUX_U0_HIFI4_JTCK                              15
+#define GPI_SYS_IOMUX_U0_HIFI4_JTDI                              16
+#define GPI_SYS_IOMUX_U0_HIFI4_JTMS                              17
+#define GPI_SYS_IOMUX_U0_HIFI4_JTRSTN                            18
+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI                  19
+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS                  20
+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN                      21
+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN                      22
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0     23
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1     24
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2     25
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN                        26
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN                        27
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD                          28
+#define GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK                    29
+#define GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK                        30
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV                  31
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV                  32
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV                  33
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV                  34
+#define GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV                     35
+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD                       36
+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN                    37
+#define GPI_SYS_IOMUX_U1_CAN_CTRL_RXD                            38
+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A                      39
+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A                     40
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N                   41
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N                      42
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT                  43
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN                         44
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0                      45
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1                      46
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2                      47
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3                      48
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4                      49
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5                      50
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6                      51
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7                      52
+#define GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE                     53
+#define GPI_SYS_IOMUX_U1_DW_UART_CTS_N                           54
+#define GPI_SYS_IOMUX_U1_DW_UART_SIN                             55
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN                        56
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN                        57
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD                          58
+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A                      59
+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A                     60
+#define GPI_SYS_IOMUX_U2_DW_UART_CTS_N                           61
+#define GPI_SYS_IOMUX_U2_DW_UART_SIN                             62
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN                        63
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN                        64
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD                          65
+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A                      66
+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A                     67
+#define GPI_SYS_IOMUX_U3_DW_UART_SIN                             68
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN                        69
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN                        70
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD                          71
+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A                      72
+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A                     73
+#define GPI_SYS_IOMUX_U4_DW_UART_CTS_N                           74
+#define GPI_SYS_IOMUX_U4_DW_UART_SIN                             75
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN                        76
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN                        77
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD                          78
+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A                      79
+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A                     80
+#define GPI_SYS_IOMUX_U5_DW_UART_CTS_N                           81
+#define GPI_SYS_IOMUX_U5_DW_UART_SIN                             82
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN                        83
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN                        84
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD                          85
+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A                      86
+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A                     87
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN                        88
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN                        89
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD                          90
+
+// gpo(n)_dout signal pool
+#define GPO_LOW   0
+#define GPO_HIGH  1
+#define GPO_CAN0_CTRL_STBY              \
+        GPO_SYS_IOMUX_U0_CAN_CTRL_STBY
+#define GPO_CAN0_CTRL_TST_NEXT_BIT      \
+        GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT  \
+        GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN0_CTRL_TXD               \
+        GPO_SYS_IOMUX_U0_CAN_CTRL_TXD
+#define GPO_CAN1_CTRL_STBY              \
+        GPO_SYS_IOMUX_U1_CAN_CTRL_STBY
+#define GPO_CAN1_CTRL_TST_NEXT_BIT      \
+        GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT  \
+        GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN1_CTRL_TXD               \
+        GPO_SYS_IOMUX_U1_CAN_CTRL_TXD
+#define GPO_CRG0_MCLK_OUT               \
+        GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT
+#define GPO_GMAC0_CLK_PHY               \
+        GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY
+#define GPO_HDMI0_CEC_SDA_OUT           \
+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT
+#define GPO_HDMI0_DDC_SCL_OUT           \
+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT
+#define GPO_HDMI0_DDC_SDA_OUT           \
+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT
+#define GPO_I2C0_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C0_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C1_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C1_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C2_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C2_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C3_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C3_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C4_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C4_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C5_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C5_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C6_IC_CLK_OUT_A           \
+        GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C6_IC_DATA_OUT_A          \
+        GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2SRX0_BCLK_MST             \
+        GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST
+#define GPO_I2SRX0_LRCK_MST             \
+        GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST
+#define GPO_I2STX_4CH1_SDO0             \
+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0
+#define GPO_I2STX_4CH1_SDO1             \
+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1
+#define GPO_I2STX_4CH1_SDO2             \
+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2
+#define GPO_I2STX_4CH1_SDO3             \
+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3
+#define GPO_I2STX0_BCLK_MST             \
+        GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST
+#define GPO_I2STX0_LRCK_MST             \
+        GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST
+#define GPO_JTAG_CPU_CERTIFICATION_TDO  \
+        GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO
+#define GPO_JTAG_DSP_TDO                \
+        GPO_SYS_IOMUX_U0_HIFI4_JTDO
+#define GPO_PDM_4MIC0_DMIC_MCLK         \
+        GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK
+#define GPO_PTC0_PWM_0                  \
+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0
+#define GPO_PTC0_PWM_1                  \
+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1
+#define GPO_PTC0_PWM_2                  \
+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2
+#define GPO_PTC0_PWM_3                  \
+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3
+#define GPO_PWMDAC0_LEFT_OUTPUT         \
+        GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT
+#define GPO_PWMDAC0_RIGHT_OUTPUT        \
+        GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT
+#define GPO_QSPI0_CSN1                  \
+        GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1
+#define GPO_SDIO0_BACK_END_POWER        \
+        GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO0_CARD_POWER_EN         \
+        GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N   \
+        GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO0_RST_N                 \
+        GPO_SYS_IOMUX_U0_DW_SDIO_RST_N
+#define GPO_SDIO1_BACK_END_POWER        \
+        GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO1_CARD_POWER_EN         \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO1_CCLK_OUT              \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT
+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N   \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO1_CCMD_OUT              \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT
+#define GPO_SDIO1_CDATA_OUT_0           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0
+#define GPO_SDIO1_CDATA_OUT_1           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1
+#define GPO_SDIO1_CDATA_OUT_2           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2
+#define GPO_SDIO1_CDATA_OUT_3           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3
+#define GPO_SDIO1_CDATA_OUT_4           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4
+#define GPO_SDIO1_CDATA_OUT_5           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5
+#define GPO_SDIO1_CDATA_OUT_6           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6
+#define GPO_SDIO1_CDATA_OUT_7           \
+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7
+#define GPO_SDIO1_RST_N                 \
+        GPO_SYS_IOMUX_U1_DW_SDIO_RST_N
+#define GPO_SPDIF0_SPDIFO               \
+        GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO
+#define GPO_SPI0_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT
+#define GPO_SPI0_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT
+#define GPO_SPI0_SSPTXD                 \
+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD
+#define GPO_SPI1_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT
+#define GPO_SPI1_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT
+#define GPO_SPI1_SSPTXD                 \
+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD
+#define GPO_SPI2_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT
+#define GPO_SPI2_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT
+#define GPO_SPI2_SSPTXD                 \
+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD
+#define GPO_SPI3_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT
+#define GPO_SPI3_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT
+#define GPO_SPI3_SSPTXD                 \
+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD
+#define GPO_SPI4_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT
+#define GPO_SPI4_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT
+#define GPO_SPI4_SSPTXD                 \
+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD
+#define GPO_SPI5_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT
+#define GPO_SPI5_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT
+#define GPO_SPI5_SSPTXD                 \
+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD
+#define GPO_SPI6_SSPCLKOUT              \
+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT
+#define GPO_SPI6_SSPFSSOUT              \
+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT
+#define GPO_SPI6_SSPTXD                 \
+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD
+#define GPO_TDM0_CLK_MST                \
+        GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST
+#define GPO_TDM0_PCM_SYNCOUT            \
+        GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT
+#define GPO_TDM0_PCM_TXD                \
+        GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD
+#define GPO_U7MC_TRACE0_TDATA_0         \
+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0
+#define GPO_U7MC_TRACE0_TDATA_1         \
+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1
+#define GPO_U7MC_TRACE0_TDATA_2         \
+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2
+#define GPO_U7MC_TRACE0_TDATA_3         \
+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3
+#define GPO_U7MC_TRACE0_TREF            \
+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF
+#define GPO_UART0_SOUT                  \
+        GPO_SYS_IOMUX_U0_DW_UART_SOUT
+#define GPO_UART1_RTS_N                 \
+        GPO_SYS_IOMUX_U1_DW_UART_RTS_N
+#define GPO_UART1_SOUT                  \
+        GPO_SYS_IOMUX_U1_DW_UART_SOUT
+#define GPO_UART2_RTS_N                 \
+        GPO_SYS_IOMUX_U2_DW_UART_RTS_N
+#define GPO_UART2_SOUT                  \
+        GPO_SYS_IOMUX_U2_DW_UART_SOUT
+#define GPO_UART3_SOUT                  \
+        GPO_SYS_IOMUX_U3_DW_UART_SOUT
+#define GPO_UART4_RTS_N                 \
+        GPO_SYS_IOMUX_U4_DW_UART_RTS_N
+#define GPO_UART4_SOUT                  \
+        GPO_SYS_IOMUX_U4_DW_UART_SOUT
+#define GPO_UART5_RTS_N                 \
+        GPO_SYS_IOMUX_U5_DW_UART_RTS_N
+#define GPO_UART5_SOUT                  \
+        GPO_SYS_IOMUX_U5_DW_UART_SOUT
+#define GPO_USB0_DRIVE_VBUS_IO          \
+        GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO
+#define GPO_WAVE511_0_O_UART_TXSOUT     \
+        GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT
+#define GPO_WDT0_WDOGRES                \
+        GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES
+#define GPO_NONE                        \
+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD + 1
+
+// gpo(n)_doen signal pool
+#define OEN_LOW   0
+#define OEN_HIGH  1
+#define OEN_HDMI0_CEC_SDA_OEN               \
+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN
+#define OEN_HDMI0_DDC_SCL_OEN               \
+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN
+#define OEN_HDMI0_DDC_SDA_OEN               \
+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN
+#define OEN_I2C0_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE
+#define OEN_I2C0_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE
+#define OEN_I2C1_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE
+#define OEN_I2C1_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE
+#define OEN_I2C2_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE
+#define OEN_I2C2_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE
+#define OEN_I2C3_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE
+#define OEN_I2C3_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE
+#define OEN_I2C4_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE
+#define OEN_I2C4_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE
+#define OEN_I2C5_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE
+#define OEN_I2C5_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE
+#define OEN_I2C6_IC_CLK_OE                  \
+        GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE
+#define OEN_I2C6_IC_DATA_OE                 \
+        GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE
+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE   \
+        GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE
+#define OEN_JTAG_DSP_TDO_OEN                \
+        GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN
+#define OEN_PTC0_PWM_0_OE_N                 \
+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0
+#define OEN_PTC0_PWM_1_OE_N                 \
+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1
+#define OEN_PTC0_PWM_2_OE_N                 \
+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2
+#define OEN_PTC0_PWM_3_OE_N                 \
+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3
+#define OEN_SDIO1_CCMD_OUT_EN               \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN
+#define OEN_SDIO1_CDATA_OUT_EN_0            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0
+#define OEN_SDIO1_CDATA_OUT_EN_1            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1
+#define OEN_SDIO1_CDATA_OUT_EN_2            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2
+#define OEN_SDIO1_CDATA_OUT_EN_3            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3
+#define OEN_SDIO1_CDATA_OUT_EN_4            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4
+#define OEN_SDIO1_CDATA_OUT_EN_5            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5
+#define OEN_SDIO1_CDATA_OUT_EN_6            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6
+#define OEN_SDIO1_CDATA_OUT_EN_7            \
+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7
+#define OEN_SPI0_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE
+#define OEN_SPI0_NSSPOE                     \
+        GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE
+#define OEN_SPI1_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE
+#define OEN_SPI1_NSSPOE                     \
+        GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE
+#define OEN_SPI2_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE
+#define OEN_SPI2_NSSPOE                     \
+        GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE
+#define OEN_SPI3_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE
+#define OEN_SPI3_NSSPOE                     \
+        GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE
+#define OEN_SPI4_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE
+#define OEN_SPI4_NSSPOE                     \
+        GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE
+#define OEN_SPI5_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE
+#define OEN_SPI5_NSSPOE                     \
+        GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE
+#define OEN_SPI6_NSSPCTLOE                  \
+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE
+#define OEN_SPI6_NSSPOE                     \
+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE
+#define OEN_TDM0_NPCM_SYNCOE                \
+        GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE
+#define OEN_TDM0_NPCM_TXDOE                 \
+        GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE
+#define OEN_NONE                            \
+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1
+
+// sys_iomux gpi din
+#define GPI_CAN0_CTRL_RXD                       \
+        GPI_SYS_IOMUX_U0_CAN_CTRL_RXD
+#define GPI_CAN1_CTRL_RXD                       \
+        GPI_SYS_IOMUX_U1_CAN_CTRL_RXD
+#define GPI_CRG0_EXT_MCLK                       \
+        GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK
+#define GPI_HDMI0_CEC_SDA_IN                    \
+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN
+#define GPI_HDMI0_DDC_SCL_IN                    \
+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN
+#define GPI_HDMI0_DDC_SDA_IN                    \
+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN
+#define GPI_HDMI0_HPD                           \
+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD
+#define GPI_I2C0_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C0_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C1_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C1_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C2_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C2_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C3_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C3_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C4_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C4_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C5_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C5_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C6_IC_CLK_IN_A                    \
+        GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C6_IC_DATA_IN_A                   \
+        GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A
+#define GPI_I2SRX0_BCLK_SLV                     \
+        GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV
+#define GPI_I2SRX0_EXT_SDIN0                    \
+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0
+#define GPI_I2SRX0_EXT_SDIN1                    \
+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1
+#define GPI_I2SRX0_EXT_SDIN2                    \
+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2
+#define GPI_I2SRX0_LRCK_SLV                     \
+        GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV
+#define GPI_I2STX0_BCLK_SLV                     \
+        GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV
+#define GPI_I2STX0_LRCK_SLV                     \
+        GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV
+#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN \
+        GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN
+#define GPI_JTAG_CPU_CERTIFICATION_TCK          \
+        GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK
+#define GPI_JTAG_CPU_CERTIFICATION_TDI          \
+        GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI
+#define GPI_JTAG_CPU_CERTIFICATION_TMS          \
+        GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS
+#define GPI_JTAG_DSP_TCK                        \
+        GPI_SYS_IOMUX_U0_HIFI4_JTCK
+#define GPI_JTAG_DSP_TDI                        \
+        GPI_SYS_IOMUX_U0_HIFI4_JTDI
+#define GPI_JTAG_DSP_TMS                        \
+        GPI_SYS_IOMUX_U0_HIFI4_JTMS
+#define GPI_JTAG_DSP_TRST_N                     \
+        GPI_SYS_IOMUX_U0_HIFI4_JTRSTN
+#define GPI_PDM_4MIC0_DMIC0_DIN                 \
+        GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN
+#define GPI_PDM_4MIC0_DMIC1_DIN                 \
+        GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN
+#define GPI_SDIO0_CARD_DETECT_N                 \
+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N
+#define GPI_SDIO0_CARD_INT_N                    \
+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N
+#define GPI_SDIO0_CARD_WRITE_PRT                \
+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT
+#define GPI_SDIO1_CARD_DETECT_N                 \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N
+#define GPI_SDIO1_CARD_INT_N                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N
+#define GPI_SDIO1_CARD_WRITE_PRT                \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT
+#define GPI_SDIO1_CCMD_IN                       \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN
+#define GPI_SDIO1_CDATA_IN_0                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0
+#define GPI_SDIO1_CDATA_IN_1                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1
+#define GPI_SDIO1_CDATA_IN_2                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2
+#define GPI_SDIO1_CDATA_IN_3                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3
+#define GPI_SDIO1_CDATA_IN_4                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4
+#define GPI_SDIO1_CDATA_IN_5                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5
+#define GPI_SDIO1_CDATA_IN_6                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6
+#define GPI_SDIO1_CDATA_IN_7                    \
+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7
+#define GPI_SDIO1_DATA_STROBE                   \
+        GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE
+#define GPI_SPDIF0_SPDIFI                       \
+        GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI
+#define GPI_SPI0_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN
+#define GPI_SPI0_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN
+#define GPI_SPI0_SSPRXD                         \
+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD
+#define GPI_SPI1_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN
+#define GPI_SPI1_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN
+#define GPI_SPI1_SSPRXD                         \
+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD
+#define GPI_SPI2_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN
+#define GPI_SPI2_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN
+#define GPI_SPI2_SSPRXD                         \
+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD
+#define GPI_SPI3_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN
+#define GPI_SPI3_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN
+#define GPI_SPI3_SSPRXD                         \
+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD
+#define GPI_SPI4_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN
+#define GPI_SPI4_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN
+#define GPI_SPI4_SSPRXD                         \
+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD
+#define GPI_SPI5_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN
+#define GPI_SPI5_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN
+#define GPI_SPI5_SSPRXD                         \
+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD
+#define GPI_SPI6_SSPCLKIN                       \
+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN
+#define GPI_SPI6_SSPFSSIN                       \
+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN
+#define GPI_SPI6_SSPRXD                         \
+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD
+#define GPI_TDM0_CLK_SLV                        \
+        GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV
+#define GPI_TDM0_PCM_RXD                        \
+        GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD
+#define GPI_TDM0_PCM_SYNCIN                     \
+        GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN
+#define GPI_UART0_SIN                           \
+        GPI_SYS_IOMUX_U0_DW_UART_SIN
+#define GPI_UART1_CTS_N                         \
+        GPI_SYS_IOMUX_U1_DW_UART_CTS_N
+#define GPI_UART1_SIN                           \
+        GPI_SYS_IOMUX_U1_DW_UART_SIN
+#define GPI_UART2_CTS_N                         \
+        GPI_SYS_IOMUX_U2_DW_UART_CTS_N
+#define GPI_UART2_SIN                           \
+        GPI_SYS_IOMUX_U2_DW_UART_SIN
+#define GPI_UART3_SIN                           \
+        GPI_SYS_IOMUX_U3_DW_UART_SIN
+#define GPI_UART4_CTS_N                         \
+        GPI_SYS_IOMUX_U4_DW_UART_CTS_N
+#define GPI_UART4_SIN                           \
+        GPI_SYS_IOMUX_U4_DW_UART_SIN
+#define GPI_UART5_CTS_N                         \
+        GPI_SYS_IOMUX_U5_DW_UART_CTS_N
+#define GPI_UART5_SIN                           \
+        GPI_SYS_IOMUX_U5_DW_UART_SIN
+#define GPI_USB0_OVERCURRENT_N_IO               \
+        GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO
+#define GPI_WAVE511_0_I_UART_RXSIN              \
+        GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN
+#define GPI_NONE  GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD
+
+// sys_iomux syscon
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR  (0x24cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR  (0x250U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR  (0x254U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR  (0x258U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR  (0x25cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR  (0x260U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR  (0x264U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR  (0x268U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR  (0x26cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR  (0x270U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR  (0x274U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR  (0x278U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR  (0x27cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR  (0x280U)
+
+#define PADCFG_PAD_GMAC1_MDC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR
+#define PADCFG_PAD_GMAC1_MDIO_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR
+#define PADCFG_PAD_GMAC1_RXD0_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR
+#define PADCFG_PAD_GMAC1_RXD1_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR
+#define PADCFG_PAD_GMAC1_RXD2_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR
+#define PADCFG_PAD_GMAC1_RXD3_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR
+#define PADCFG_PAD_GMAC1_RXDV_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR
+#define PADCFG_PAD_GMAC1_RXC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR
+#define PADCFG_PAD_GMAC1_TXD0_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR
+#define PADCFG_PAD_GMAC1_TXD1_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR
+#define PADCFG_PAD_GMAC1_TXD2_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR
+#define PADCFG_PAD_GMAC1_TXD3_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR
+#define PADCFG_PAD_GMAC1_TXEN_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR
+#define PADCFG_PAD_GMAC1_TXC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR
+
+// sys_iomux func sel setting
+#define SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                 (0x29cU)
+#define PAD_GMAC1_RXC_FUNC_SEL_WIDTH                       0x2U
+#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT                       0x0U
+#define PAD_GMAC1_RXC_FUNC_SEL_MASK                        0x3U
+#define PAD_GPIO10_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO10_FUNC_SEL_SHIFT                          0x2U
+#define PAD_GPIO10_FUNC_SEL_MASK                           0x1CU
+#define PAD_GPIO11_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO11_FUNC_SEL_SHIFT                          0x5U
+#define PAD_GPIO11_FUNC_SEL_MASK                           0xE0U
+#define PAD_GPIO12_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO12_FUNC_SEL_SHIFT                          0x8U
+#define PAD_GPIO12_FUNC_SEL_MASK                           0x700U
+#define PAD_GPIO13_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO13_FUNC_SEL_SHIFT                          0xBU
+#define PAD_GPIO13_FUNC_SEL_MASK                           0x3800U
+#define PAD_GPIO14_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO14_FUNC_SEL_SHIFT                          0xEU
+#define PAD_GPIO14_FUNC_SEL_MASK                           0x1C000U
+#define PAD_GPIO15_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO15_FUNC_SEL_SHIFT                          0x11U
+#define PAD_GPIO15_FUNC_SEL_MASK                           0xE0000U
+#define PAD_GPIO16_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO16_FUNC_SEL_SHIFT                          0x14U
+#define PAD_GPIO16_FUNC_SEL_MASK                           0x700000U
+#define PAD_GPIO17_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO17_FUNC_SEL_SHIFT                          0x17U
+#define PAD_GPIO17_FUNC_SEL_MASK                           0x3800000U
+#define PAD_GPIO18_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO18_FUNC_SEL_SHIFT                          0x1AU
+#define PAD_GPIO18_FUNC_SEL_MASK                           0x1C000000U
+#define PAD_GPIO19_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO19_FUNC_SEL_SHIFT                          0x1DU
+#define PAD_GPIO19_FUNC_SEL_MASK                           0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                 (0x2a0U)
+#define PAD_GPIO20_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO20_FUNC_SEL_SHIFT                          0x0U
+#define PAD_GPIO20_FUNC_SEL_MASK                           0x7U
+#define PAD_GPIO21_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO21_FUNC_SEL_SHIFT                          0x3U
+#define PAD_GPIO21_FUNC_SEL_MASK                           0x38U
+#define PAD_GPIO22_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO22_FUNC_SEL_SHIFT                          0x6U
+#define PAD_GPIO22_FUNC_SEL_MASK                           0x1C0U
+#define PAD_GPIO23_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO23_FUNC_SEL_SHIFT                          0x9U
+#define PAD_GPIO23_FUNC_SEL_MASK                           0xE00U
+#define PAD_GPIO24_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO24_FUNC_SEL_SHIFT                          0xCU
+#define PAD_GPIO24_FUNC_SEL_MASK                           0x7000U
+#define PAD_GPIO25_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO25_FUNC_SEL_SHIFT                          0xFU
+#define PAD_GPIO25_FUNC_SEL_MASK                           0x38000U
+#define PAD_GPIO26_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO26_FUNC_SEL_SHIFT                          0x12U
+#define PAD_GPIO26_FUNC_SEL_MASK                           0x1C0000U
+#define PAD_GPIO27_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO27_FUNC_SEL_SHIFT                          0x15U
+#define PAD_GPIO27_FUNC_SEL_MASK                           0xE00000U
+#define PAD_GPIO28_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO28_FUNC_SEL_SHIFT                          0x18U
+#define PAD_GPIO28_FUNC_SEL_MASK                           0x7000000U
+#define PAD_GPIO29_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO29_FUNC_SEL_SHIFT                          0x1BU
+#define PAD_GPIO29_FUNC_SEL_MASK                           0x38000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                 (0x2a4U)
+#define PAD_GPIO30_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO30_FUNC_SEL_SHIFT                          0x0U
+#define PAD_GPIO30_FUNC_SEL_MASK                           0x7U
+#define PAD_GPIO31_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO31_FUNC_SEL_SHIFT                          0x3U
+#define PAD_GPIO31_FUNC_SEL_MASK                           0x38U
+#define PAD_GPIO32_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO32_FUNC_SEL_SHIFT                          0x6U
+#define PAD_GPIO32_FUNC_SEL_MASK                           0x1C0U
+#define PAD_GPIO33_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO33_FUNC_SEL_SHIFT                          0x9U
+#define PAD_GPIO33_FUNC_SEL_MASK                           0xE00U
+#define PAD_GPIO34_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO34_FUNC_SEL_SHIFT                          0xCU
+#define PAD_GPIO34_FUNC_SEL_MASK                           0x7000U
+#define PAD_GPIO35_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO35_FUNC_SEL_SHIFT                          0xFU
+#define PAD_GPIO35_FUNC_SEL_MASK                           0x18000U
+#define PAD_GPIO36_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO36_FUNC_SEL_SHIFT                          0x11U
+#define PAD_GPIO36_FUNC_SEL_MASK                           0xE0000U
+#define PAD_GPIO37_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO37_FUNC_SEL_SHIFT                          0x14U
+#define PAD_GPIO37_FUNC_SEL_MASK                           0x700000U
+#define PAD_GPIO38_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO38_FUNC_SEL_SHIFT                          0x17U
+#define PAD_GPIO38_FUNC_SEL_MASK                           0x3800000U
+#define PAD_GPIO39_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO39_FUNC_SEL_SHIFT                          0x1AU
+#define PAD_GPIO39_FUNC_SEL_MASK                           0x1C000000U
+#define PAD_GPIO40_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO40_FUNC_SEL_SHIFT                          0x1DU
+#define PAD_GPIO40_FUNC_SEL_MASK                           0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                 (0x2a8U)
+#define PAD_GPIO41_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO41_FUNC_SEL_SHIFT                          0x0U
+#define PAD_GPIO41_FUNC_SEL_MASK                           0x7U
+#define PAD_GPIO42_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO42_FUNC_SEL_SHIFT                          0x3U
+#define PAD_GPIO42_FUNC_SEL_MASK                           0x38U
+#define PAD_GPIO43_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO43_FUNC_SEL_SHIFT                          0x6U
+#define PAD_GPIO43_FUNC_SEL_MASK                           0x1C0U
+#define PAD_GPIO44_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO44_FUNC_SEL_SHIFT                          0x9U
+#define PAD_GPIO44_FUNC_SEL_MASK                           0xE00U
+#define PAD_GPIO45_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO45_FUNC_SEL_SHIFT                          0xCU
+#define PAD_GPIO45_FUNC_SEL_MASK                           0x7000U
+#define PAD_GPIO46_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO46_FUNC_SEL_SHIFT                          0xFU
+#define PAD_GPIO46_FUNC_SEL_MASK                           0x38000U
+#define PAD_GPIO47_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO47_FUNC_SEL_SHIFT                          0x12U
+#define PAD_GPIO47_FUNC_SEL_MASK                           0x1C0000U
+#define PAD_GPIO48_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO48_FUNC_SEL_SHIFT                          0x15U
+#define PAD_GPIO48_FUNC_SEL_MASK                           0xE00000U
+#define PAD_GPIO49_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO49_FUNC_SEL_SHIFT                          0x18U
+#define PAD_GPIO49_FUNC_SEL_MASK                           0x7000000U
+#define PAD_GPIO50_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO50_FUNC_SEL_SHIFT                          0x1BU
+#define PAD_GPIO50_FUNC_SEL_MASK                           0x38000000U
+#define PAD_GPIO51_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO51_FUNC_SEL_SHIFT                          0x1EU
+#define PAD_GPIO51_FUNC_SEL_MASK                           0xC0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                 (0x2acU)
+#define PAD_GPIO52_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO52_FUNC_SEL_SHIFT                          0x0U
+#define PAD_GPIO52_FUNC_SEL_MASK                           0x3U
+#define PAD_GPIO53_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO53_FUNC_SEL_SHIFT                          0x2U
+#define PAD_GPIO53_FUNC_SEL_MASK                           0xCU
+#define PAD_GPIO54_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO54_FUNC_SEL_SHIFT                          0x4U
+#define PAD_GPIO54_FUNC_SEL_MASK                           0x30U
+#define PAD_GPIO55_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO55_FUNC_SEL_SHIFT                          0x6U
+#define PAD_GPIO55_FUNC_SEL_MASK                           0x1C0U
+#define PAD_GPIO56_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO56_FUNC_SEL_SHIFT                          0x9U
+#define PAD_GPIO56_FUNC_SEL_MASK                           0xE00U
+#define PAD_GPIO57_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO57_FUNC_SEL_SHIFT                          0xCU
+#define PAD_GPIO57_FUNC_SEL_MASK                           0x7000U
+#define PAD_GPIO58_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO58_FUNC_SEL_SHIFT                          0xFU
+#define PAD_GPIO58_FUNC_SEL_MASK                           0x38000U
+#define PAD_GPIO59_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO59_FUNC_SEL_SHIFT                          0x12U
+#define PAD_GPIO59_FUNC_SEL_MASK                           0x1C0000U
+#define PAD_GPIO60_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO60_FUNC_SEL_SHIFT                          0x15U
+#define PAD_GPIO60_FUNC_SEL_MASK                           0xE00000U
+#define PAD_GPIO61_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO61_FUNC_SEL_SHIFT                          0x18U
+#define PAD_GPIO61_FUNC_SEL_MASK                           0x7000000U
+#define PAD_GPIO62_FUNC_SEL_WIDTH                          0x3U
+#define PAD_GPIO62_FUNC_SEL_SHIFT                          0x1BU
+#define PAD_GPIO62_FUNC_SEL_MASK                           0x38000000U
+#define PAD_GPIO63_FUNC_SEL_WIDTH                          0x2U
+#define PAD_GPIO63_FUNC_SEL_SHIFT                          0x1EU
+#define PAD_GPIO63_FUNC_SEL_MASK                           0xC0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                 (0x2b0U)
+#define PAD_GPIO6_FUNC_SEL_WIDTH                           0x2U
+#define PAD_GPIO6_FUNC_SEL_SHIFT                           0x0U
+#define PAD_GPIO6_FUNC_SEL_MASK                            0x3U
+#define PAD_GPIO7_FUNC_SEL_WIDTH                           0x3U
+#define PAD_GPIO7_FUNC_SEL_SHIFT                           0x2U
+#define PAD_GPIO7_FUNC_SEL_MASK                            0x1CU
+#define PAD_GPIO8_FUNC_SEL_WIDTH                           0x3U
+#define PAD_GPIO8_FUNC_SEL_SHIFT                           0x5U
+#define PAD_GPIO8_FUNC_SEL_MASK                            0xE0U
+#define PAD_GPIO9_FUNC_SEL_WIDTH                           0x3U
+#define PAD_GPIO9_FUNC_SEL_SHIFT                           0x8U
+#define PAD_GPIO9_FUNC_SEL_MASK                            0x700U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT   0xBU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK    0x3800U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_WIDTH  0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT  0xEU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK   0x1C000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_WIDTH  0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT  0x11U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK   0xE0000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT   0x14U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK    0x700000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT   0x17U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK    0x3800000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT   0x1AU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK    0x1C000000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT   0x1DU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK    0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                 (0x2b4U)
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT   0x0U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK    0x7U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK    0x38U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT   0x6U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK    0x1C0U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT   0x9U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK    0xE00U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_WIDTH   0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT   0xCU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK    0x7000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_WIDTH  0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT  0xFU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK   0x38000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_WIDTH  0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT  0x12U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK   0x1C0000U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_WIDTH                  0x3U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT                  0x15U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK                   0xE00000U
+
+#define PAD_GMAC1_RXC_FUNC_SEL                              \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GMAC1_RXC_FUNC_SEL_SHIFT                        \
+        PAD_GMAC1_RXC_FUNC_SEL_MASK
+#define PAD_GPIO10_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO10_FUNC_SEL_SHIFT                           \
+        PAD_GPIO10_FUNC_SEL_MASK
+#define PAD_GPIO11_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO11_FUNC_SEL_SHIFT                           \
+        PAD_GPIO11_FUNC_SEL_MASK
+#define PAD_GPIO12_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO12_FUNC_SEL_SHIFT                           \
+        PAD_GPIO12_FUNC_SEL_MASK
+#define PAD_GPIO13_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO13_FUNC_SEL_SHIFT                           \
+        PAD_GPIO13_FUNC_SEL_MASK
+#define PAD_GPIO14_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO14_FUNC_SEL_SHIFT                           \
+        PAD_GPIO14_FUNC_SEL_MASK
+#define PAD_GPIO15_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO15_FUNC_SEL_SHIFT                           \
+        PAD_GPIO15_FUNC_SEL_MASK
+#define PAD_GPIO16_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO16_FUNC_SEL_SHIFT                           \
+        PAD_GPIO16_FUNC_SEL_MASK
+#define PAD_GPIO17_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO17_FUNC_SEL_SHIFT                           \
+        PAD_GPIO17_FUNC_SEL_MASK
+#define PAD_GPIO18_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO18_FUNC_SEL_SHIFT                           \
+        PAD_GPIO18_FUNC_SEL_MASK
+#define PAD_GPIO19_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \
+        PAD_GPIO19_FUNC_SEL_SHIFT                           \
+        PAD_GPIO19_FUNC_SEL_MASK
+#define PAD_GPIO20_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO20_FUNC_SEL_SHIFT                           \
+        PAD_GPIO20_FUNC_SEL_MASK
+#define PAD_GPIO21_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO21_FUNC_SEL_SHIFT                           \
+        PAD_GPIO21_FUNC_SEL_MASK
+#define PAD_GPIO22_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO22_FUNC_SEL_SHIFT                           \
+        PAD_GPIO22_FUNC_SEL_MASK
+#define PAD_GPIO23_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO23_FUNC_SEL_SHIFT                           \
+        PAD_GPIO23_FUNC_SEL_MASK
+#define PAD_GPIO24_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO24_FUNC_SEL_SHIFT                           \
+        PAD_GPIO24_FUNC_SEL_MASK
+#define PAD_GPIO25_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO25_FUNC_SEL_SHIFT                           \
+        PAD_GPIO25_FUNC_SEL_MASK
+#define PAD_GPIO26_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO26_FUNC_SEL_SHIFT                           \
+        PAD_GPIO26_FUNC_SEL_MASK
+#define PAD_GPIO27_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO27_FUNC_SEL_SHIFT                           \
+        PAD_GPIO27_FUNC_SEL_MASK
+#define PAD_GPIO28_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO28_FUNC_SEL_SHIFT                           \
+        PAD_GPIO28_FUNC_SEL_MASK
+#define PAD_GPIO29_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \
+        PAD_GPIO29_FUNC_SEL_SHIFT                           \
+        PAD_GPIO29_FUNC_SEL_MASK
+#define PAD_GPIO30_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO30_FUNC_SEL_SHIFT                           \
+        PAD_GPIO30_FUNC_SEL_MASK
+#define PAD_GPIO31_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO31_FUNC_SEL_SHIFT                           \
+        PAD_GPIO31_FUNC_SEL_MASK
+#define PAD_GPIO32_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO32_FUNC_SEL_SHIFT                           \
+        PAD_GPIO32_FUNC_SEL_MASK
+#define PAD_GPIO33_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO33_FUNC_SEL_SHIFT                           \
+        PAD_GPIO33_FUNC_SEL_MASK
+#define PAD_GPIO34_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO34_FUNC_SEL_SHIFT                           \
+        PAD_GPIO34_FUNC_SEL_MASK
+#define PAD_GPIO35_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO35_FUNC_SEL_SHIFT                           \
+        PAD_GPIO35_FUNC_SEL_MASK
+#define PAD_GPIO36_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO36_FUNC_SEL_SHIFT                           \
+        PAD_GPIO36_FUNC_SEL_MASK
+#define PAD_GPIO37_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO37_FUNC_SEL_SHIFT                           \
+        PAD_GPIO37_FUNC_SEL_MASK
+#define PAD_GPIO38_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO38_FUNC_SEL_SHIFT                           \
+        PAD_GPIO38_FUNC_SEL_MASK
+#define PAD_GPIO39_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO39_FUNC_SEL_SHIFT                           \
+        PAD_GPIO39_FUNC_SEL_MASK
+#define PAD_GPIO40_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \
+        PAD_GPIO40_FUNC_SEL_SHIFT                           \
+        PAD_GPIO40_FUNC_SEL_MASK
+#define PAD_GPIO41_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO41_FUNC_SEL_SHIFT                           \
+        PAD_GPIO41_FUNC_SEL_MASK
+#define PAD_GPIO42_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO42_FUNC_SEL_SHIFT                           \
+        PAD_GPIO42_FUNC_SEL_MASK
+#define PAD_GPIO43_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO43_FUNC_SEL_SHIFT                           \
+        PAD_GPIO43_FUNC_SEL_MASK
+#define PAD_GPIO44_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO44_FUNC_SEL_SHIFT                           \
+        PAD_GPIO44_FUNC_SEL_MASK
+#define PAD_GPIO45_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO45_FUNC_SEL_SHIFT                           \
+        PAD_GPIO45_FUNC_SEL_MASK
+#define PAD_GPIO46_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO46_FUNC_SEL_SHIFT                           \
+        PAD_GPIO46_FUNC_SEL_MASK
+#define PAD_GPIO47_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO47_FUNC_SEL_SHIFT                           \
+        PAD_GPIO47_FUNC_SEL_MASK
+#define PAD_GPIO48_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO48_FUNC_SEL_SHIFT                           \
+        PAD_GPIO48_FUNC_SEL_MASK
+#define PAD_GPIO49_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO49_FUNC_SEL_SHIFT                           \
+        PAD_GPIO49_FUNC_SEL_MASK
+#define PAD_GPIO50_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO50_FUNC_SEL_SHIFT                           \
+        PAD_GPIO50_FUNC_SEL_MASK
+#define PAD_GPIO51_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \
+        PAD_GPIO51_FUNC_SEL_SHIFT                           \
+        PAD_GPIO51_FUNC_SEL_MASK
+#define PAD_GPIO52_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO52_FUNC_SEL_SHIFT                           \
+        PAD_GPIO52_FUNC_SEL_MASK
+#define PAD_GPIO53_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO53_FUNC_SEL_SHIFT                           \
+        PAD_GPIO53_FUNC_SEL_MASK
+#define PAD_GPIO54_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO54_FUNC_SEL_SHIFT                           \
+        PAD_GPIO54_FUNC_SEL_MASK
+#define PAD_GPIO55_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO55_FUNC_SEL_SHIFT                           \
+        PAD_GPIO55_FUNC_SEL_MASK
+#define PAD_GPIO56_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO56_FUNC_SEL_SHIFT                           \
+        PAD_GPIO56_FUNC_SEL_MASK
+#define PAD_GPIO57_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO57_FUNC_SEL_SHIFT                           \
+        PAD_GPIO57_FUNC_SEL_MASK
+#define PAD_GPIO58_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO58_FUNC_SEL_SHIFT                           \
+        PAD_GPIO58_FUNC_SEL_MASK
+#define PAD_GPIO59_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO59_FUNC_SEL_SHIFT                           \
+        PAD_GPIO59_FUNC_SEL_MASK
+#define PAD_GPIO60_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO60_FUNC_SEL_SHIFT                           \
+        PAD_GPIO60_FUNC_SEL_MASK
+#define PAD_GPIO61_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO61_FUNC_SEL_SHIFT                           \
+        PAD_GPIO61_FUNC_SEL_MASK
+#define PAD_GPIO62_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO62_FUNC_SEL_SHIFT                           \
+        PAD_GPIO62_FUNC_SEL_MASK
+#define PAD_GPIO63_FUNC_SEL                                 \
+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \
+        PAD_GPIO63_FUNC_SEL_SHIFT                           \
+        PAD_GPIO63_FUNC_SEL_MASK
+#define PAD_GPIO6_FUNC_SEL                                  \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        PAD_GPIO6_FUNC_SEL_SHIFT                            \
+        PAD_GPIO6_FUNC_SEL_MASK
+#define PAD_GPIO7_FUNC_SEL                                  \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        PAD_GPIO7_FUNC_SEL_SHIFT                            \
+        PAD_GPIO7_FUNC_SEL_MASK
+#define PAD_GPIO8_FUNC_SEL                                  \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        PAD_GPIO8_FUNC_SEL_SHIFT                            \
+        PAD_GPIO8_FUNC_SEL_MASK
+#define PAD_GPIO9_FUNC_SEL                                  \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        PAD_GPIO9_FUNC_SEL_SHIFT                            \
+        PAD_GPIO9_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL         \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT   \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL         \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT   \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL          \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT    \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL         \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT   \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL         \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT   \
+        U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL                         \
+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \
+        U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT                   \
+        U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK
+/************************sys_iomux***************************/
+// aon ioconfig
+
+// POS[0]
+#define TESTEN_POS(data)  ((data << 0x0U) & 0x1U)
+
+// SMT[0] POS[1]
+#define RSTN_SMT(data)  ((data << 0x0U) & 0x1U)
+#define RSTN_POS(data)  ((data << 0x1U) & 0x2U)
+
+// DS[1:0]
+#define OSC_DS(data)  ((data << 0x0U) & 0x3U)
+
+// sys ioconfig
+// IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7]
+#define GPIO_IE(data)    ((data << 0x0U) & 0x1U)
+#define GPIO_DS(data)    ((data << 0x1U) & 0x6U)
+#define GPIO_PU(data)    ((data << 0x3U) & 0x8U)
+#define GPIO_PD(data)    ((data << 0x4U) & 0x10U)
+#define GPIO_SLEW(data)  ((data << 0x5U) & 0x20U)
+#define GPIO_SMT(data)   ((data << 0x6U) & 0x40U)
+#define GPIO_POS(data)   ((data << 0x7U) & 0x80U)
+
+#define IO(config)    ((config) & 0xFF)
+#define DOUT(dout)    ((dout) & 0xFF)
+#define DOEN(doen)    ((doen) & 0xFF)
+#define DIN(din_reg)  ((din_reg) & 0xFF)
+
+// syscon value
+#define IO_3_3V  0 /*00:3.3v*/
+#define IO_2_5V  1 /*01:2.5v*/
+#define IO_1_8V  2 /*10:1.8v*/
+
+#endif /* __DT_BINDINGS_JH7110_PIN_CTRL_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h
new file mode 100755
index 000000000000..4763c4de1f22
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h
@@ -0,0 +1,22 @@
+/** @file
+  This header provide all JH7110 power device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_POWER_H__
+#define __DT_BINDINGS_JH7110_POWER_H__
+
+#define JH7110_PD_SYSTOP  0
+#define JH7110_PD_CPU     1
+#define JH7110_PD_GPUA    2
+#define JH7110_PD_VDEC    3
+#define JH7110_PD_VOUT    4
+#define JH7110_PD_ISP     5
+#define JH7110_PD_VENC    6
+#define JH7110_PD_GPUB    7
+
+#endif /* __DT_BINDINGS_JH7110_POWER_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h
new file mode 100644
index 000000000000..fc9a2ff01a00
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h
@@ -0,0 +1,228 @@
+/** @file
+  This header provide all JH7110 reset device tree bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_JH7110_RESET_H__
+#define __DT_BINDINGS_JH7110_RESET_H__
+
+/*
+ * group[0]: syscrg: assert0
+ */
+#define RSTN_U0_JTAG2APB_PRESETN       0
+#define RSTN_U0_SYS_SYSCON_PRESETN     1
+#define RSTN_U0_SYS_IOMUX_PRESETN      2
+#define RSTN_U0_U7MC_RST_BUS           3
+#define RSTN_U0_U7MC_DEBUG             4
+#define RSTN_U0_U7MC_CORE0             5
+#define RSTN_U0_U7MC_CORE1             6
+#define RSTN_U0_U7MC_CORE2             7
+#define RSTN_U0_U7MC_CORE3             8
+#define RSTN_U0_U7MC_CORE4             9
+#define RSTN_U0_U7MC_CORE0_ST          10
+#define RSTN_U0_U7MC_CORE1_ST          11
+#define RSTN_U0_U7MC_CORE2_ST          12
+#define RSTN_U0_U7MC_CORE3_ST          13
+#define RSTN_U0_U7MC_CORE4_ST          14
+#define RSTN_U0_U7MC_TRACE_RST0        15
+#define RSTN_U0_U7MC_TRACE_RST1        16
+#define RSTN_U0_U7MC_TRACE_RST2        17
+#define RSTN_U0_U7MC_TRACE_RST3        18
+#define RSTN_U0_U7MC_TRACE_RST4        19
+#define RSTN_U0_U7MC_TRACE_COM         20
+#define RSTN_U0_IMG_GPU_APB            21
+#define RSTN_U0_IMG_GPU_DOMA           22
+#define RSTN_U0_NOC_BUS_APB_BUS_N      23
+#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N  24
+#define RSTN_U0_NOC_BUS_CPU_AXI_N      25
+#define RSTN_U0_NOC_BUS_DISP_AXI_N     26
+#define RSTN_U0_NOC_BUS_GPU_AXI_N      27
+#define RSTN_U0_NOC_BUS_ISP_AXI_N      28
+#define RSTN_U0_NOC_BUS_DDRC_N         29
+#define RSTN_U0_NOC_BUS_STG_AXI_N      30
+#define RSTN_U0_NOC_BUS_VDEC_AXI_N     31
+
+/*
+ * group[1]: syscrg: assert1
+ */
+#define RSTN_U0_NOC_BUS_VENC_AXI_N     32
+#define RSTN_U0_AXI_CFG1_DEC_AHB       33
+#define RSTN_U0_AXI_CFG1_DEC_MAIN      34
+#define RSTN_U0_AXI_CFG0_DEC_MAIN      35
+#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV  36
+#define RSTN_U0_AXI_CFG0_DEC_HIFI4     37
+#define RSTN_U0_DDR_AXI                38
+#define RSTN_U0_DDR_OSC                39
+#define RSTN_U0_DDR_APB                40
+#define RSTN_U0_DOM_ISP_TOP_N          41
+#define RSTN_U0_DOM_ISP_TOP_AXI        42
+#define RSTN_U0_DOM_VOUT_TOP_SRC       43
+#define RSTN_U0_CODAJ12_AXI            44
+#define RSTN_U0_CODAJ12_CORE           45
+#define RSTN_U0_CODAJ12_APB            46
+#define RSTN_U0_WAVE511_AXI            47
+#define RSTN_U0_WAVE511_BPU            48
+#define RSTN_U0_WAVE511_VCE            49
+#define RSTN_U0_WAVE511_APB            50
+#define RSTN_U0_VDEC_JPG_ARB_JPG       51
+#define RSTN_U0_VDEC_JPG_ARB_MAIN      52
+#define RSTN_U0_AXIMEM_128B_AXI        53
+#define RSTN_U0_WAVE420L_AXI           54
+#define RSTN_U0_WAVE420L_BPU           55
+#define RSTN_U0_WAVE420L_VCE           56
+#define RSTN_U0_WAVE420L_APB           57
+#define RSTN_U1_AXIMEM_128B_AXI        58
+#define RSTN_U2_AXIMEM_128B_AXI        59
+#define RSTN_U0_INTMEM_ROM_SRAM_ROM    60
+#define RSTN_U0_CDNS_QSPI_AHB          61
+#define RSTN_U0_CDNS_QSPI_APB          62
+#define RSTN_U0_CDNS_QSPI_REF          63
+
+/*
+ * group[2]: syscrg: assert2
+ */
+#define RSTN_U0_DW_SDIO_AHB         64
+#define RSTN_U1_DW_SDIO_AHB         65
+#define RSTN_U1_DW_GMAC5_AXI64_A_I  66
+#define RSTN_U1_DW_GMAC5_AXI64_H_N  67
+#define RSTN_U0_MAILBOX_RRESETN     68
+#define RSTN_U0_SSP_SPI_APB         69
+#define RSTN_U1_SSP_SPI_APB         70
+#define RSTN_U2_SSP_SPI_APB         71
+#define RSTN_U3_SSP_SPI_APB         72
+#define RSTN_U4_SSP_SPI_APB         73
+#define RSTN_U5_SSP_SPI_APB         74
+#define RSTN_U6_SSP_SPI_APB         75
+#define RSTN_U0_DW_I2C_APB          76
+#define RSTN_U1_DW_I2C_APB          77
+#define RSTN_U2_DW_I2C_APB          78
+#define RSTN_U3_DW_I2C_APB          79
+#define RSTN_U4_DW_I2C_APB          80
+#define RSTN_U5_DW_I2C_APB          81
+#define RSTN_U6_DW_I2C_APB          82
+#define RSTN_U0_DW_UART_APB         83
+#define RSTN_U0_DW_UART_CORE        84
+#define RSTN_U1_DW_UART_APB         85
+#define RSTN_U1_DW_UART_CORE        86
+#define RSTN_U2_DW_UART_APB         87
+#define RSTN_U2_DW_UART_CORE        88
+#define RSTN_U3_DW_UART_APB         89
+#define RSTN_U3_DW_UART_CORE        90
+#define RSTN_U4_DW_UART_APB         91
+#define RSTN_U4_DW_UART_CORE        92
+#define RSTN_U5_DW_UART_APB         93
+#define RSTN_U5_DW_UART_CORE        94
+#define RSTN_U0_CDNS_SPDIF_APB      95
+
+/*
+ * group[3]: syscrg: assert3
+ */
+#define RSTN_U0_PWMDAC_APB            96
+#define RSTN_U0_PDM_4MIC_DMIC         97
+#define RSTN_U0_PDM_4MIC_APB          98
+#define RSTN_U0_I2SRX_3CH_APB         99
+#define RSTN_U0_I2SRX_3CH_BCLK        100
+#define RSTN_U0_I2STX_4CH_APB         101
+#define RSTN_U0_I2STX_4CH_BCLK        102
+#define RSTN_U1_I2STX_4CH_APB         103
+#define RSTN_U1_I2STX_4CH_BCLK        104
+#define RSTN_U0_TDM16SLOT_AHB         105
+#define RSTN_U0_TDM16SLOT_TDM         106
+#define RSTN_U0_TDM16SLOT_APB         107
+#define RSTN_U0_PWM_8CH_APB           108
+#define RSTN_U0_DSKIT_WDT_APB         109
+#define RSTN_U0_DSKIT_WDT_CORE        110
+#define RSTN_U0_CAN_CTRL_APB          111
+#define RSTN_U0_CAN_CTRL_CORE         112
+#define RSTN_U0_CAN_CTRL_TIMER        113
+#define RSTN_U1_CAN_CTRL_APB          114
+#define RSTN_U1_CAN_CTRL_CORE         115
+#define RSTN_U1_CAN_CTRL_TIMER        116
+#define RSTN_U0_TIMER_APB             117
+#define RSTN_U0_TIMER_TIMER0          118
+#define RSTN_U0_TIMER_TIMER1          119
+#define RSTN_U0_TIMER_TIMER2          120
+#define RSTN_U0_TIMER_TIMER3          121
+#define RSTN_U0_INT_CTRL_APB          122
+#define RSTN_U0_TEMP_SENSOR_APB       123
+#define RSTN_U0_TEMP_SENSOR_TEMP      124
+#define RSTN_U0_JTAG_CERTIFICATION_N  125
+
+/*
+ * group[4]: stgcrg
+ */
+#define RSTN_U0_STG_SYSCON_PRESETN  128
+#define RSTN_U0_HIFI4_CORE          129
+#define RSTN_U0_HIFI4_AXI           130
+#define RSTN_U0_SEC_TOP_HRESETN     131
+#define RSTN_U0_E24_CORE            132
+#define RSTN_U0_DW_DMA1P_AXI        133
+#define RSTN_U0_DW_DMA1P_AHB        134
+#define RSTN_U0_CDN_USB_AXI         135
+#define RSTN_U0_CDN_USB_APB         136
+#define RSTN_U0_CDN_USB_UTMI_APB    137
+#define RSTN_U0_CDN_USB_PWRUP       138
+#define RSTN_U0_PLDA_PCIE_AXI_MST0  139
+#define RSTN_U0_PLDA_PCIE_AXI_SLV0  140
+#define RSTN_U0_PLDA_PCIE_AXI_SLV   141
+#define RSTN_U0_PLDA_PCIE_BRG       142
+#define RSTN_U0_PLDA_PCIE_CORE      143
+#define RSTN_U0_PLDA_PCIE_APB       144
+#define RSTN_U1_PLDA_PCIE_AXI_MST0  145
+#define RSTN_U1_PLDA_PCIE_AXI_SLV0  146
+#define RSTN_U1_PLDA_PCIE_AXI_SLV   147
+#define RSTN_U1_PLDA_PCIE_BRG       148
+#define RSTN_U1_PLDA_PCIE_CORE      149
+#define RSTN_U1_PLDA_PCIE_APB       150
+
+/*
+ * group[5]: aoncrg
+ */
+#define RSTN_U0_DW_GMAC5_AXI64_AXI  160
+#define RSTN_U0_DW_GMAC5_AXI64_AHB  161
+#define RSTN_U0_AON_IOMUX_PRESETN   162
+#define RSTN_U0_PMU_APB             163
+#define RSTN_U0_PMU_WKUP            164
+#define RSTN_U0_RTC_HMS_APB         165
+#define RSTN_U0_RTC_HMS_CAL         166
+#define RSTN_U0_RTC_HMS_OSC32K      167
+
+/*
+ * group[6]: ispcrg
+ */
+#define RSTN_U0_ISPV2_TOP_WRAPPER_P    192
+#define RSTN_U0_ISPV2_TOP_WRAPPER_C    193
+#define RSTN_U0_M31DPHY_HW             194
+#define RSTN_U0_M31DPHY_B09_ALWAYS_ON  195
+#define RSTN_U0_VIN_N_PCLK             196
+#define RSTN_U0_VIN_N_PIXEL_CLK_IF0    197
+#define RSTN_U0_VIN_N_PIXEL_CLK_IF1    198
+#define RSTN_U0_VIN_N_PIXEL_CLK_IF2    199
+#define RSTN_U0_VIN_N_PIXEL_CLK_IF3    200
+#define RSTN_U0_VIN_N_SYS_CLK          201
+#define RSTN_U0_VIN_P_AXIRD            202
+#define RSTN_U0_VIN_P_AXIWR            203
+
+/*
+ * group[7]: voutcrg
+ */
+#define RSTN_U0_DC8200_AXI            224
+#define RSTN_U0_DC8200_AHB            225
+#define RSTN_U0_DC8200_CORE           226
+#define RSTN_U0_CDNS_DSITX_DPI        227
+#define RSTN_U0_CDNS_DSITX_APB        228
+#define RSTN_U0_CDNS_DSITX_RXESC      229
+#define RSTN_U0_CDNS_DSITX_SYS        230
+#define RSTN_U0_CDNS_DSITX_TXBYTEHS   231
+#define RSTN_U0_CDNS_DSITX_TXESC      232
+#define RSTN_U0_HDMI_TX_HDMI          233
+#define RSTN_U0_MIPITX_DPHY_SYS       234
+#define RSTN_U0_MIPITX_DPHY_TXBYTEHS  235
+
+#define RSTN_JH7110_RESET_END  236
+
+#endif /* __DT_BINDINGS_JH7110_RESET_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Led.h b/Platform/StarFive/VisionFive2/DeviceTree/Led.h
new file mode 100644
index 000000000000..53d636e17215
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Led.h
@@ -0,0 +1,90 @@
+/** @file
+  This header provide all the LEDs bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_LEDS_H__
+#define __DT_BINDINGS_LEDS_H__
+
+/* External trigger type */
+#define LEDS_TRIG_TYPE_EDGE   0
+#define LEDS_TRIG_TYPE_LEVEL  1
+
+/* Boost modes */
+#define LEDS_BOOST_OFF       0
+#define LEDS_BOOST_ADAPTIVE  1
+#define LEDS_BOOST_FIXED     2
+
+/* Standard LED colors */
+#define LED_COLOR_ID_WHITE   0
+#define LED_COLOR_ID_RED     1
+#define LED_COLOR_ID_GREEN   2
+#define LED_COLOR_ID_BLUE    3
+#define LED_COLOR_ID_AMBER   4
+#define LED_COLOR_ID_VIOLET  5
+#define LED_COLOR_ID_YELLOW  6
+#define LED_COLOR_ID_IR      7
+#define LED_COLOR_ID_MULTI   8   /* For multicolor LEDs */
+#define LED_COLOR_ID_RGB     9   /* For multicolor LEDs that can do arbitrary color, \
+                                    so this would include RGBW and similar */
+#define LED_COLOR_ID_MAX     10
+
+/* Standard LED functions */
+/* Keyboard LEDs, usually it would be input4::capslock etc. */
+#define LED_FUNCTION_CAPSLOCK       "capslock"
+#define LED_FUNCTION_SCROLLLOCK     "scrolllock"
+#define LED_FUNCTION_NUMLOCK        "numlock"
+#define LED_FUNCTION_KBD_BACKLIGHT  "kbd_backlight"
+
+/* System LEDs, usually found on system body.
+   platform:: mute (etc) is sometimes seen, : mute would be better */
+#define LED_FUNCTION_POWER  "power"
+#define LED_FUNCTION_DISK   "disk"
+
+/*   Obsolete: "platform:*:charging" (allwinner sun50i) */
+#define LED_FUNCTION_CHARGING  "charging"
+
+/*   Used RGB notification LEDs common on phones.
+     Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4),
+     "lp5523:{r,g,b}" (Nokia N900) */
+#define LED_FUNCTION_STATUS  "status"
+
+#define LED_FUNCTION_MICMUTE  "micmute"
+#define LED_FUNCTION_MUTE     "mute"
+
+/* Miscelleaus functions. Use functions above if you can. */
+#define LED_FUNCTION_ACTIVITY       "activity"
+#define LED_FUNCTION_ALARM          "alarm"
+#define LED_FUNCTION_BACKLIGHT      "backlight"
+#define LED_FUNCTION_BLUETOOTH      "bluetooth"
+#define LED_FUNCTION_BOOT           "boot"
+#define LED_FUNCTION_CPU            "cpu"
+#define LED_FUNCTION_DEBUG          "debug"
+#define LED_FUNCTION_DISK_ACTIVITY  "disk-activity"
+#define LED_FUNCTION_DISK_ERR       "disk-err"
+#define LED_FUNCTION_DISK_READ      "disk-read"
+#define LED_FUNCTION_DISK_WRITE     "disk-write"
+#define LED_FUNCTION_FAULT          "fault"
+#define LED_FUNCTION_FLASH          "flash"
+#define LED_FUNCTION_HEARTBEAT      "heartbeat"
+#define LED_FUNCTION_INDICATOR      "indicator"
+#define LED_FUNCTION_LAN            "lan"
+#define LED_FUNCTION_MAIL           "mail"
+#define LED_FUNCTION_MTD            "mtd"
+#define LED_FUNCTION_PANIC          "panic"
+#define LED_FUNCTION_PROGRAMMING    "programming"
+#define LED_FUNCTION_RX             "rx"
+#define LED_FUNCTION_SD             "sd"
+#define LED_FUNCTION_STANDBY        "standby"
+#define LED_FUNCTION_TORCH          "torch"
+#define LED_FUNCTION_TX             "tx"
+#define LED_FUNCTION_USB            "usb"
+#define LED_FUNCTION_WAN            "wan"
+#define LED_FUNCTION_WLAN           "wlan"
+#define LED_FUNCTION_WPS            "wps"
+
+#endif /* __DT_BINDINGS_LEDS_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi
new file mode 100755
index 000000000000..be3bfe405d99
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi
@@ -0,0 +1,130 @@
+/** @file
+  Device tree defination for all JH7110 clocks used in StarFive VisionFive 2 platform
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/ {
+    osc: osc {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    clk_ext_camera: clk-ext-camera {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+
+    gmac1_rmii_refin: gmac1_rmii_refin {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <50000000>;
+    };
+
+    gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <125000000>;
+    };
+
+    i2stx_bclk_ext: i2stx_bclk_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <12288000>;
+    };
+
+    i2stx_lrck_ext: i2stx_lrck_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <192000>;
+    };
+
+    i2srx_bclk_ext: i2srx_bclk_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <12288000>;
+    };
+
+    i2srx_lrck_ext: i2srx_lrck_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <192000>;
+    };
+
+    tdm_ext: tdm_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <49152000>;
+    };
+
+    mclk_ext: mclk_ext {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <12288000>;
+    };
+
+    jtag_tck_inner: jtag_tck_inner {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <50000000>;
+    };
+
+    bist_apb: bist_apb {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <50000000>;
+    };
+
+    gmac0_rmii_refin: gmac0_rmii_refin {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <50000000>;
+    };
+
+    gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <125000000>;
+    };
+
+    clk_rtc: clk_rtc {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <32768>;
+    };
+
+    hdmitx0_pixelclk: hdmitx0_pixelclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <297000000>;
+    };
+
+    mipitx_dphy_rxesc: mipitx_dphy_rxesc {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <10000000>;
+    };
+
+    mipitx_dphy_txbytehs: mipitx_dphy_txbytehs {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <297000000>;
+    };
+
+    wm8960_mclk: wm8960_mclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <24576000>;
+    };
+
+    ac108_mclk: ac108_mclk {
+        compatible = "fixed-clock";
+        #clock-cells = <0>;
+        clock-frequency = <24000000>;
+    };
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi
new file mode 100644
index 000000000000..ca96fa954ab4
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi
@@ -0,0 +1,28 @@
+/** @file
+  Device tree defination all JH7110 display audio for StarFive VisionFive 2 platform
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+&sound1 {
+    /* i2s + hdmi */
+    simple-audio-card,dai-link@0 {
+        reg = <0>;
+        format = "i2s";
+        bitclock-master = <&sndi2s0>;
+        frame-master = <&sndi2s0>;
+        mclk-fs = <256>;
+        status = "okay";
+
+        sndi2s0: cpu {
+            sound-dai = <&i2stx_4ch0>;
+        };
+
+        sndhdmi0: codec {
+            sound-dai = <&hdmi>;
+        };
+    };
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi
new file mode 100644
index 000000000000..d216c0357a4b
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi
@@ -0,0 +1,1812 @@
+/** @file
+  Device tree defination for JH7110 SoC
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/dts-v1/;
+#include "StarFiveClk.dtsi"
+#include "JH7110ClkGen.h"
+#include "JH7110ClkVout.h"
+#include "JH7110ClkIsp.h"
+#include "JH7110Rst.h"
+#include "JH7110Power.h"
+#include "Thermal.h"
+#include "Irq.h"
+
+/ {
+    compatible = "starfive,jh7110";
+    #address-cells = <2>;
+    #size-cells = <2>;
+
+    cluster0_opp: opp-table-0 {
+            compatible = "operating-points-v2";
+            opp-shared;
+            opp-375000000 {
+                    opp-hz = /bits/ 64 <375000000>;
+                    opp-microvolt = <800000>;
+            };
+            opp-500000000 {
+                    opp-hz = /bits/ 64 <500000000>;
+                    opp-microvolt = <800000>;
+            };
+            opp-750000000 {
+                    opp-hz = /bits/ 64 <750000000>;
+                    opp-microvolt = <800000>;
+                    opp-suspend;
+            };
+            opp-1500000000 {
+                    opp-hz = /bits/ 64 <1500000000>;
+                    opp-microvolt = <1040000>;
+            };
+    };
+
+    cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        cpu0: cpu@0 {
+            compatible = "sifive,u74-mc", "riscv";
+            reg = <0>;
+            d-cache-block-size = <64>;
+            d-cache-sets = <64>;
+            d-cache-size = <8192>;
+            d-tlb-sets = <1>;
+            d-tlb-size = <40>;
+            device_type = "cpu";
+            i-cache-block-size = <64>;
+            i-cache-sets = <64>;
+            i-cache-size = <16384>;
+            i-tlb-sets = <1>;
+            i-tlb-size = <40>;
+            mmu-type = "riscv,sv39";
+            next-level-cache = <&cachectrl>;
+            riscv,isa = "rv64imac";
+            tlb-split;
+            #cooling-cells = <2>;
+            status = "disabled";
+
+            cpu0intctrl: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu1: cpu@1 {
+            compatible = "sifive,u74-mc", "riscv";
+            reg = <1>;
+            d-cache-block-size = <64>;
+            d-cache-sets = <64>;
+            d-cache-size = <32768>;
+            d-tlb-sets = <1>;
+            d-tlb-size = <40>;
+            device_type = "cpu";
+            i-cache-block-size = <64>;
+            i-cache-sets = <64>;
+            i-cache-size = <32768>;
+            i-tlb-sets = <1>;
+            i-tlb-size = <40>;
+            mmu-type = "riscv,sv39";
+            next-level-cache = <&cachectrl>;
+            riscv,isa = "rv64imafdc";
+            tlb-split;
+            #cooling-cells = <2>;
+            status = "okay";
+            operating-points-v2 = <&cluster0_opp>;
+
+            cpu1intctrl: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu2: cpu@2 {
+            compatible = "sifive,u74-mc", "riscv";
+            reg = <2>;
+            d-cache-block-size = <64>;
+            d-cache-sets = <64>;
+            d-cache-size = <32768>;
+            d-tlb-sets = <1>;
+            d-tlb-size = <40>;
+            device_type = "cpu";
+            i-cache-block-size = <64>;
+            i-cache-sets = <64>;
+            i-cache-size = <32768>;
+            i-tlb-sets = <1>;
+            i-tlb-size = <40>;
+            mmu-type = "riscv,sv39";
+            next-level-cache = <&cachectrl>;
+            riscv,isa = "rv64imafdc";
+            tlb-split;
+            #cooling-cells = <2>;
+            status = "okay";
+            operating-points-v2 = <&cluster0_opp>;
+
+            cpu2intctrl: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu3: cpu@3 {
+            compatible = "sifive,u74-mc", "riscv";
+            reg = <3>;
+            d-cache-block-size = <64>;
+            d-cache-sets = <64>;
+            d-cache-size = <32768>;
+            d-tlb-sets = <1>;
+            d-tlb-size = <40>;
+            device_type = "cpu";
+            i-cache-block-size = <64>;
+            i-cache-sets = <64>;
+            i-cache-size = <32768>;
+            i-tlb-sets = <1>;
+            i-tlb-size = <40>;
+            mmu-type = "riscv,sv39";
+            next-level-cache = <&cachectrl>;
+            riscv,isa = "rv64imafdc";
+            tlb-split;
+            #cooling-cells = <2>;
+            status = "okay";
+            operating-points-v2 = <&cluster0_opp>;
+
+            cpu3intctrl: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+
+        cpu4: cpu@4 {
+            compatible = "sifive,u74-mc", "riscv";
+            reg = <4>;
+            d-cache-block-size = <64>;
+            d-cache-sets = <64>;
+            d-cache-size = <32768>;
+            d-tlb-sets = <1>;
+            d-tlb-size = <40>;
+            device_type = "cpu";
+            i-cache-block-size = <64>;
+            i-cache-sets = <64>;
+            i-cache-size = <32768>;
+            i-tlb-sets = <1>;
+            i-tlb-size = <40>;
+            mmu-type = "riscv,sv39";
+            next-level-cache = <&cachectrl>;
+            riscv,isa = "rv64imafdc";
+            tlb-split;
+            #cooling-cells = <2>;
+            status = "okay";
+            operating-points-v2 = <&cluster0_opp>;
+
+            cpu4intctrl: interrupt-controller {
+                #interrupt-cells = <1>;
+                compatible = "riscv,cpu-intc";
+                interrupt-controller;
+            };
+        };
+    };
+
+    soc: soc {
+        compatible = "simple-bus";
+        interrupt-parent = <&plic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        #clock-cells = <1>;
+        ranges;
+
+        cachectrl: cache-controller@2010000 {
+            compatible = "sifive,fu740-c000-ccache", "cache";
+            reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
+            reg-names = "control", "sideband";
+            interrupts = <1 3 4 2>;
+            cache-block-size = <64>;
+            cache-level = <2>;
+            cache-sets = <2048>;
+            cache-size = <2097152>;
+            cache-unified;
+        };
+
+        aon_syscon: aon_syscon@17010000 {
+            compatible = "syscon";
+            reg = <0x0 0x17010000 0x0 0x1000>;
+        };
+
+        phyctrl0: multi-phyctrl@10210000 {
+            compatible = "starfive,phyctrl";
+            reg = <0x0 0x10210000 0x0 0x10000>;
+        };
+
+        phyctrl1: pcie1-phyctrl@10220000 {
+            compatible = "starfive,phyctrl";
+            reg = <0x0 0x10220000 0x0 0x10000>;
+        };
+
+        stg_syscon: stg_syscon@10240000 {
+            compatible = "syscon";
+            reg = <0x0 0x10240000 0x0 0x1000>;
+        };
+
+        sys_syscon: sys_syscon@13030000 {
+            compatible = "syscon";
+            reg = <0x0 0x13030000 0x0 0x1000>;
+        };
+
+        clint: clint@2000000 {
+            compatible = "riscv,clint0";
+            reg = <0x0 0x2000000 0x0 0x10000>;
+            reg-names = "control";
+            interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
+                        &cpu1intctrl 3 &cpu1intctrl 7
+                        &cpu2intctrl 3 &cpu2intctrl 7
+                        &cpu3intctrl 3 &cpu3intctrl 7
+                        &cpu4intctrl 3 &cpu4intctrl 7>;
+            #interrupt-cells = <1>;
+        };
+
+        plic: plic@c000000 {
+            compatible = "riscv,plic0";
+            reg = <0x0 0xc000000 0x0 0x4000000>;
+            reg-names = "control";
+            interrupts-extended = <&cpu0intctrl 11
+                        &cpu1intctrl 11 &cpu1intctrl 9
+                        &cpu2intctrl 11 &cpu2intctrl 9
+                        &cpu3intctrl 11 &cpu3intctrl 9
+                        &cpu4intctrl 11 &cpu4intctrl 9>;
+            interrupt-controller;
+            #interrupt-cells = <1>;
+            riscv,max-priority = <7>;
+            riscv,ndev = <136>;
+        };
+
+        clkgen: clock-controller {
+            compatible = "starfive,jh7110-clkgen";
+            reg = <0x0 0x13020000 0x0 0x10000>,
+                <0x0 0x10230000 0x0 0x10000>,
+                <0x0 0x17000000 0x0 0x10000>;
+            reg-names = "sys", "stg", "aon";
+            clocks = <&osc>, <&gmac1_rmii_refin>,
+                 <&gmac1_rgmii_rxin>,
+                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                 <&tdm_ext>, <&mclk_ext>,
+                 <&jtag_tck_inner>, <&bist_apb>,
+                 <&clk_rtc>,
+                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+            clock-names = "osc", "gmac1_rmii_refin",
+                "gmac1_rgmii_rxin",
+                "i2stx_bclk_ext", "i2stx_lrck_ext",
+                "i2srx_bclk_ext", "i2srx_lrck_ext",
+                "tdm_ext", "mclk_ext",
+                "jtag_tck_inner", "bist_apb",
+                "clk_rtc",
+                "gmac0_rmii_refin", "gmac0_rgmii_rxin";
+            #clock-cells = <1>;
+            starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+                    0x20 0x24 0x28 0x2c 0x30 0x34>;
+            status = "okay";
+        };
+
+        clkvout: clock-controller@295C0000 {
+            compatible = "starfive,jh7110-clk-vout";
+            reg = <0x0 0x295C0000 0x0 0x10000>;
+            reg-names = "vout";
+            clocks = <&hdmitx0_pixelclk>,
+                 <&mipitx_dphy_rxesc>,
+                 <&mipitx_dphy_txbytehs>,
+                 <&clkgen JH7110_VOUT_SRC>,
+                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
+            clock-names = "hdmitx0_pixelclk",
+                      "mipitx_dphy_rxesc",
+                      "mipitx_dphy_txbytehs",
+                      "vout_src",
+                      "vout_top_ahb";
+            resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
+            reset-names = "vout_src";
+            #clock-cells = <1>;
+            power-domains = <&pwrc JH7110_PD_VOUT>;
+            status = "okay";
+        };
+
+        clkisp: clock-controller@19810000 {
+            compatible = "starfive,jh7110-clk-isp";
+            reg = <0x0 0x19810000 0x0 0x10000>;
+            reg-names = "isp";
+            #clock-cells = <1>;
+            clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
+                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
+            clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+                      "u0_sft7110_noc_bus_clk_isp_axi";
+            resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
+                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
+            reset-names = "rst_isp_top_n", "rst_isp_top_axi",
+                      "rst_isp_noc_bus_n";
+            power-domains = <&pwrc JH7110_PD_ISP>;
+            status = "okay";
+        };
+
+        qspi: spi@13010000 {
+            compatible = "cdns,qspi-nor";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0x0 0x13010000 0x0 0x10000
+                0x0 0x21000000 0x0 0x400000>;
+            interrupts = <25>;
+            clocks = <&clkgen JH7110_QSPI_CLK_REF>,
+                 <&clkgen JH7110_QSPI_CLK_APB>,
+                 <&clkgen JH7110_AHB1>,
+                 <&clkgen JH7110_QSPI_CLK_AHB>;
+            clock-names = "clk_ref",
+                      "clk_apb",
+                      "ahb1",
+                      "clk_ahb";
+            resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
+                 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
+                 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
+            cdns,fifo-depth = <256>;
+            cdns,fifo-width = <4>;
+            cdns,trigger-address = <0x0>;
+            spi-max-frequency = <250000000>;
+
+            nor_flash: nor-flash@0 {
+                compatible = "jedec,spi-nor";
+                reg=<0>;
+                cdns,read-delay = <5>;
+                spi-max-frequency = <100000000>;
+                cdns,tshsl-ns = <1>;
+                cdns,tsd2d-ns = <1>;
+                cdns,tchsh-ns = <1>;
+                cdns,tslch-ns = <1>;
+
+                partitions {
+                    compatible = "fixed-partitions";
+                    #address-cells = <1>;
+                    #size-cells = <1>;
+
+                    spl@0 {
+                        reg = <0x0 0x40000>;
+                    };
+                    uboot@100000 {
+                        reg = <0x100000 0x300000>;
+                    };
+                    data@f00000 {
+                        reg = <0xf00000 0x100000>;
+                    };
+                };
+            };
+        };
+
+        otp: otp@17050000 {
+            compatible = "starfive,jh7110-otp";
+            reg = <0x0 0x17050000 0x0 0x10000>;
+            clock-frequency = <4000000>;
+            clocks = <&clkgen JH7110_OTPC_CLK_APB>;
+            clock-names = "apb";
+        };
+
+        usbdrd30: usbdrd{
+            compatible = "starfive,jh7110-cdns3";
+            reg = <0x0 0x10210000 0x0 0x1000>,
+                  <0x0 0x10200000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_USB_125M>,
+                 <&clkgen JH7110_USB0_CLK_APP_125>,
+                 <&clkgen JH7110_USB0_CLK_LPM>,
+                 <&clkgen JH7110_USB0_CLK_STB>,
+                 <&clkgen JH7110_USB0_CLK_USB_APB>,
+                 <&clkgen JH7110_USB0_CLK_AXI>,
+                 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
+                 <&clkgen JH7110_PCIE0_CLK_APB>;
+            clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
+            resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+                 <&rstgen RSTN_U0_CDN_USB_APB>,
+                 <&rstgen RSTN_U0_CDN_USB_AXI>,
+                 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
+            reset-names = "pwrup","apb","axi","utmi", "phy";
+            starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
+            starfive,sys-syscon = <&sys_syscon 0x18>;
+            status = "disabled";
+            #address-cells = <2>;
+            #size-cells = <2>;
+            #interrupt-cells = <1>;
+            ranges;
+            usbdrd_cdns3: usb@10100000 {
+                compatible = "cdns,usb3";
+                reg = <0x0 0x10100000 0x0 0x10000>,
+                      <0x0 0x10110000 0x0 0x10000>,
+                      <0x0 0x10120000 0x0 0x10000>;
+                reg-names = "otg", "xhci", "dev";
+                interrupts = <100>, <108>, <110>;
+                interrupt-names = "host", "peripheral", "otg";
+                phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+                maximum-speed = "super-speed";
+            };
+        };
+
+        timer: timer@13050000 {
+            compatible = "starfive,jh7110-timers";
+            reg = <0x0 0x13050000 0x0 0x10000>;
+            interrupts = <69>, <70>, <71> ,<72>;
+            interrupt-names = "timer0", "timer1",
+                      "timer2", "timer3";
+            clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
+                 <&clkgen JH7110_TIMER_CLK_TIMER1>,
+                 <&clkgen JH7110_TIMER_CLK_TIMER2>,
+                 <&clkgen JH7110_TIMER_CLK_TIMER3>,
+                 <&clkgen JH7110_TIMER_CLK_APB>;
+            clock-names = "timer0", "timer1",
+                      "timer2", "timer3", "apb_clk";
+            resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
+                 <&rstgen RSTN_U0_TIMER_TIMER1>,
+                 <&rstgen RSTN_U0_TIMER_TIMER2>,
+                 <&rstgen RSTN_U0_TIMER_TIMER3>,
+                 <&rstgen RSTN_U0_TIMER_APB>;
+            reset-names = "timer0", "timer1",
+                      "timer2", "timer3", "apb_rst";
+            clock-frequency = <24000000>;
+            status = "okay";
+        };
+
+        wdog: wdog@13070000 {
+            compatible = "starfive,jh7110-wdt";
+            reg = <0x0 0x13070000 0x0 0x10000>;
+            interrupts = <68>;
+            interrupt-names = "wdog";
+            clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
+                 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
+            clock-names = "core_clk", "apb_clk";
+            resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
+                 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
+            reset-names = "rst_apb", "rst_core";
+            timeout-sec = <15>;
+            status = "okay";
+        };
+
+        rtc: rtc@17040000 {
+            compatible = "starfive,jh7110-rtc";
+            reg = <0x0 0x17040000 0x0 0x10000>;
+            interrupts = <10>, <11>, <12>;
+            interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
+            clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
+                 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
+            clock-names = "pclk", "cal_clk";
+            resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
+                 <&rstgen RSTN_U0_RTC_HMS_APB>,
+                 <&rstgen RSTN_U0_RTC_HMS_CAL>;
+            reset-names = "rst_osc", "rst_apb", "rst_cal";
+            rtc,cal-clock-freq = <1000000>;
+            status = "okay";
+        };
+
+        pwrc: power-controller@17030000 {
+            compatible = "starfive,jh7110-pmu";
+            reg = <0x0 0x17030000 0x0 0x10000>;
+            interrupts = <111>;
+            #power-domain-cells = <1>;
+            status = "okay";
+        };
+
+        uart0: serial@10000000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x10000000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART0_CLK_CORE>,
+                 <&clkgen JH7110_UART0_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U0_DW_UART_APB>,
+                <&rstgen RSTN_U0_DW_UART_CORE>;
+            interrupts = <32>;
+            status = "disabled";
+        };
+
+        uart1: serial@10010000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x10010000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART1_CLK_CORE>,
+                 <&clkgen JH7110_UART1_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U1_DW_UART_APB>,
+                <&rstgen RSTN_U1_DW_UART_CORE>;
+            interrupts = <33>;
+            status = "disabled";
+        };
+
+        uart2: serial@10020000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x10020000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART2_CLK_CORE>,
+                 <&clkgen JH7110_UART2_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U2_DW_UART_APB>,
+                <&rstgen RSTN_U2_DW_UART_CORE>;
+            interrupts = <34>;
+            status = "disabled";
+        };
+
+        uart3: serial@12000000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x12000000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART3_CLK_CORE>,
+                 <&clkgen JH7110_UART3_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U3_DW_UART_APB>,
+                <&rstgen RSTN_U3_DW_UART_CORE>;
+            interrupts = <45>;
+            status = "disabled";
+        };
+
+        uart4: serial@12010000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x12010000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART4_CLK_CORE>,
+                 <&clkgen JH7110_UART4_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U4_DW_UART_APB>,
+                <&rstgen RSTN_U4_DW_UART_CORE>;
+            interrupts = <46>;
+            status = "disabled";
+        };
+
+        uart5: serial@12020000 {
+            compatible = "snps,dw-apb-uart";
+            reg = <0x0 0x12020000 0x0 0x10000>;
+            reg-io-width = <4>;
+            reg-shift = <2>;
+            clocks = <&clkgen JH7110_UART5_CLK_CORE>,
+                 <&clkgen JH7110_UART5_CLK_APB>;
+            clock-names = "baudclk", "apb_pclk";
+            resets = <&rstgen RSTN_U5_DW_UART_APB>,
+                <&rstgen RSTN_U5_DW_UART_CORE>;
+            interrupts = <47>;
+            status = "disabled";
+        };
+
+        dma: dma-controller@16050000 {
+            compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
+            reg = <0x0 0x16050000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
+                 <&clkgen JH7110_DMA1P_CLK_AHB>,
+                 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
+            clock-names = "core-clk", "cfgr-clk", "stg_clk";
+            resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
+                 <&rstgen RSTN_U0_DW_DMA1P_AHB>,
+                 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
+            reset-names = "rst_axi", "rst_ahb", "rst_stg";
+            interrupts = <73>;
+            #dma-cells = <2>;
+            dma-channels = <4>;
+            snps,dma-masters = <1>;
+            snps,data-width = <3>;
+            snps,num-hs-if = <56>;
+            snps,block-size = <65536 65536 65536 65536>;
+            snps,priority = <0 1 2 3>;
+            snps,axi-max-burst-len = <16>;
+            status = "disabled";
+        };
+
+        gpio: gpio@13040000 {
+            compatible = "starfive,jh7110-sys-pinctrl";
+            reg = <0x0 0x13040000 0x0 0x10000>;
+            reg-names = "control";
+            clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
+            resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
+            interrupts = <86>;
+            interrupt-controller;
+            #gpio-cells = <2>;
+            ngpios = <64>;
+            status = "okay";
+        };
+
+        gpioa: gpio@17020000 {
+            compatible = "starfive,jh7110-aon-pinctrl";
+            reg = <0x0 0x17020000 0x0 0x10000>;
+            reg-names = "control";
+            resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
+            interrupts = <85>;
+            interrupt-controller;
+            #gpio-cells = <2>;
+            ngpios = <4>;
+            status = "okay";
+        };
+
+        sfctemp: tmon@120e0000  {
+            compatible = "starfive,jh7110-temp";
+            reg = <0x0 0x120e0000 0x0 0x10000>;
+            interrupts = <81>;
+            clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
+                 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
+            clock-names = "sense", "bus";
+            resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
+                 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
+            reset-names = "sense", "bus";
+            #thermal-sensor-cells = <0>;
+            status = "disabled";
+        };
+
+        thermal-zones {
+            cpu-thermal {
+                polling-delay-passive = <250>;
+                polling-delay = <15000>;
+
+                thermal-sensors = <&sfctemp>;
+
+                trips {
+                    cpu_alert0: cpu_alert0 {
+                        /* milliCelsius */
+                        temperature = <75000>;
+                        hysteresis = <2000>;
+                        type = "passive";
+                    };
+
+                    cpu_crit: cpu_crit {
+                        /* milliCelsius */
+                        temperature = <90000>;
+                        hysteresis = <2000>;
+                        type = "critical";
+                    };
+                };
+
+                cooling-maps {
+                    map0 {
+                        trip = <&cpu_alert0>;
+                        cooling-device =
+                            <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                            <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                            <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                            <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                    };
+                };
+            };
+        };
+
+        trng: trng@1600C000 {
+            compatible = "starfive,jh7110-trng";
+            reg = <0x0 0x1600C000 0x0 0x4000>;
+            clocks = <&clkgen JH7110_SEC_HCLK>,
+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+            clock-names = "hclk", "ahb";
+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+            interrupts = <30>;
+            status = "disabled";
+        };
+
+        sec_dma: sec_dma@16008000 {
+            compatible = "arm,pl080", "arm,primecell";
+            arm,primecell-periphid = <0x00041080>;
+            reg = <0x0 0x16008000 0x0 0x4000>;
+            reg-names = "sec_dma";
+            interrupts = <29>;
+            clocks = <&clkgen JH7110_SEC_HCLK>,
+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+            clock-names = "sec_hclk","apb_pclk";
+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+            reset-names = "sec_hre";
+            lli-bus-interface-ahb1;
+            mem-bus-interface-ahb1;
+            memcpy-burst-size = <256>;
+            memcpy-bus-width = <32>;
+            #dma-cells = <2>;
+            status = "disabled";
+        };
+
+        crypto: crypto@16000000 {
+            compatible = "starfive,jh7110-sec";
+            reg = <0x0 0x16000000 0x0 0x4000>,
+                  <0x0 0x16008000 0x0 0x4000>;
+            reg-names = "secreg","secdma";
+            interrupts = <28>, <29>;
+            interrupt-names = "secirq", "dmairq";
+            clocks = <&clkgen JH7110_SEC_HCLK>,
+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+            clock-names = "sec_hclk","sec_ahb";
+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+            reset-names = "sec_hre";
+            enable-side-channel-mitigation = "true";
+            enable-dma = "true";
+            dmas = <&sec_dma 1 2>,
+                   <&sec_dma 0 2>;
+            dma-names = "sec_m","sec_p";
+            status = "disabled";
+        };
+
+        i2c0: i2c@10030000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x10030000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
+                 <&clkgen JH7110_I2C0_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U0_DW_I2C_APB>;
+            interrupts = <35>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c1: i2c@10040000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x10040000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
+                 <&clkgen JH7110_I2C1_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U1_DW_I2C_APB>;
+            interrupts = <36>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c2: i2c@10050000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x10050000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
+                 <&clkgen JH7110_I2C2_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U2_DW_I2C_APB>;
+            interrupts = <37>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c3: i2c@12030000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x12030000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
+                 <&clkgen JH7110_I2C3_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U3_DW_I2C_APB>;
+            interrupts = <48>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c4: i2c@12040000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x12040000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
+                 <&clkgen JH7110_I2C4_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U4_DW_I2C_APB>;
+            interrupts = <49>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c5: i2c@12050000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x12050000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
+                 <&clkgen JH7110_I2C5_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U5_DW_I2C_APB>;
+            interrupts = <50>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        i2c6: i2c@12060000 {
+            compatible = "snps,designware-i2c";
+            reg = <0x0 0x12060000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
+                 <&clkgen JH7110_I2C6_CLK_APB>;
+            clock-names = "ref", "pclk";
+            resets = <&rstgen RSTN_U6_DW_I2C_APB>;
+            interrupts = <51>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        /* unremovable emmc as mmcblk0 */
+        sdio0: sdio0@16010000 {
+            compatible = "starfive,jh7110-sdio";
+            reg = <0x0 0x16010000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
+                 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
+            clock-names = "biu","ciu";
+            resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
+            reset-names = "reset";
+            interrupts = <74>;
+            fifo-depth = <32>;
+            fifo-watermark-aligned;
+            data-addr = <0>;
+            starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
+            status = "disabled";
+        };
+
+        sdio1: sdio1@16020000 {
+            compatible = "starfive,jh7110-sdio";
+            reg = <0x0 0x16020000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
+                 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
+            clock-names = "biu","ciu";
+            resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
+            reset-names = "reset";
+            interrupts = <75>;
+            fifo-depth = <32>;
+            fifo-watermark-aligned;
+            data-addr = <0>;
+            starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
+            status = "disabled";
+        };
+
+        vin_sysctl: vin_sysctl@19800000 {
+            compatible = "starfive,jh7110-vin";
+            reg = <0x0 0x19800000 0x0 0x10000>,
+                <0x0 0x19810000 0x0 0x10000>,
+                <0x0 0x19820000 0x0 0x10000>,
+                <0x0 0x19840000 0x0 0x10000>,
+                <0x0 0x19870000 0x0 0x30000>,
+                <0x0 0x11840000 0x0 0x10000>,
+                <0x0 0x17030000 0x0 0x10000>,
+                <0x0 0x13020000 0x0 0x10000>;
+            reg-names = "csi2rx", "vclk", "vrst", "sctrl",
+                "isp", "trst", "pmu", "syscrg";
+            clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
+                 <&clkisp JH7110_U0_VIN_PCLK>,
+                 <&clkisp JH7110_U0_VIN_SYS_CLK>,
+                 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
+                 <&clkisp JH7110_DVP_INV>,
+                 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
+                 <&clkisp JH7110_MIPI_RX0_PXL>,
+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
+                 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
+                 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
+                 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
+            clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
+                "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
+                "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
+                "clk_pixel_clk_if1", "clk_pixel_clk_if2",
+                "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
+                "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
+                "clk_ispcore_2x", "clk_isp_axi";
+            resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
+                 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
+                 <&rstgen RSTN_U0_VIN_N_PCLK>,
+                 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
+                 <&rstgen RSTN_U0_VIN_P_AXIRD>,
+                 <&rstgen RSTN_U0_VIN_P_AXIWR>,
+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
+                 <&rstgen RSTN_U0_M31DPHY_HW>,
+                 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
+            reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
+                "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
+                "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
+                "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
+                "rst_isp_top_n", "rst_isp_top_axi";
+            starfive,aon-syscon = <&aon_syscon 0x00>;
+            power-domains = <&pwrc JH7110_PD_ISP>;
+            /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
+            interrupts = <92 87 88 89 90>;
+            status = "disabled";
+        };
+
+        jpu: jpu@11900000 {
+            compatible = "starfive,jpu";
+            reg = <0x0 0x13090000 0x0 0x300>;
+            interrupts = <14>;
+            clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
+                 <&clkgen JH7110_CODAJ12_CLK_CORE>,
+                 <&clkgen JH7110_CODAJ12_CLK_APB>,
+                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
+            clock-names = "axi_clk", "core_clk",
+                      "apb_clk", "noc_bus";
+            resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
+                 <&rstgen RSTN_U0_CODAJ12_CORE>,
+                 <&rstgen RSTN_U0_CODAJ12_APB>;
+            reset-names = "rst_axi", "rst_core", "rst_apb";
+            power-domains = <&pwrc JH7110_PD_VDEC>;
+            status = "disabled";
+        };
+
+        vpu_dec: vpu_dec@130A0000 {
+            compatible = "starfive,vdec";
+            reg = <0x0 0x130A0000 0x0 0x10000>;
+            interrupts = <13>;
+            clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
+                 <&clkgen JH7110_WAVE511_CLK_BPU>,
+                 <&clkgen JH7110_WAVE511_CLK_VCE>,
+                 <&clkgen JH7110_WAVE511_CLK_APB>,
+                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
+            clock-names = "axi_clk", "bpu_clk", "vce_clk",
+                      "apb_clk", "noc_bus";
+            resets = <&rstgen RSTN_U0_WAVE511_AXI>,
+                <&rstgen RSTN_U0_WAVE511_BPU>,
+                <&rstgen RSTN_U0_WAVE511_VCE>,
+                <&rstgen RSTN_U0_WAVE511_APB>,
+                <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
+            reset-names = "rst_axi", "rst_bpu", "rst_vce",
+                      "rst_apb", "rst_sram";
+            starfive,vdec_noc_ctrl;
+            power-domains = <&pwrc JH7110_PD_VDEC>;
+            status = "disabled";
+        };
+
+        vpu_enc: vpu_enc@130B0000 {
+            compatible = "starfive,venc";
+            reg = <0x0 0x130B0000 0x0 0x10000>;
+            interrupts = <15>;
+            clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
+                 <&clkgen JH7110_WAVE420L_CLK_BPU>,
+                 <&clkgen JH7110_WAVE420L_CLK_VCE>,
+                 <&clkgen JH7110_WAVE420L_CLK_APB>,
+                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
+            clock-names = "axi_clk", "bpu_clk", "vce_clk",
+                      "apb_clk", "noc_bus";
+            resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
+                 <&rstgen RSTN_U0_WAVE420L_BPU>,
+                 <&rstgen RSTN_U0_WAVE420L_VCE>,
+                 <&rstgen RSTN_U0_WAVE420L_APB>,
+                 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
+            reset-names = "rst_axi", "rst_bpu", "rst_vce",
+                      "rst_apb", "rst_sram";
+            starfive,venc_noc_ctrl;
+            power-domains = <&pwrc JH7110_PD_VENC>;
+            status = "disabled";
+        };
+
+        rstgen: reset-controller {
+            compatible = "starfive,jh7110-reset";
+            reg = <0x0 0x13020000 0x0 0x10000>,
+                <0x0 0x10230000 0x0 0x10000>,
+                <0x0 0x17000000 0x0 0x10000>,
+                <0x0 0x19810000 0x0 0x10000>,
+                <0x0 0x295C0000 0x0 0x10000>;
+            reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
+            #reset-cells = <1>;
+            status = "okay";
+        };
+
+        stmmac_axi_setup: stmmac-axi-config {
+            snps,wr_osr_lmt = <0xf>;
+            snps,rd_osr_lmt = <0xf>;
+            snps,blen = <256 128 64 32 0 0 0>;
+        };
+
+        gmac0: ethernet@16030000 {
+            compatible = "starfive,dwmac","snps,dwmac-5.10a";
+            reg = <0x0 0x16030000 0x0 0x10000>;
+            clock-names = "gtx",
+                "tx",
+                "ptp_ref",
+                "stmmaceth",
+                "pclk",
+                "gtxc",
+                "rmii_rtx";
+            clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
+                 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
+                 <&clkgen JH7110_GMAC0_PTP>,
+                 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
+                 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
+                 <&clkgen JH7110_GMAC0_GTXC>,
+                 <&clkgen JH7110_GMAC0_RMII_RTX>;
+            resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
+                 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
+            reset-names = "ahb", "stmmaceth";
+            interrupts = <7>, <6>, <5> ;
+            interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+            max-frame-size = <9000>;
+            phy-mode = "rgmii-id";
+            snps,multicast-filter-bins = <64>;
+            snps,perfect-filter-entries = <128>;
+            rx-fifo-depth = <2048>;
+            tx-fifo-depth = <2048>;
+            snps,fixed-burst;
+            snps,no-pbl-x8;
+            snps,force_thresh_dma_mode;
+            snps,axi-config = <&stmmac_axi_setup>;
+            snps,tso;
+            snps,en-tx-lpi-clockgating;
+            snps,en-lpi;
+            snps,write-requests = <4>;
+            snps,read-requests = <4>;
+            snps,burst-map = <0x7>;
+            snps,txpbl = <16>;
+            snps,rxpbl = <16>;
+            status = "disabled";
+        };
+
+        gmac1: ethernet@16040000 {
+            compatible = "starfive,dwmac","snps,dwmac-5.10a";
+            reg = <0x0 0x16040000 0x0 0x10000>;
+            clock-names = "gtx",
+                "tx",
+                "ptp_ref",
+                "stmmaceth",
+                "pclk",
+                "gtxc",
+                "rmii_rtx";
+            clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
+                 <&clkgen JH7110_GMAC5_CLK_TX>,
+                 <&clkgen JH7110_GMAC5_CLK_PTP>,
+                 <&clkgen JH7110_GMAC5_CLK_AHB>,
+                 <&clkgen JH7110_GMAC5_CLK_AXI>,
+                 <&clkgen JH7110_GMAC1_GTXC>,
+                 <&clkgen JH7110_GMAC1_RMII_RTX>;
+            resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
+                 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
+            reset-names = "ahb", "stmmaceth";
+            interrupts = <78>, <77>, <76> ;
+            interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+            max-frame-size = <9000>;
+            phy-mode = "rgmii-id";
+            snps,multicast-filter-bins = <64>;
+            snps,perfect-filter-entries = <128>;
+            rx-fifo-depth = <2048>;
+            tx-fifo-depth = <2048>;
+            snps,fixed-burst;
+            snps,no-pbl-x8;
+            snps,force_thresh_dma_mode;
+            snps,axi-config = <&stmmac_axi_setup>;
+            snps,tso;
+            snps,en-tx-lpi-clockgating;
+            snps,en-lpi;
+            snps,write-requests = <4>;
+            snps,read-requests = <4>;
+            snps,burst-map = <0x7>;
+            snps,txpbl = <16>;
+            snps,rxpbl = <16>;
+            status = "disabled";
+        };
+
+        gpu: gpu@18000000 {
+            compatible = "img-gpu";
+            reg = <0x0 0x18000000 0x0 0x100000>,
+                <0x0 0x130C000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_GPU_CORE>,
+                 <&clkgen JH7110_GPU_CLK_APB>,
+                 <&clkgen JH7110_GPU_RTC_TOGGLE>,
+                 <&clkgen JH7110_GPU_CORE_CLK>,
+                 <&clkgen JH7110_GPU_SYS_CLK>,
+                 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
+            clock-names = "clk_bv", "clk_apb", "clk_rtc",
+                    "clk_core", "clk_sys", "clk_axi";
+            resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
+                 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
+            reset-names = "rst_apb", "rst_doma";
+            power-domains = <&pwrc JH7110_PD_GPUA>;
+            interrupts = <82>;
+            current-clock = <8000000>;
+            status = "disabled";
+        };
+
+        can0: can@130d0000 {
+            compatible = "starfive,jh7110-can", "ipms,can";
+            reg = <0x0 0x130d0000 0x0 0x1000>;
+            interrupts = <112>;
+            clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
+                 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
+                 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
+            clock-names = "apb_clk", "core_clk", "timer_clk";
+            resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
+                 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
+                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
+            reset-names = "rst_apb", "rst_core", "rst_timer";
+            frequency = <40000000>;
+            starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
+            syscon,can_or_canfd = <0>;
+            status = "disabled";
+        };
+
+        can1: can@130e0000 {
+            compatible = "starfive,jh7110-can", "ipms,can";
+            reg = <0x0 0x130e0000 0x0 0x1000>;
+            interrupts = <113>;
+            clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
+                 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
+                 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
+            clock-names = "apb_clk", "core_clk", "timer_clk";
+            resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
+                 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
+                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
+            reset-names = "rst_apb", "rst_core", "rst_timer";
+            frequency = <40000000>;
+            starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
+            syscon,can_or_canfd = <1>;
+            status = "disabled";
+        };
+
+        tdm: tdm@10090000 {
+            compatible = "starfive,jh7110-tdm";
+            reg = <0x0 0x10090000 0x0 0x1000>;
+            reg-names = "tdm";
+            clocks = <&clkgen JH7110_TDM_CLK_AHB>,
+                 <&clkgen JH7110_TDM_CLK_APB>,
+                 <&clkgen JH7110_TDM_INTERNAL>,
+                 <&tdm_ext>,
+                 <&clkgen JH7110_TDM_CLK_TDM>,
+                 <&clkgen JH7110_MCLK_INNER>;
+            clock-names = "clk_tdm_ahb", "clk_tdm_apb",
+                      "clk_tdm_internal", "clk_tdm_ext",
+                      "clk_tdm", "mclk_inner";
+            resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
+                 <&rstgen RSTN_U0_TDM16SLOT_APB>,
+                 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
+            reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
+            dmas = <&dma 20 1>, <&dma 21 1>;
+            dma-names = "rx","tx";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        spdif0: spdif0@100a0000 {
+            compatible = "starfive,jh7110-spdif";
+            reg = <0x0 0x100a0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
+                 <&clkgen JH7110_SPDIF_CLK_CORE>,
+                 <&clkgen JH7110_AUDIO_ROOT>,
+                 <&clkgen JH7110_MCLK_INNER>,
+                 <&mclk_ext>, <&clkgen JH7110_MCLK>;
+            clock-names = "spdif-apb", "spdif-core",
+                      "audroot", "mclk_inner",
+                      "mclk_ext", "mclk";
+            resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
+            reset-names = "rst_apb";
+            interrupts = <84>;
+            interrupt-names = "tx";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        pwmdac: pwmdac@100b0000 {
+            compatible = "starfive,jh7110-pwmdac";
+            reg = <0x0 0x100b0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_APB0>,
+                 <&clkgen JH7110_PWMDAC_CLK_APB>,
+                 <&clkgen JH7110_PWMDAC_CLK_CORE>;
+            clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
+            resets = <&rstgen RSTN_U0_PWMDAC_APB>;
+            reset-names = "rst-apb";
+            dmas = <&dma 22 1>;
+            dma-names = "tx";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        i2stx: i2stx@100c0000 {
+            compatible = "snps,designware-i2stx";
+            reg = <0x0 0x100c0000 0x0 0x1000>;
+            interrupt-names = "tx";
+            #sound-dai-cells = <0>;
+            dmas = <&dma 28 1>;
+            dma-names = "rx";
+            status = "disabled";
+        };
+
+        pdm: pdm@100d0000 {
+            compatible = "starfive,jh7110-pdm";
+            reg = <0x0 0x100d0000 0x0 0x1000>;
+            reg-names = "pdm";
+            clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
+                 <&clkgen JH7110_PDM_CLK_APB>,
+                 <&clkgen JH7110_MCLK>,
+                 <&mclk_ext>;
+            clock-names = "pdm_mclk",
+                      "pdm_apb", "clk_mclk",
+                      "mclk_ext";
+            resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
+                 <&rstgen RSTN_U0_PDM_4MIC_APB>;
+            reset-names = "pdm_dmic", "pdm_apb";
+            #sound-dai-cells = <0>;
+        };
+
+        i2srx_mst: i2srx_mst@100e0000 {
+            compatible = "starfive,jh7110-i2srx-master";
+            reg = <0x0 0x100e0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_APB0>,
+                 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
+                 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
+                 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
+                 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
+                 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
+                 <&clkgen JH7110_MCLK>,
+                 <&mclk_ext>;
+            clock-names = "apb0", "i2srx_apb",
+                      "i2srx_bclk_mst", "i2srx_lrck_mst",
+                      "i2srx_bclk", "i2srx_lrck",
+                      "mclk", "mclk_ext";
+            resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
+                 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
+            reset-names = "rst_apb_rx", "rst_bclk_rx";
+            dmas = <&dma 24 1>;
+            dma-names = "rx";
+            starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        i2srx_3ch: i2srx_3ch@100e0000 {
+            compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
+            reg = <0x0 0x100e0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_APB0>,
+                 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
+                 <&clkgen JH7110_AUDIO_ROOT>,
+                 <&clkgen JH7110_MCLK_INNER>,
+                 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
+                 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
+                 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
+                 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
+                 <&clkgen JH7110_MCLK>,
+                 <&mclk_ext>,
+                 <&i2srx_bclk_ext>,
+                 <&i2srx_lrck_ext>;
+            clock-names = "apb0", "3ch-apb",
+                      "audioroot", "mclk-inner",
+                      "bclk_mst", "3ch-lrck",
+                      "rx-bclk", "rx-lrck",
+                      "mclk", "mclk_ext",
+                      "bclk-ext", "lrck-ext";
+            resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
+                 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
+            dmas = <&dma 24 1>;
+            dma-names = "rx";
+            starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        i2stx_4ch0: i2stx_4ch0@120b0000 {
+            compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
+            reg = <0x0 0x120b0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_MCLK_INNER>,
+                 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
+                 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
+                 <&clkgen JH7110_MCLK>,
+                 <&clkgen JH7110_I2STX0_4CHBCLK>,
+                 <&clkgen JH7110_I2STX0_4CHLRCK>,
+                 <&clkgen JH7110_I2STX0_4CHCLK_APB>,
+                 <&mclk_ext>;
+            clock-names = "inner", "bclk-mst",
+                    "lrck-mst", "mclk",
+                    "bclk0", "lrck0",
+                    "i2s_apb", "mclk_ext";
+            resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
+                 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
+            reset-names = "rst_apb", "rst_bclk";
+            dmas = <&dma 47 1>;
+            dma-names = "tx";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        i2stx_4ch1: i2stx_4ch1@120c0000 {
+            compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
+            reg = <0x0 0x120c0000 0x0 0x1000>;
+            clocks = <&clkgen JH7110_AUDIO_ROOT>,
+                 <&clkgen JH7110_MCLK_INNER>,
+                 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
+                 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
+                 <&clkgen JH7110_MCLK>,
+                 <&clkgen JH7110_I2STX1_4CHBCLK>,
+                 <&clkgen JH7110_I2STX1_4CHLRCK>,
+                 <&clkgen JH7110_MCLK_OUT>,
+                 <&clkgen JH7110_APB0>,
+                 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
+                 <&mclk_ext>,
+                 <&i2stx_bclk_ext>,
+                 <&i2stx_lrck_ext>;
+            clock-names = "audroot", "mclk_inner", "bclk_mst",
+                      "lrck_mst", "mclk", "4chbclk",
+                      "4chlrck", "mclk_out",
+                      "apb0", "clk_apb",
+                      "mclk_ext", "bclk_ext", "lrck_ext";
+            resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
+                 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
+            dmas = <&dma 48 1>;
+            dma-names = "tx";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        ptc: pwm@120d0000 {
+            compatible = "starfive,jh7110-pwm";
+            reg = <0x0 0x120d0000 0x0 0x10000>;
+            reg-names = "control";
+            clocks = <&clkgen JH7110_PWM_CLK_APB>;
+            resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
+            starfive,approx-freq = <2000000>;
+            #pwm-cells=<3>;
+            starfive,npwm = <8>;
+            status = "disabled";
+        };
+
+        spdif_transmitter: spdif_transmitter {
+            compatible = "linux,spdif-dit";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        pwmdac_codec: pwmdac-transmitter {
+            compatible = "starfive,jh7110-pwmdac-dit";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        dmic_codec: dmic_codec {
+            compatible = "dmic-codec";
+            #sound-dai-cells = <0>;
+            status = "disabled";
+        };
+
+        spi0: spi@10060000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x10060000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI0_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <38>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 14 1>, <&dma 15 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi1: spi@10070000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x10070000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI1_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <39>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 16 1>, <&dma 17 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi2: spi@10080000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x10080000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI2_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <40>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 18 1>, <&dma 19 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi3: spi@12070000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x12070000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI3_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <52>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 39 1>, <&dma 40 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi4: spi@12080000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x12080000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI4_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <53>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 41 1>, <&dma 42 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi5: spi@12090000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x12090000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI5_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <54>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 43 1>, <&dma 44 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        spi6: spi@120A0000 {
+            compatible = "arm,pl022", "arm,primecell";
+            reg = <0x0 0x120A0000 0x0 0x10000>;
+            clocks = <&clkgen JH7110_SPI6_CLK_APB>;
+            clock-names = "apb_pclk";
+            resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
+            reset-names = "rst_apb";
+            interrupts = <55>;
+            /* shortage of dma channel that not be used */
+            /*dmas = <&dma 45 1>, <&dma 46 1>;*/
+            /*dma-names = "rx","tx";*/
+            arm,primecell-periphid = <0x00041022>;
+            num-cs = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            status = "disabled";
+        };
+
+        pcie0: pcie@2B000000 {
+            compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            #interrupt-cells = <1>;
+            reg = <0x0 0x2B000000 0x0 0x1000000
+                   0x9 0x40000000 0x0 0x10000000>;
+            reg-names = "reg", "config";
+            device_type = "pci";
+            starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
+            starfive,phyctrl = <&phyctrl0 0x28 0x80>;
+            bus-range = <0x0 0xff>;
+            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+                 <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+            msi-parent = <&plic>;
+            interrupts = <56>;
+            interrupt-controller;
+            interrupt-names = "msi";
+            interrupt-parent = <&plic>;
+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+            interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+                    <0x0 0x0 0x0 0x2 &plic 0x2>,
+                    <0x0 0x0 0x0 0x3 &plic 0x3>,
+                    <0x0 0x0 0x0 0x4 &plic 0x4>;
+            resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
+                 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
+            reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+                      "rst_brg", "rst_core", "rst_apb";
+            clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+                 <&clkgen JH7110_PCIE0_CLK_TL>,
+                 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
+                 <&clkgen JH7110_PCIE0_CLK_APB>;
+            clock-names = "noc", "tl", "axi_mst0", "apb";
+            status = "disabled";
+        };
+
+        pcie1: pcie@2C000000 {
+            compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            #interrupt-cells = <1>;
+            reg = <0x0 0x2C000000 0x0 0x1000000
+                   0x9 0xc0000000 0x0 0x10000000>;
+            reg-names = "reg", "config";
+            device_type = "pci";
+            starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
+            starfive,phyctrl = <&phyctrl1 0x28 0x80>;
+            bus-range = <0x0 0xff>;
+            ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+                 <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+            msi-parent = <&plic>;
+            interrupts = <57>;
+            interrupt-controller;
+            interrupt-names = "msi";
+            interrupt-parent = <&plic>;
+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+            interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+                    <0x0 0x0 0x0 0x2 &plic 0x2>,
+                    <0x0 0x0 0x0 0x3 &plic 0x3>,
+                    <0x0 0x0 0x0 0x4 &plic 0x4>;
+            resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
+                 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
+                 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
+                 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
+                 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
+                 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
+            reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+                      "rst_brg", "rst_core", "rst_apb";
+            clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+                 <&clkgen JH7110_PCIE1_CLK_TL>,
+                 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
+                 <&clkgen JH7110_PCIE1_CLK_APB>;
+            clock-names = "noc", "tl", "axi_mst0", "apb";
+            status = "disabled";
+        };
+
+        mailbox_contrl0: mailbox@0 {
+            compatible = "starfive,mail_box";
+            reg = <0x0 0x13060000 0x0 0x0001000>;
+            clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
+            clock-names = "clk_apb";
+            resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
+            reset-names = "mbx_rre";
+            interrupts = <26 27>;
+            #mbox-cells = <2>;
+            status = "disabled";
+        };
+
+        mailbox_client0: mailbox_client@0 {
+            compatible = "starfive,mailbox-test";
+            mbox-names = "rx", "tx";
+            mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
+            status = "disabled";
+        };
+
+        display: display-subsystem {
+            compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
+            ports = <&dc_out_dpi0>;
+            status = "disabled";
+        };
+
+        dssctrl: dssctrl@295B0000 {
+            compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
+            reg = <0 0x295B0000 0 0x90>;
+        };
+
+        tda988x_pin: tda988x_pin {
+            compatible = "starfive,tda998x_rgb_pin";
+            status = "disabled";
+        };
+
+        rgb_output: rgb-output {
+            compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
+            //verisilicon,dss-syscon = <&dssctrl>;
+            //verisilicon,mux-mask = <0x70 0x380>;
+            //verisilicon,mux-val = <0x40 0x280>;
+            status = "disabled";
+        };
+
+        dc8200: dc8200@29400000 {
+            compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
+            verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
+            reg = <0x0 0x29400000 0x0 0x100>,
+                  <0x0 0x29400800 0x0 0x2000>,
+                  <0x0 0x17030000 0x0 0x1000>;
+            interrupts = <95>;
+            status = "disabled";
+            clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
+            <&clkgen JH7110_VOUT_SRC>,
+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
+            <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
+            <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
+            <&clkvout JH7110_U0_DC8200_CLK_AXI>,
+            <&clkvout JH7110_U0_DC8200_CLK_CORE>,
+            <&clkvout JH7110_U0_DC8200_CLK_AHB>,
+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+            <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
+            <&hdmitx0_pixelclk>,
+            <&clkvout JH7110_DC8200_PIX0>,
+            <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
+            <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
+            clock-names = "noc_disp","vout_src",
+               "top_vout_axi","top_vout_ahb",
+               "pix_clk","vout_pix1",
+               "axi_clk","core_clk","vout_ahb",
+               "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
+               "dc8200_pix0_out","dc8200_pix1_out";
+            resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
+                 <&rstgen RSTN_U0_DC8200_AXI>,
+                 <&rstgen RSTN_U0_DC8200_AHB>,
+                 <&rstgen RSTN_U0_DC8200_CORE>,
+                 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
+            reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
+                    "rst_noc_disp";
+        };
+
+        dsi_output: dsi-output {
+            compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
+            status = "disabled";
+        };
+
+        mipi_dphy: mipi-dphy@295e0000{
+            compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
+            reg = <0x0 0x295e0000 0x0 0x10000>;
+            clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
+            clock-names = "dphy_txesc";
+            resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
+                 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
+            reset-names = "dphy_sys", "dphy_txbytehs";
+            #phy-cells = <0>;
+            status = "disabled";
+        };
+
+         mipi_dsi: mipi@295d0000 {
+            compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
+            reg = <0x0 0x295d0000 0x0 0x10000>;
+            interrupts = <98>;
+            reg-names = "dsi";
+            clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
+            clock-names = "sys", "apb", "txesc", "dpi";
+            resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
+                 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
+                 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
+                 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
+                 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
+                 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
+            reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
+                    "dsi_sys", "dsi_txbytehs", "dsi_txesc";
+            phys = <&mipi_dphy>;
+            phy-names = "dphy";
+            status = "disabled";
+
+        };
+
+        hdmi: hdmi@29590000 {
+            compatible = "starfive,jh7110-hdmi","inno,hdmi";
+            reg = <0x0 0x29590000 0x0 0x4000>;
+            interrupts = <99>;
+            /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
+            /*clocks = <&cru  PCLK_HDMI>;*/
+            /*clock-names = "pclk";*/
+            /*pinctrl-names = "default";*/
+            /*pinctrl-0 = <&hdmi_ctl>;*/
+            status = "disabled";
+            clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
+                 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
+                 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
+                 <&hdmitx0_pixelclk>;
+            clock-names = "sysclk", "mclk","bclk","pclk";
+            resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
+            reset-names = "hdmi_tx";
+            #sound-dai-cells = <0>;
+        };
+
+        sound0: snd-card0 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-AC108-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound1: snd-card1 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-HDMI-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound2: snd-card2 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-PDM-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound3: snd-card3 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound4: snd-card4 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound5: snd-card5 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-TDM-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        sound6: snd-card6 {
+            compatible = "simple-audio-card";
+            simple-audio-card,name = "Starfive-WM8960-Sound-Card";
+            #address-cells = <1>;
+            #size-cells = <0>;
+        };
+
+        co_process: e24@0 {
+            compatible = "starfive,e24";
+            reg = <0x0 0xc0110000 0x0 0x00001000>,
+                <0x0 0xc0111000 0x0 0x0001f000>;
+            reg-names = "ecmd", "espace";
+            clocks = <&clkgen JH7110_E2_RTC_CLK>,
+                 <&clkgen JH7110_E2_CLK_CORE>,
+                 <&clkgen JH7110_E2_CLK_DBG>;
+            clock-names = "clk_rtc", "clk_core", "clk_dbg";
+            resets = <&rstgen RSTN_U0_E24_CORE>;
+            reset-names = "e24_core";
+            starfive,stg-syscon = <&stg_syscon>;
+            interrupt-parent = <&plic>;
+            firmware-name = "e24_elf";
+            irq-mode = <1>;
+            mbox-names = "tx", "rx";
+            mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
+            status = "disabled";
+            dsp@0 {};
+        };
+
+        xrp: xrp@0 {
+            compatible = "cdns,xrp";
+            reg = <0x0  0x10230000 0x0 0x00010000
+                0x0  0x10240000 0x0 0x00010000>;
+            memory-region = <&xrp_reserved>;
+            clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
+            clock-names = "core_clk";
+            resets = <&rstgen RSTN_U0_HIFI4_CORE>,
+                 <&rstgen RSTN_U0_HIFI4_AXI>;
+            reset-names = "rst_core","rst_axi";
+            starfive,stg-syscon = <&stg_syscon>;
+            firmware-name = "hifi4_elf";
+            #address-cells = <1>;
+            #size-cells = <1>;
+            ranges = <0x40000000 0x0 0x20000000 0x040000
+                0xf0000000 0x0 0xf0000000 0x03000000>;
+            status = "disabled";
+            dsp@0 {
+            };
+        };
+
+        starfive_cpufreq: starfive,jh7110-cpufreq {
+            compatible = "starfive,jh7110-cpufreq";
+            clocks = <&clkgen JH7110_CPU_CORE>;
+            clock-names = "cpu_clk";
+        };
+    };
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi
new file mode 100644
index 000000000000..ed2883b5d02f
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi
@@ -0,0 +1,26 @@
+/** @file
+  Device tree defination all JH7110 pwmdac audio for StarFive VisionFive 2 platform
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+&sound3 {
+    simple-audio-card,dai-link@0 {
+        reg = <0>;
+        format = "left_j";
+        bitclock-master = <&sndcpu0>;
+        frame-master = <&sndcpu0>;
+        status = "okay";
+
+        sndcpu0: cpu {
+            sound-dai = <&pwmdac>;
+        };
+
+        codec {
+            sound-dai = <&pwmdac_codec>;
+        };
+    };
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts
new file mode 100644
index 000000000000..6649c5b9dc00
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts
@@ -0,0 +1,211 @@
+/** @file
+  Device tree defination for StarFive VisionFive 2 platform
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/dts-v1/;
+#include "StarFiveVisionFive2.dtsi"
+#include "StarFiveHdmi.dtsi"
+
+/ {
+    model = "StarFive VisionFive V2";
+    compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+    gpio-restart {
+        compatible = "gpio-restart";
+        gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+        priority = <160>;
+    };
+
+};
+
+&gpio {
+    uart0_pins: uart0-pins {
+        uart0-pins-tx {
+            starfive,pins = <PAD_GPIO5>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_UART0_SOUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        uart0-pins-rx {
+            starfive,pins = <PAD_GPIO6>;
+            starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+            starfive,pin-gpio-din =  <GPI_UART0_SIN>;
+        };
+    };
+
+    i2c2_pins: i2c2-pins {
+        i2c2-pins-scl {
+            starfive,pins = <PAD_GPIO3>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C2_IC_CLK_IN_A>;
+        };
+
+        i2c2-pins-sda {
+            starfive,pins = <PAD_GPIO2>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C2_IC_DATA_IN_A>;
+        };
+    };
+
+    mmc0_pins: mmc0-pins {
+         mmc0-pins-rest {
+            starfive,pins = <PAD_GPIO62>;
+            starfive,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    sdcard1_pins: sdcard1-pins {
+        sdcard1-pins0 {
+            starfive,pins = <PAD_GPIO10>;
+            starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        sdcard1-pins1 {
+            starfive,pins = <PAD_GPIO9>;
+            starfive,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+            starfive,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+            starfive,pin-gpio-din =  <GPI_SDIO1_CCMD_IN>;
+        };
+
+        sdcard1-pins2 {
+            starfive,pins = <PAD_GPIO11>;
+            starfive,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_0>;
+        };
+
+        sdcard1-pins3 {
+            starfive,pins = <PAD_GPIO12>;
+            starfive,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_1>;
+        };
+
+        sdcard1-pins4 {
+            starfive,pins = <PAD_GPIO7>;
+            starfive,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_2>;
+        };
+
+        sdcard1-pins5 {
+            starfive,pins = <PAD_GPIO8>;
+            starfive,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;
+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_3>;
+        };
+    };
+
+    inno_hdmi_pins: inno_hdmi-pins {
+        inno_hdmi-scl {
+            starfive,pins = <PAD_GPIO0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;
+            starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;
+            starfive,pin-gpio-din =  <GPI_HDMI0_DDC_SCL_IN>;
+        };
+
+        inno_hdmi-sda {
+            starfive,pins = <PAD_GPIO1>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;
+            starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;
+            starfive,pin-gpio-din =  <GPI_HDMI0_DDC_SDA_IN>;
+        };
+        inno_hdmi-cec-pins {
+            starfive,pins = <PAD_GPIO14>;
+            //starfive,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;
+            starfive,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;
+            starfive,pin-gpio-din =  <GPI_HDMI0_CEC_SDA_IN>;
+        };
+        inno_hdmi-hpd-pins {
+            starfive,pins = <PAD_GPIO15>;
+            //starfive,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+            starfive,pin-gpio-din =  <GPI_HDMI0_HPD>;
+        };
+    };
+
+    mclk_ext_pins: mclk_ext_pins {
+        mclk_ext_pins {
+            starfive,pins = <PAD_GPIO4>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-din = <GPI_CRG0_EXT_MCLK>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+};
+
+&uart0 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&uart0_pins>;
+    status = "okay";
+};
+
+&i2c2 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2c2_pins>;
+    status = "okay";
+};
+
+&sdio0 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&mmc0_pins>;
+    status = "okay";
+};
+
+&sdio1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&sdcard1_pins>;
+    //cd-gpios = <&gpio 41 0>;
+    status = "okay";
+};
+
+&hdmi {
+    status = "okay";
+    pinctrl-names = "default";
+    pinctrl-0 = <&inno_hdmi_pins>;
+};
+
+&i2stx_4ch0 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&mclk_ext_pins>;
+    status = "okay";
+};
+
+&cpu1 {
+    cpu-supply = <&cpu_vdd>;
+    clocks = <&clkgen JH7110_CPU_CORE>;
+    clock-names = "cpu";
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi
new file mode 100755
index 000000000000..f56307568874
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi
@@ -0,0 +1,838 @@
+/** @file
+  Device tree defination for StarFive VisionFive 2 platform
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/dts-v1/;
+#include "StarFiveJH7110.dtsi"
+#include "StarFivePwmDac.dtsi"
+#include "JH7110PinCtrl.h"
+#include "Gpio.h"
+#include "Led.h"
+
+/ {
+    model = "StarFive VisionFive V2";
+    compatible = "starfive,visionfive-v2", "starfive,jh7110";
+
+    aliases {
+        spi0 = &qspi;
+        gpio0 = &gpio;
+        ethernet0 = &gmac0;
+        ethernet1 = &gmac1;
+        mmc0 = &sdio0;
+        mmc1 = &sdio1;
+        serial0 = &uart0;
+        serial3 = &uart3;
+        i2c0 = &i2c0;
+        i2c1 = &i2c1;
+        i2c2 = &i2c2;
+        i2c3 = &i2c3;
+        i2c4 = &i2c4;
+        i2c5 = &i2c5;
+        i2c6 = &i2c6;
+    };
+
+    chosen {
+        linux,initrd-start = <0x0 0x46100000>;
+        linux,initrd-end = <0x0 0x4c000000>;
+        stdout-path = "serial0:115200";
+        #bootargs = "debug console=ttyS0 rootwait";
+    };
+
+    cpus {
+        timebase-frequency = <4000000>;
+    };
+
+    memory@40000000 {
+        device_type = "memory";
+        reg = <0x0 0x40000000 0x1 0x0>;
+    };
+
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        linux,cma {
+            compatible = "shared-dma-pool";
+            reusable;
+            size = <0x0 0x20000000>;
+            alignment = <0x0 0x1000>;
+            alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
+            linux,cma-default;
+        };
+
+        e24_mem: e24@c0000000 {
+            no-map;
+            reg = <0x0 0xc0110000 0x0 0xf0000>;
+        };
+
+        xrp_reserved: xrpbuffer@f0000000 {
+            reg = <0x0 0xf0000000 0x0 0x01ffffff
+                0x0 0xf2000000 0x0 0x00001000
+                0x0 0xf2001000 0x0 0x00fff000
+                0x0 0xf3000000 0x0 0x00001000>;
+        };
+
+    };
+
+    leds {
+        compatible = "gpio-leds";
+
+        led-ack {
+            gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+            color = <LED_COLOR_ID_GREEN>;
+            function = LED_FUNCTION_HEARTBEAT;
+            linux,default-trigger = "heartbeat";
+            label = "ack";
+        };
+    };
+};
+
+&gpio {
+    i2c0_pins: i2c0-pins {
+        i2c0-pins-scl {
+            starfive,pins = <PAD_GPIO57>;
+            starfive,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C0_IC_CLK_IN_A>;
+        };
+
+        i2c0-pins-sda {
+            starfive,pins = <PAD_GPIO58>;
+            starfive,pinmux = <PAD_GPIO58_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C0_IC_DATA_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C0_IC_DATA_IN_A>;
+        };
+    };
+
+    i2c5_pins: i2c5-pins {
+        i2c5-pins-scl {
+            starfive,pins = <PAD_GPIO19>;
+            starfive,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C5_IC_CLK_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C5_IC_CLK_IN_A>;
+        };
+
+        i2c5-pins-sda {
+            starfive,pins = <PAD_GPIO20>;
+            starfive,pinmux = <PAD_GPIO20_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C5_IC_DATA_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C5_IC_DATA_IN_A>;
+        };
+    };
+
+    i2c6_pins: i2c6-pins {
+        i2c6-pins-scl {
+            starfive,pins = <PAD_GPIO16>;
+            starfive,pinmux = <PAD_GPIO16_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C6_IC_CLK_IN_A>;
+        };
+
+        i2c6-pins-sda {
+            starfive,pins = <PAD_GPIO17>;
+            starfive,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_I2C6_IC_DATA_OE>;
+            starfive,pin-gpio-din =  <GPI_I2C6_IC_DATA_IN_A>;
+        };
+    };
+
+    csi_pins: csi-pins {
+        csi-pins-pwdn {
+            starfive,pins = <PAD_GPIO18>;
+            starfive,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_HIGH>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pwmdac0_pins: pwmdac0-pins {
+        pwmdac0-pins-left {
+            starfive,pins = <PAD_GPIO33>;
+            starfive,pinmux = <PAD_GPIO33_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        pwmdac0-pins-right {
+            starfive,pins = <PAD_GPIO34>;
+            starfive,pinmux = <PAD_GPIO34_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;
+            starfive,pin-gpio-dout = <GPO_PWMDAC0_RIGHT_OUTPUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pwm_pins: pwm-pins {
+        pwm_ch0-pins {
+            starfive,pins = <PAD_GPIO46>;
+            starfive,pinmux = <PAD_GPIO46_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_PTC0_PWM_0>;
+            starfive,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
+        };
+
+        pwm_ch1-pins {
+            starfive,pins = <PAD_GPIO59>;
+            starfive,pinmux = <PAD_GPIO59_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_PTC0_PWM_1>;
+            starfive,pin-gpio-doen = <OEN_PTC0_PWM_1_OE_N>;
+        };
+    };
+
+    ssp0_pins: ssp0-pins {
+        ssp0-pins_tx {
+            starfive,pins = <PAD_GPIO52>;
+            starfive,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_SPI0_SSPTXD>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        ssp0-pins_rx {
+            starfive,pins = <PAD_GPIO53>;
+            starfive,pinmux = <PAD_GPIO53_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+            starfive,pin-gpio-din =  <GPI_SPI0_SSPRXD>;
+        };
+
+        ssp0-pins_clk {
+            starfive,pins = <PAD_GPIO48>;
+            starfive,pinmux = <PAD_GPIO48_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+
+        ssp0-pins_cs {
+            starfive,pins = <PAD_GPIO49>;
+            starfive,pinmux = <PAD_GPIO49_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pcie0_perst_default: pcie0_perst_default {
+        perst-pins {
+            starfive,pins = <PAD_GPIO26>;
+            starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_HIGH>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pcie0_perst_active: pcie0_perst_active {
+        perst-pins {
+            starfive,pins = <PAD_GPIO26>;
+            starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pcie0_wake_default: pcie0_wake_default {
+        wake-pins {
+            starfive,pins = <PAD_GPIO32>;
+            starfive,pinmux = <PAD_GPIO32_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+
+    pcie0_clkreq_default: pcie0_clkreq_default {
+        clkreq-pins {
+            starfive,pins = <PAD_GPIO27>;
+            starfive,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+
+    pcie1_perst_default: pcie1_perst_default {
+        perst-pins {
+            starfive,pins = <PAD_GPIO28>;
+            starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_HIGH>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pcie1_perst_active: pcie1_perst_active {
+        perst-pins {
+            starfive,pins = <PAD_GPIO28>;
+            starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_LOW>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    pcie1_wake_default: pcie1_wake_default {
+        wake-pins {
+            starfive,pins = <PAD_GPIO21>;
+            starfive,pinmux = <PAD_GPIO21_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+
+    pcie1_clkreq_default: pcie1_clkreq_default {
+        clkreq-pins {
+            starfive,pins = <PAD_GPIO29>;
+            starfive,pinmux = <PAD_GPIO29_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+
+    usb_pins: usb-pins {
+        drive-vbus-pin {
+            starfive,pins = <PAD_GPIO25>;
+            starfive,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_USB0_DRIVE_VBUS_IO>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+
+    i2srx_pins: i2srx-pins {
+        i2srx-pins0 {
+            starfive,pins = <PAD_GPIO61>;
+            starfive,pinmux = <PAD_GPIO61_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+            starfive,pin-gpio-din =  <GPI_I2SRX0_EXT_SDIN0>;
+        };
+    };
+
+    i2s_clk_pins: i2s-clk0 {
+        i2s-clk0_bclk {
+            starfive,pins = <PAD_GPIO38>;
+            starfive,pinmux = <PAD_GPIO38_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-din = <GPI_I2STX0_BCLK_SLV GPI_I2SRX0_BCLK_SLV>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+
+        i2s-clk0_lrclk {
+            starfive,pins = <PAD_GPIO63>;
+            starfive,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-din = <GPI_I2STX0_LRCK_SLV GPI_I2SRX0_LRCK_SLV>;
+            starfive,pin-gpio-doen = <OEN_HIGH>;
+        };
+    };
+
+    i2stx_pins: i2stx-pins {
+        i2stx-pins0 {
+            starfive,pins = <PAD_GPIO44>;
+            starfive,pinmux = <PAD_GPIO44_FUNC_SEL 0>;
+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;
+            starfive,pin-gpio-dout = <GPO_I2STX_4CH1_SDO0>;
+            starfive,pin-gpio-doen = <OEN_LOW>;
+        };
+    };
+};
+
+&uart0 {
+    status = "okay";
+};
+
+&dma {
+    status = "okay";
+};
+
+&trng {
+    status = "okay";
+};
+
+&crypto {
+    status = "okay";
+};
+
+&sec_dma {
+    status = "okay";
+};
+
+&i2c0 {
+    clock-frequency = <100000>;
+    i2c-sda-hold-time-ns = <300>;
+    i2c-sda-falling-time-ns = <510>;
+    i2c-scl-falling-time-ns = <510>;
+    auto_calc_scl_lhcnt;
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2c0_pins>;
+    status = "okay";
+};
+
+&i2c2 {
+    clock-frequency = <100000>;
+    i2c-sda-hold-time-ns = <300>;
+    i2c-sda-falling-time-ns = <510>;
+    i2c-scl-falling-time-ns = <510>;
+    auto_calc_scl_lhcnt;
+    status = "okay";
+
+    seeed_plane_i2c@45 {
+        compatible = "seeed_panel";
+        reg = <0x45>;
+
+        port {
+            panel_out0: endpoint {
+                remote-endpoint = <&dsi0_output>;
+            };
+        };
+    };
+
+    tinker_ft5406: tinker_ft5406@38 {
+        compatible = "tinker_ft5406";
+        reg = <0x38>;
+    };
+
+    panel_radxa@19 {
+        compatible ="starfive_jadard";
+        reg = <0x19>;
+        reset-gpio = <&gpio 23 0>;
+        enable-gpio = <&gpio 22 0>;
+
+        port {
+            panel_out1: endpoint {
+                remote-endpoint = <&dsi1_output>;
+                };
+        };
+    };
+
+    touchscreen@14 {
+        compatible = "goodix,gt911";
+        reg = <0x14>;
+        irq-gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;
+        reset-gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;
+    };
+};
+
+&i2c5 {
+    clock-frequency = <100000>;
+    i2c-sda-hold-time-ns = <300>;
+    i2c-sda-falling-time-ns = <510>;
+    i2c-scl-falling-time-ns = <510>;
+    auto_calc_scl_lhcnt;
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2c5_pins>;
+    status = "okay";
+
+    eeprom@50 {
+        compatible = "atmel,24c04";
+        reg = <0x50>;
+        pagesize = <16>;
+    };
+
+    pmic: axp15060_reg@36 {
+        compatible = "stf,axp15060-regulator";
+        reg = <0x36>;
+
+        regulators {
+            mipi_0p9: ALDO1 {
+                regulator-boot-on;
+                regulator-compatible = "mipi_0p9";
+                regulator-name = "mipi_0p9";
+                regulator-min-microvolt = <900000>;
+                regulator-max-microvolt = <900000>;
+            };
+            hdmi_0p9: ALDO5 {
+                regulator-boot-on;
+                regulator-compatible = "hdmi_0p9";
+                regulator-name = "hdmi_0p9";
+                regulator-min-microvolt = <900000>;
+                regulator-max-microvolt = <900000>;
+            };
+            hdmi_1p8: ALDO3 {
+                regulator-boot-on;
+                regulator-compatible = "hdmi_1p8";
+                regulator-name = "hdmi_1p8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+            };
+            cpu_vdd: DCDC2 {
+                regulator-boot-on;
+                regulator-always-on;
+                regulator-compatible = "cpu_vdd";
+                regulator-name = "cpu_vdd";
+                regulator-min-microvolt = <500000>;
+                regulator-max-microvolt = <1540000>;
+            };
+        };
+    };
+};
+
+&i2c6 {
+    clock-frequency = <100000>;
+    i2c-sda-hold-time-ns = <300>;
+    i2c-sda-falling-time-ns = <510>;
+    i2c-scl-falling-time-ns = <510>;
+    auto_calc_scl_lhcnt;
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2c6_pins>;
+    status = "okay";
+
+    imx219: imx219@10 {
+        compatible = "sony,imx219";
+        reg = <0x10>;
+        clocks = <&clk_ext_camera>;
+        clock-names = "xclk";
+        //reset-gpio = <&gpio 18 0>;
+        //DOVDD-supply = <&v2v8>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&csi_pins>;
+        rotation = <0>;
+        orientation = <1>; //CAMERA_ORIENTATION_BACK
+
+        port {
+            /* CSI2 bus endpoint */
+            imx219_to_csi2rx0: endpoint {
+                remote-endpoint = <&csi2rx0_from_imx219>;
+                bus-type = <4>;      /* MIPI CSI-2 D-PHY */
+                clock-lanes = <4>;
+                data-lanes = <0 1>;
+                lane-polarities = <0 0 0>;
+                link-frequencies = /bits/ 64 <456000000>;
+            };
+        };
+    };
+};
+
+&sdio0 {
+    max-frequency = <100000000>;
+    card-detect-delay = <300>;
+    bus-width = <8>;
+    cap-mmc-highspeed;
+    mmc-ddr-1_8v;
+    mmc-hs200-1_8v;
+    non-removable;
+    cap-mmc-hw-reset;
+    post-power-on-delay-ms = <200>;
+    status = "okay";
+};
+
+&sdio1 {
+    max-frequency = <100000000>;
+    card-detect-delay = <300>;
+    bus-width = <4>;
+    no-sdio;
+    no-mmc;
+    broken-cd;
+    cap-sd-highspeed;
+    post-power-on-delay-ms = <200>;
+    status = "okay";
+};
+
+&vin_sysctl {
+    /* when use dvp open this pinctrl*/
+    status = "okay";
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@1 {
+            reg = <1>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            /* CSI2 bus endpoint */
+            csi2rx0_from_imx219: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&imx219_to_csi2rx0>;
+                bus-type = <4>;      /* MIPI CSI-2 D-PHY */
+                clock-lanes = <4>;
+                data-lanes = <0 1>;
+                lane-polarities = <0 0 0>;
+                status = "okay";
+            };
+        };
+    };
+};
+
+&sfctemp {
+    status = "okay";
+};
+
+&jpu {
+    status = "okay";
+};
+
+&vpu_dec {
+    status = "okay";
+};
+
+&vpu_enc {
+    status = "okay";
+};
+
+&gmac0 {
+    status = "okay";
+    #address-cells = <1>;
+    #size-cells = <0>;
+    phy0: ethernet-phy@0 {
+        rxc_dly_en = <1>;
+        tx_delay_sel_fe = <5>;
+        tx_delay_sel = <0xa>;
+        tx_inverted_10 = <0x1>;
+        tx_inverted_100 = <0x1>;
+        tx_inverted_1000 = <0x1>;
+    };
+};
+
+&gmac1 {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    status = "okay";
+    phy1: ethernet-phy@1 {
+        tx_delay_sel_fe = <5>;
+        tx_delay_sel = <0>;
+        rxc_dly_en = <0>;
+        tx_inverted_10 = <0x1>;
+        tx_inverted_100 = <0x1>;
+        tx_inverted_1000 = <0x0>;
+    };
+};
+
+&gpu {
+    status = "okay";
+};
+
+&pwmdac {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pwmdac0_pins>;
+    status = "okay";
+};
+
+&i2srx_3ch {
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2s_clk_pins &i2srx_pins>;
+    status = "disabled";
+};
+
+&i2stx_4ch1 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&i2stx_pins>;
+    status = "disabled";
+};
+
+&pwmdac_codec {
+    status = "okay";
+};
+
+&spi0 {
+    pinctrl-names = "default";
+    pinctrl-0 = <&ssp0_pins>;
+    status = "okay";
+
+    spi_dev0: spi@0 {
+        compatible = "rohm,dh2228fv";
+        pl022,com-mode = <1>;
+        spi-max-frequency = <10000000>;
+        reg = <0>;
+        status = "okay";
+    };
+};
+
+&pcie0 {
+    pinctrl-names = "default", "perst-default", "perst-active";
+    pinctrl-0 = <&pcie0_wake_default>,
+            <&pcie0_clkreq_default>;
+    pinctrl-1 = <&pcie0_perst_default>;
+    pinctrl-2 = <&pcie0_perst_active>;
+    status = "okay";
+};
+
+&pcie1 {
+    pinctrl-names = "default", "perst-default", "perst-active";
+    pinctrl-0 = <&pcie1_wake_default>,
+            <&pcie1_clkreq_default>;
+    pinctrl-1 = <&pcie1_perst_default>;
+    pinctrl-2 = <&pcie1_perst_active>;
+    status = "okay";
+};
+
+&mailbox_contrl0 {
+    status = "okay";
+};
+
+&mailbox_client0 {
+    status = "okay";
+};
+
+&display {
+    status = "okay";
+};
+
+&hdmi {
+    status = "okay";
+
+    hdmi_in: port {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        hdmi_in_lcdc: endpoint@0 {
+            reg = <0>;
+            remote-endpoint = <&dc_out_dpi1>;
+        };
+    };
+};
+
+&dc8200 {
+    status = "okay";
+
+    dc_out: port {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        dc_out_dpi0: endpoint@0 {
+            reg = <0>;
+            remote-endpoint = <&hdmi_input0>;
+        };
+        dc_out_dpi1: endpoint@1 {
+            reg = <1>;
+            remote-endpoint = <&hdmi_in_lcdc>;
+        };
+
+        dc_out_dpi2: endpoint@2 {
+            reg = <2>;
+            remote-endpoint = <&mipi_in>;
+        };
+    };
+};
+
+&rgb_output {
+    status = "disabled";
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        port@0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0>;
+            hdmi_input0:endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&dc_out_dpi0>;
+            };
+        };
+    };
+};
+
+&dsi_output {
+    status = "okay";
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@0 {
+            reg = <0>;
+            mipi_in: endpoint {
+                remote-endpoint = <&dc_out_dpi2>;
+            };
+        };
+
+        port@1 {
+            reg = <1>;
+            sf_dpi_output: endpoint {
+                remote-endpoint = <&dsi_in_port>;
+            };
+        };
+    };
+};
+
+&mipi_dsi {
+    status = "okay";
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@0 {
+            reg = <0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            dsi0_output: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&panel_out0>;
+            };
+
+            dsi1_output: endpoint@1 {
+                reg = <1>;
+                remote-endpoint = <&panel_out1>;
+            };
+        };
+
+        port@1{
+            reg = <1>;
+            dsi_in_port: endpoint {
+                remote-endpoint = <&sf_dpi_output>;
+            };
+        };
+
+    };
+};
+
+&mipi_dphy {
+    status = "okay";
+};
+
+&co_process {
+    status = "okay";
+};
+
+&usbdrd30 {
+    clocks = <&clkgen JH7110_USB_125M>,
+         <&clkgen JH7110_USB0_CLK_APP_125>,
+         <&clkgen JH7110_USB0_CLK_LPM>,
+         <&clkgen JH7110_USB0_CLK_STB>,
+         <&clkgen JH7110_USB0_CLK_USB_APB>,
+         <&clkgen JH7110_USB0_CLK_AXI>,
+         <&clkgen JH7110_USB0_CLK_UTMI_APB>;
+    clock-names = "125m","app","lpm","stb","apb","axi","utmi";
+    resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+         <&rstgen RSTN_U0_CDN_USB_APB>,
+         <&rstgen RSTN_U0_CDN_USB_AXI>,
+         <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+    reset-names = "pwrup","apb","axi","utmi";
+    starfive,usb2-only;
+    dr_mode = "peripheral"; /*host or peripheral*/
+    status = "okay";
+};
+
+&xrp {
+    status = "okay";
+};
+
+&ptc {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pwm_pins>;
+    status = "okay";
+};
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h b/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h
new file mode 100644
index 000000000000..48af62f5722e
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h
@@ -0,0 +1,16 @@
+/** @file
+  This header provide all the thermal bindings
+
+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __DT_BINDINGS_THERMAL_H__
+#define __DT_BINDINGS_THERMAL_H__
+
+/* On cooling devices upper and lower limits */
+#define THERMAL_NO_LIMIT  (~0)
+
+#endif /* __DT_BINDINGS_THERMAL_H__ */
diff --git a/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf
new file mode 100644
index 000000000000..75256cbf6406
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf
@@ -0,0 +1,36 @@
+## @file
+#  Device tree description of the StarFive VisionFive 2 platform
+#
+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION    = 0x0001001A
+  BASE_NAME      = VisionFive2DeviceTree
+  FILE_GUID      = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #gDtPlatformDefaultDtbFileGuid
+  MODULE_TYPE    = USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  StarFiveClk.dtsi
+  StarFiveHdmi.dtsi
+  StarFiveVisionFive2.dtsi
+  StarFivePwmDac.dtsi
+  StarFiveVisionFive2.dts
+  StarFiveVisionFive2.dtsi
+  JH7110Rst.h
+  JH7110Power.h
+  JH7110ClkGen.h
+  JH7110ClkIsp.h
+  JH7110ClkVout.h
+  JH7110PinCtrl.h
+  Led.h
+  Irq.h
+  Gpio.h
+  Thermal.h
+
+[Packages]
+  MdePkg/MdePkg.dec
diff --git a/Platform/StarFive/VisionFive2/VarStore.fdf.inc b/Platform/StarFive/VisionFive2/VarStore.fdf.inc
new file mode 100644
index 000000000000..62b4baa43e98
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VarStore.fdf.inc
@@ -0,0 +1,77 @@
+## @file
+#  FDF include file with Layout Regions that define an empty variable store.
+#
+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(VARS_OFFSET)|$(VARS_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#
+# NV_VARIABLE_STORE
+#
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid =
+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
+  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0xC0000
+  0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # Signature "_FVH"       # Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02,
+  # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+  0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
+  # Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  # Signature: gEfiAuthenticatedVariableGuid =
+  #   { 0xaaf32c78, 0x947b, 0x439a,
+  #     { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+  # Signature: gEfiVariableGuid =
+  #   { 0xddcf3616, 0x3275, 0x4164,
+  #     { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+  # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3FFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xFF, 0x03, 0x00,
+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#
+# NV_FTW_WORKING
+#
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64
+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#
+# NV_FTW_SPARE
+#
diff --git a/Platform/StarFive/VisionFive2/VisionFive2.dsc b/Platform/StarFive/VisionFive2/VisionFive2.dsc
new file mode 100644
index 000000000000..d8dd16867c20
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.dsc
@@ -0,0 +1,596 @@
+## @file
+#  RISC-V EFI on StarFive VisionFive 2 platform
+#
+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = VisionFive2
+  PLATFORM_GUID                  = 8317E90F-428B-403F-9057-112B0C19008E
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x0001001c
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = RISCV64
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Platform/StarFive/VisionFive2/VisionFive2.fdf
+
+  #
+  # Enable below options may cause build error or may not work on
+  # the initial version of RISC-V package
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  #
+  DEFINE SECURE_BOOT_ENABLE      = FALSE
+  DEFINE DEBUG_ON_SERIAL_PORT    = FALSE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_SNP_ENABLE       = FALSE
+  DEFINE NETWORK_IP6_ENABLE       = FALSE
+  DEFINE NETWORK_TLS_ENABLE       = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+  DEFINE NETWORK_ISCSI_ENABLE     = FALSE
+
+[BuildOptions]
+  GCC:RELEASE_*_*_CC_FLAGS       = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  GCC:*_*_RISCV64_GENFW_FLAGS    = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+  0|DEFAULT
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include MdePkg/MdeLibs.dsc.inc
+
+[LibraryClasses]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+  SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
+  VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
+  NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf
+
+# RISC-V Platform Library
+  TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
+  RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+# RISC-V Core Library
+  RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+!else
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+  SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf
+  SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf
+  PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf
+!else
+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+!endif
+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+!if $(HTTP_BOOT_ENABLE) == TRUE
+  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+
+  # ACPI not supported yet.
+  #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+  SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
+  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+
+[LibraryClasses.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+  RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+  RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+  RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+  MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
+  CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
+  # Pci dependencies
+  PciHostBridgeLib|Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+  PciSegmentLib|Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.inf
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+
+  # Flattened Device Tree (FDT) access library
+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+[LibraryClasses.common.SEC]
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+
+  ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+  ResetSystemLib|Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+  PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+  PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf
+  PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+  PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+[PcdsFeatureFlag]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+
+[PcdsFixedAtBuild]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0
+
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+!endif
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
+!endif
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
+  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+  gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+  gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+  # F2 for UI APP
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+  # PCIE
+  gJH7110TokenSpaceGuid.PcdPciBusMin|0x00
+  gJH7110TokenSpaceGuid.PcdPciBusMax|0xFF
+  gJH7110TokenSpaceGuid.PcdPciIoBase|0x01
+  gJH7110TokenSpaceGuid.PcdPciIoSize|0x00 #Disable PIO
+  gJH7110TokenSpaceGuid.PcdPciIoOffset|0x00
+  gJH7110TokenSpaceGuid.PcdPci0Mmio32Base|0x30000000
+  gJH7110TokenSpaceGuid.PcdPci0Mmio32Size|0x8000000
+  gJH7110TokenSpaceGuid.PcdPci0Mmio64Base|0x900000000
+  gJH7110TokenSpaceGuid.PcdPci0Mmio64Size|0x40000000
+  gJH7110TokenSpaceGuid.PcdPci1Mmio32Base|0x38000000
+  gJH7110TokenSpaceGuid.PcdPci1Mmio32Size|0x8000000
+  gJH7110TokenSpaceGuid.PcdPci1Mmio64Base|0x980000000
+  gJH7110TokenSpaceGuid.PcdPci1Mmio64Size|0x40000000
+
+  # DW MMC/SD card controller
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x16010000
+  gDesignWareTokenSpaceGuid.PcdDwSdDxeBaseAddress|0x16020000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|198000000
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|198000000
+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|32
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn|FALSE
+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|TRUE
+
+  # SPI
+  gJH7110TokenSpaceGuid.PcdSpiFlashRegBase|0x13010000
+  gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase|0x21000000
+  gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth|4
+  gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz|100000000
+  gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs|1
+  gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs|1
+  gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs|1
+  gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs|1
+
+################################################################################
+#
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsDynamicDefault]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
+
+  #
+  # Set video resolution for boot options and for text setup.
+  # PlatformDxe can set the former at runtime.
+  #
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
+
+  # Set video resolution for text setup.
+  # gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components]
+
+  #
+  # SEC Phase modules
+  #
+  OvmfPkg/RiscVVirt/Sec/SecMain.inf {
+    <LibraryClasses>
+      ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+      LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+      PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+      HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+      PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+      MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+  }
+
+  #
+  # DXE Phase modules
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  }
+
+  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+   MdeModulePkg/Universal/PCD/Dxe/Pcd.inf  {
+   <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  }
+
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+    <LibraryClasses>
+      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+  }
+!else
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+!endif
+
+  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+  MdeModulePkg/Universal/Metronome/Metronome.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {
+    <LibraryClasses>
+      ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf
+  }
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  # MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  # MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  # MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+  #
+  # RISC-V Platform module
+  #
+  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+
+  #
+  # RISC-V Core module
+  #
+  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+      VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
+  }
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+  #
+  # Emulator for x64 OpRoms, etc.
+  #
+  #MultiArchUefiPkg/Drivers/Emulator/Emulator.inf {
+  #    <LibraryClasses>
+  #    UnicornEngineLib|unicorn/efi/UnicornEngineLib.inf
+  #    UnicornStubLib|unicorn/efi/UnicornStubLib.inf
+  #    UnicornX86Lib|unicorn/efi/UnicornX86Lib.inf
+  #}
+
+  # No graphic console supported yet.
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {
+  <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
+    <LibraryClasses>
+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  #
+  # Network Support
+  #
+  !include NetworkPkg/Network.dsc.inc
+
+  #
+  # sdio/mmc support
+  #
+  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf {
+    <BuildOptions>
+      GCC:*_*_*_CC_FLAGS       = -DCONFIG_DWEMMC
+  }
+  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf {
+    <BuildOptions>
+      GCC:*_*_*_CC_FLAGS       = -DCONFIG_DWSDMMC
+  }
+
+  #
+  # PCIe support
+  #
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+  #
+  # NVMe boot devices
+  #
+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+  #
+  # Usb Support
+  #
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning + UDF filesystem
+  #
+  FatPkg/EnhancedFatDxe/Fat.inf
+  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
+
+  #
+  # QSPI Flash Support
+  #
+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf
+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf
+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf
+
+  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
+    <PcdsFixedAtBuild>
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+    <LibraryClasses>
+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+  }
+
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+  MdeModulePkg/Logo/LogoDxe.inf
+  MdeModulePkg/Application/UiApp/UiApp.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+  }
+
+  #
+  # Device Tree Binary
+  # - Compile by EDK2, and will embed into OpenSBI .rodata section using FW_FDT_PATH
+  #   when compiling OpenSBI. EDK2 will get the start address of the device tree from
+  #   register 'a1'
+  #
+  Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf
diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf b/Platform/StarFive/VisionFive2/VisionFive2.fdf
new file mode 100644
index 000000000000..4007258ea588
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf
@@ -0,0 +1,284 @@
+# @file
+#  Flash definition file on StarFive VisionFive 2 platform
+#
+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+!include VisionFive2.fdf.inc
+
+#
+# Build the variable store and the firmware code as one unified flash device
+# image.
+#
+[FD.VisionFive2]
+BaseAddress   = $(FW_BASE_OFFSET)
+Size          = $(FW_SIZE)
+ErasePolarity = 1
+BlockSize     = $(BLOCK_SIZE)
+NumBlocks     = $(BLOCK_NUM)
+
+
+$(FVMAIN_OFFSET)|$(FVMAIN_SIZE)
+gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
+FV = FVMAIN_COMPACT
+
+!include VarStore.fdf.inc
+
+################################################################################
+
+[FV.DXEFV]
+BlockSize          = 0x10000
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
+
+APRIORI DXE {
+  INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf
+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf
+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf
+}
+
+#
+# DXE Phase modules
+#
+INF  MdeModulePkg/Core/Dxe/DxeMain.inf
+
+INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+#
+# Emulator for x64 OpRoms, etc.
+#
+#INF  MultiArchUefiPkg/Drivers/Emulator/Emulator.inf
+
+INF  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+INF  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+INF  MdeModulePkg/Universal/Metronome/Metronome.inf
+INF  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+# RISC-V Core Drivers
+INF  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+INF  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
+
+INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  INF  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+INF  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+INF  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+INF  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+INF  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+#
+# Multiple Console IO support
+#
+INF  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+INF  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+INF  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+INF  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+INF  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+INF  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+INF  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+INF  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+INF  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+INF  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+# INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+# INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+INF  FatPkg/EnhancedFatDxe/Fat.inf
+INF  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
+
+# !ifndef $(SOURCE_DEBUG_ENABLE)
+# INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+# !endif
+
+INF  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
+INF  ShellPkg/Application/Shell/Shell.inf
+
+#
+# Bds
+#
+INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+INF  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf
+INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF  MdeModulePkg/Application/UiApp/UiApp.inf
+
+#
+# Network modules
+#
+!if $(E1000_ENABLE)
+  FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
+    SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI
+  }
+!endif
+
+!include NetworkPkg/Network.fdf.inc
+
+#
+# SDIO/MMC support
+#
+INF  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+INF  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
+INF  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf
+
+#
+# PCIe support
+#
+INF  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+INF  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+# NVMe boot devices
+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+#
+# Usb Support
+#
+INF  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+INF  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+INF  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+INF  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+INF  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+INF  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+INF  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+#
+# TianoCore logo (splash screen)
+#
+INF  MdeModulePkg/Logo/LogoDxe.inf
+
+#
+# QSPI Flash Support
+#
+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf
+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf
+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf
+################################################################################
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+INF OvmfPkg/RiscVVirt/Sec/SecMain.inf
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+   SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+     #
+     # These firmware volumes will have files placed in them uncompressed,
+     # and then both firmware volumes will be compressed in a single
+     # compression operation in order to achieve better overall compression.
+     #
+     SECTION FV_IMAGE = DXEFV
+   }
+ }
+
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED{
+    PE32     PE32   Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING ="$(MODULE_NAME)" Optional
+    VERSION  STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      |.depex
+    PE32      PE32   |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32  |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI               |.acpi
+    RAW ASL                |.aml
+  }
+
+[Rule.Common.USER_DEFINED.DTB]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW BIN                |.dtb
+  }
diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc b/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc
new file mode 100644
index 000000000000..98beda0de77c
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc
@@ -0,0 +1,48 @@
+## @file
+#  Definitions of Flash definition file on StarFive VisionFive 2 platform
+#
+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+#
+# OpenSBI: 0x4000_0000 ~ 0x401F_FFFF
+# EDK2   : 0x4020_0000 ~ 0x40A0_0000
+#
+DEFINE FSBL_SIZE      = 0x00100000 #100MB
+DEFINE OPENSBI_SIZE   = 0x00200000
+DEFINE FW_BASE_OFFSET = 0x40200000
+DEFINE FW_SIZE        = 0x00800000 # (BLOCK_NUM x BLOCK_SIZE)
+
+DEFINE BLOCK_NUM      = 0x800
+DEFINE BLOCK_SIZE     = 0x1000
+
+DEFINE FVMAIN_OFFSET  = 0x00000000 # Offset from FW_BASE end
+DEFINE FVMAIN_SIZE    = 0x00740000
+
+#
+# EFI Variables memory region in Flash.
+#
+DEFINE VARS_OFFSET             = 0x00740000 # Offset from FW_BASE end
+DEFINE VARS_SIZE               = 0x00040000
+DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_SIZE)
+DEFINE VARS_FTW_WORKING_SIZE   = 0x00040000
+DEFINE VARS_FTW_SPARE_OFFSET   = $(VARS_FTW_WORKING_OFFSET) + $(VARS_FTW_WORKING_SIZE)
+DEFINE VARS_FTW_SPARE_SIZE     = 0x00040000
+
+#
+# Memory map use for non-volatile variable offset in flash
+# | FSBL | OPENSBI | EDK2 | EFI VARS | ... |
+#
+SET gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset = $(FSBL_SIZE) + $(OPENSBI_SIZE) + $(VARS_OFFSET)
+
+#
+# Temporary RAM region use for sec startup before memory is discovered
+#
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase = 0x43FF0000
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize = 0x00010000
+
+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency = 24000000 # 24Mhz
-- 
2.34.1



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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [edk2-devel] [PATCH v2 1/1] StarFive/VisionFive2: Add VisionFive 2 platform
@ 2023-10-23  7:19 John Chew
  2023-10-23  7:59 ` John Chew
  0 siblings, 1 reply; 5+ messages in thread
From: John Chew @ 2023-10-23  7:19 UTC (permalink / raw)
  To: devel
  Cc: mindachen1987, Sunil V L, Leif Lindholm, Michael D Kinney,
	Cc : Li Yong, John Chew

From: mindachen1987 <minda.chen@starfivetech.com>

v2:
  - Change PlatformBootManagerLib to:
      Platform/RISC-V/PlatformPkg/.../PlatformBootManagerLib.inf
    [Sunil]
  - Added PCIE PCDs
    PcdPciBusMin, PcdPciBusMax, PcdPciIoBase, PcdPciIoSize
    PcdPciIoOffset, PcdPci0Mmio32Base, PcdPci0Mmio32Size
    PcdPci0Mmio64Base, PcdPci0Mmio64Size, PcdPci1Mmio32Base
    PcdPci1Mmio32Size, PcdPci1Mmio64Base, PcdPci1Mmio64Size
    [John Chew]

v1:
  - Added new platform support for VisionFive2 SBC.
  - Boot flow in VF2 using EDK2 as bootloader:
    BootROM -> U-Boot SPL -> OpenSBI -> EDK2 -> Linux -> OS

  - Supported boot source for Linux from EDK2:
      - SD Card
      - eMMC
      - NVMe
      - USB

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Cc: Li Yong <yong.li@intel.com>
Co-authored-by: John Chew <yuinyee.chew@starfivetech.com>
Signed-off-by: mindachen1987 <minda.chen@starfivetech.com>
---
 Platform/StarFive/VisionFive2/DeviceTree/Gpio.h                    |   42 +
 Platform/StarFive/VisionFive2/DeviceTree/Irq.h                     |   20 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h            |  398 +++++
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h            |   57 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h           |   68 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h           | 1573 +++++++++++++++++
 Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h             |   22 +
 Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h               |  228 +++
 Platform/StarFive/VisionFive2/DeviceTree/Led.h                     |   90 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi          |  130 ++
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi         |   28 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi       | 1812 ++++++++++++++++++++
 Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi       |   26 +
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts   |  211 +++
 Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi  |  838 +++++++++
 Platform/StarFive/VisionFive2/DeviceTree/Thermal.h                 |   16 +
 Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf |   36 +
 Platform/StarFive/VisionFive2/VarStore.fdf.inc                     |   77 +
 Platform/StarFive/VisionFive2/VisionFive2.dsc                      |  596 +++++++
 Platform/StarFive/VisionFive2/VisionFive2.fdf                      |  284 +++
 Platform/StarFive/VisionFive2/VisionFive2.fdf.inc                  |   48 +
 21 files changed, 6600 insertions(+)

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h b/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h
new file mode 100644
index 000000000000..89f4c44eaec0
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Gpio.h
@@ -0,0 +1,42 @@
+/** @file

+  This header provide all the general purpose input/output device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_GPIO_H__

+#define __DT_BINDINGS_GPIO_H__

+

+/* Bit 0 express polarity */

+#define GPIO_ACTIVE_HIGH  0

+#define GPIO_ACTIVE_LOW   1

+

+/* Bit 1 express single-endedness */

+#define GPIO_PUSH_PULL     0

+#define GPIO_SINGLE_ENDED  2

+

+/* Bit 2 express Open drain or open source */

+#define GPIO_LINE_OPEN_SOURCE  0

+#define GPIO_LINE_OPEN_DRAIN   4

+

+/*

+ * Open Drain/Collector is the combination of single-ended open drain interface.

+ * Open Source/Emitter is the combination of single-ended open source interface.

+ */

+#define GPIO_OPEN_DRAIN   (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)

+#define GPIO_OPEN_SOURCE  (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)

+

+/* Bit 3 express GPIO suspend/resume and reset persistence */

+#define GPIO_PERSISTENT  0

+#define GPIO_TRANSITORY  8

+

+/* Bit 4 express pull up */

+#define GPIO_PULL_UP  16

+

+/* Bit 5 express pull down */

+#define GPIO_PULL_DOWN  32

+

+#endif /* __DT_BINDINGS_GPIO_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Irq.h b/Platform/StarFive/VisionFive2/DeviceTree/Irq.h
new file mode 100644
index 000000000000..19d08bc4a816
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Irq.h
@@ -0,0 +1,20 @@
+/** @file

+  This header provide all the interrupt device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__

+#define __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__

+

+#define IRQ_TYPE_NONE          0

+#define IRQ_TYPE_EDGE_RISING   1

+#define IRQ_TYPE_EDGE_FALLING  2

+#define IRQ_TYPE_EDGE_BOTH     (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)

+#define IRQ_TYPE_LEVEL_HIGH    4

+#define IRQ_TYPE_LEVEL_LOW     8

+

+#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h
new file mode 100644
index 000000000000..475967eff848
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkGen.h
@@ -0,0 +1,398 @@
+/** @file

+  This header provide all JH7110 clock generator device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_CLK_GEN_H__

+#define __DT_BINDINGS_JH7110_CLK_GEN_H__

+

+/* sys regisger */

+#define JH7110_CPU_ROOT                     0

+#define JH7110_CPU_CORE                     1

+#define JH7110_CPU_BUS                      2

+#define JH7110_GPU_ROOT                     3

+#define JH7110_PERH_ROOT                    4

+#define JH7110_BUS_ROOT                     5

+#define JH7110_NOCSTG_BUS                   6

+#define JH7110_AXI_CFG0                     7

+#define JH7110_STG_AXIAHB                   8

+#define JH7110_AHB0                         9

+#define JH7110_AHB1                         10

+#define JH7110_APB_BUS_FUNC                 11

+#define JH7110_APB0                         12

+#define JH7110_PLL0_DIV2                    13

+#define JH7110_PLL1_DIV2                    14

+#define JH7110_PLL2_DIV2                    15

+#define JH7110_AUDIO_ROOT                   16

+#define JH7110_MCLK_INNER                   17

+#define JH7110_MCLK                         18

+#define JH7110_MCLK_OUT                     19

+#define JH7110_ISP_2X                       20

+#define JH7110_ISP_AXI                      21

+#define JH7110_GCLK0                        22

+#define JH7110_GCLK1                        23

+#define JH7110_GCLK2                        24

+#define JH7110_U7_CORE_CLK                  25

+#define JH7110_U7_CORE_CLK1                 26

+#define JH7110_U7_CORE_CLK2                 27

+#define JH7110_U7_CORE_CLK3                 28

+#define JH7110_U7_CORE_CLK4                 29

+#define JH7110_U7_DEBUG_CLK                 30

+#define JH7110_U7_RTC_TOGGLE                31

+#define JH7110_U7_TRACE_CLK0                32

+#define JH7110_U7_TRACE_CLK1                33

+#define JH7110_U7_TRACE_CLK2                34

+#define JH7110_U7_TRACE_CLK3                35

+#define JH7110_U7_TRACE_CLK4                36

+#define JH7110_U7_TRACE_COM_CLK             37

+#define JH7110_NOC_BUS_CLK_CPU_AXI          38

+#define JH7110_NOC_BUS_CLK_AXICFG0_AXI      39

+#define JH7110_OSC_DIV2                     40

+#define JH7110_PLL1_DIV4                    41

+#define JH7110_PLL1_DIV8                    42

+#define JH7110_DDR_BUS                      43

+#define JH7110_DDR_CLK_AXI                  44

+#define JH7110_GPU_CORE                     45

+#define JH7110_GPU_CORE_CLK                 46

+#define JH7110_GPU_SYS_CLK                  47

+#define JH7110_GPU_CLK_APB                  48

+#define JH7110_GPU_RTC_TOGGLE               49

+#define JH7110_NOC_BUS_CLK_GPU_AXI          50

+#define JH7110_ISP_TOP_CLK_ISPCORE_2X       51

+#define JH7110_ISP_TOP_CLK_ISP_AXI          52

+#define JH7110_NOC_BUS_CLK_ISP_AXI          53

+#define JH7110_HIFI4_CORE                   54

+#define JH7110_HIFI4_AXI                    55

+#define JH7110_AXI_CFG1_DEC_CLK_MAIN        56

+#define JH7110_AXI_CFG1_DEC_CLK_AHB         57

+#define JH7110_VOUT_SRC                     58

+#define JH7110_VOUT_AXI                     59

+#define JH7110_NOC_BUS_CLK_DISP_AXI         60

+#define JH7110_VOUT_TOP_CLK_VOUT_AHB        61

+#define JH7110_VOUT_TOP_CLK_VOUT_AXI        62

+#define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK    63

+#define JH7110_VOUT_TOP_CLK_MIPIPHY_REF     64

+#define JH7110_JPEGC_AXI                    65

+#define JH7110_CODAJ12_CLK_AXI              66

+#define JH7110_CODAJ12_CLK_CORE             67

+#define JH7110_CODAJ12_CLK_APB              68

+#define JH7110_VDEC_AXI                     69

+#define JH7110_WAVE511_CLK_AXI              70

+#define JH7110_WAVE511_CLK_BPU              71

+#define JH7110_WAVE511_CLK_VCE              72

+#define JH7110_WAVE511_CLK_APB              73

+#define JH7110_VDEC_JPG_ARB_JPGCLK          74

+#define JH7110_VDEC_JPG_ARB_MAINCLK         75

+#define JH7110_NOC_BUS_CLK_VDEC_AXI         76

+#define JH7110_VENC_AXI                     77

+#define JH7110_WAVE420L_CLK_AXI             78

+#define JH7110_WAVE420L_CLK_BPU             79

+#define JH7110_WAVE420L_CLK_VCE             80

+#define JH7110_WAVE420L_CLK_APB             81

+#define JH7110_NOC_BUS_CLK_VENC_AXI         82

+#define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV    83

+#define JH7110_AXI_CFG0_DEC_CLK_MAIN        84

+#define JH7110_AXI_CFG0_DEC_CLK_HIFI4       85

+#define JH7110_AXIMEM2_128B_CLK_AXI         86

+#define JH7110_QSPI_CLK_AHB                 87

+#define JH7110_QSPI_CLK_APB                 88

+#define JH7110_QSPI_REF_SRC                 89

+#define JH7110_QSPI_CLK_REF                 90

+#define JH7110_SDIO0_CLK_AHB                91

+#define JH7110_SDIO1_CLK_AHB                92

+#define JH7110_SDIO0_CLK_SDCARD             93

+#define JH7110_SDIO1_CLK_SDCARD             94

+#define JH7110_USB_125M                     95

+#define JH7110_NOC_BUS_CLK_STG_AXI          96

+#define JH7110_GMAC5_CLK_AHB                97

+#define JH7110_GMAC5_CLK_AXI                98

+#define JH7110_GMAC_SRC                     99

+#define JH7110_GMAC1_GTXCLK                 100

+#define JH7110_GMAC1_RMII_RTX               101

+#define JH7110_GMAC5_CLK_PTP                102

+#define JH7110_GMAC5_CLK_RX                 103

+#define JH7110_GMAC5_CLK_RX_INV             104

+#define JH7110_GMAC5_CLK_TX                 105

+#define JH7110_GMAC5_CLK_TX_INV             106

+#define JH7110_GMAC1_GTXC                   107

+#define JH7110_GMAC0_GTXCLK                 108

+#define JH7110_GMAC0_PTP                    109

+#define JH7110_GMAC_PHY                     110

+#define JH7110_GMAC0_GTXC                   111

+#define JH7110_SYS_IOMUX_PCLK               112

+#define JH7110_MAILBOX_CLK_APB              113

+#define JH7110_INT_CTRL_CLK_APB             114

+#define JH7110_CAN0_CTRL_CLK_APB            115

+#define JH7110_CAN0_CTRL_CLK_TIMER          116

+#define JH7110_CAN0_CTRL_CLK_CAN            117

+#define JH7110_CAN1_CTRL_CLK_APB            118

+#define JH7110_CAN1_CTRL_CLK_TIMER          119

+#define JH7110_CAN1_CTRL_CLK_CAN            120

+#define JH7110_PWM_CLK_APB                  121

+#define JH7110_DSKIT_WDT_CLK_APB            122

+#define JH7110_DSKIT_WDT_CLK_WDT            123

+#define JH7110_TIMER_CLK_APB                124

+#define JH7110_TIMER_CLK_TIMER0             125

+#define JH7110_TIMER_CLK_TIMER1             126

+#define JH7110_TIMER_CLK_TIMER2             127

+#define JH7110_TIMER_CLK_TIMER3             128

+#define JH7110_TEMP_SENSOR_CLK_APB          129

+#define JH7110_TEMP_SENSOR_CLK_TEMP         130

+#define JH7110_SPI0_CLK_APB                 131

+#define JH7110_SPI1_CLK_APB                 132

+#define JH7110_SPI2_CLK_APB                 133

+#define JH7110_SPI3_CLK_APB                 134

+#define JH7110_SPI4_CLK_APB                 135

+#define JH7110_SPI5_CLK_APB                 136

+#define JH7110_SPI6_CLK_APB                 137

+#define JH7110_I2C0_CLK_APB                 138

+#define JH7110_I2C1_CLK_APB                 139

+#define JH7110_I2C2_CLK_APB                 140

+#define JH7110_I2C3_CLK_APB                 141

+#define JH7110_I2C4_CLK_APB                 142

+#define JH7110_I2C5_CLK_APB                 143

+#define JH7110_I2C6_CLK_APB                 144

+#define JH7110_UART0_CLK_APB                145

+#define JH7110_UART0_CLK_CORE               146

+#define JH7110_UART1_CLK_APB                147

+#define JH7110_UART1_CLK_CORE               148

+#define JH7110_UART2_CLK_APB                149

+#define JH7110_UART2_CLK_CORE               150

+#define JH7110_UART3_CLK_APB                151

+#define JH7110_UART3_CLK_CORE               152

+#define JH7110_UART4_CLK_APB                153

+#define JH7110_UART4_CLK_CORE               154

+#define JH7110_UART5_CLK_APB                155

+#define JH7110_UART5_CLK_CORE               156

+#define JH7110_PWMDAC_CLK_APB               157

+#define JH7110_PWMDAC_CLK_CORE              158

+#define JH7110_SPDIF_CLK_APB                159

+#define JH7110_SPDIF_CLK_CORE               160

+#define JH7110_I2STX0_4CHCLK_APB            161

+#define JH7110_I2STX_4CH0_BCLK_MST          162

+#define JH7110_I2STX_4CH0_BCLK_MST_INV      163

+#define JH7110_I2STX_4CH0_LRCK_MST          164

+#define JH7110_I2STX0_4CHBCLK               165

+#define JH7110_I2STX0_4CHBCLK_N             166

+#define JH7110_I2STX0_4CHLRCK               167

+#define JH7110_I2STX1_4CHCLK_APB            168

+#define JH7110_I2STX_4CH1_BCLK_MST          169

+#define JH7110_I2STX_4CH1_BCLK_MST_INV      170

+#define JH7110_I2STX_4CH1_LRCK_MST          171

+#define JH7110_I2STX1_4CHBCLK               172

+#define JH7110_I2STX1_4CHBCLK_N             173

+#define JH7110_I2STX1_4CHLRCK               174

+#define JH7110_I2SRX0_3CH_CLK_APB           175

+#define JH7110_I2SRX_3CH_BCLK_MST           176

+#define JH7110_I2SRX_3CH_BCLK_MST_INV       177

+#define JH7110_I2SRX_3CH_LRCK_MST           178

+#define JH7110_I2SRX0_3CH_BCLK              179

+#define JH7110_I2SRX0_3CH_BCLK_N            180

+#define JH7110_I2SRX0_3CH_LRCK              181

+#define JH7110_PDM_CLK_DMIC                 182

+#define JH7110_PDM_CLK_APB                  183

+#define JH7110_TDM_CLK_AHB                  184

+#define JH7110_TDM_CLK_APB                  185

+#define JH7110_TDM_INTERNAL                 186

+#define JH7110_TDM_CLK_TDM                  187

+#define JH7110_TDM_CLK_TDM_N                188

+#define JH7110_JTAG_CERTIFICATION_TRNG_CLK  189

+

+#define JH7110_CLK_SYS_REG_END  190

+

+/* stg regisger */

+#define JH7110_HIFI4_CLK_CORE          190

+#define JH7110_USB0_CLK_USB_APB        191

+#define JH7110_USB0_CLK_UTMI_APB       192

+#define JH7110_USB0_CLK_AXI            193

+#define JH7110_USB0_CLK_LPM            194

+#define JH7110_USB0_CLK_STB            195

+#define JH7110_USB0_CLK_APP_125        196

+#define JH7110_USB0_REFCLK             197

+#define JH7110_PCIE0_CLK_AXI_MST0      198

+#define JH7110_PCIE0_CLK_APB           199

+#define JH7110_PCIE0_CLK_TL            200

+#define JH7110_PCIE1_CLK_AXI_MST0      201

+#define JH7110_PCIE1_CLK_APB           202

+#define JH7110_PCIE1_CLK_TL            203

+#define JH7110_PCIE01_SLV_DEC_MAINCLK  204

+#define JH7110_SEC_HCLK                205

+#define JH7110_SEC_MISCAHB_CLK         206

+#define JH7110_STG_MTRX_GRP0_CLK_MAIN  207

+#define JH7110_STG_MTRX_GRP0_CLK_BUS   208

+#define JH7110_STG_MTRX_GRP0_CLK_STG   209

+#define JH7110_STG_MTRX_GRP1_CLK_MAIN  210

+#define JH7110_STG_MTRX_GRP1_CLK_BUS   211

+#define JH7110_STG_MTRX_GRP1_CLK_STG   212

+#define JH7110_STG_MTRX_GRP1_CLK_HIFI  213

+#define JH7110_E2_RTC_CLK              214

+#define JH7110_E2_CLK_CORE             215

+#define JH7110_E2_CLK_DBG              216

+#define JH7110_DMA1P_CLK_AXI           217

+#define JH7110_DMA1P_CLK_AHB           218

+

+#define JH7110_CLK_STG_REG_END  219

+

+/* aon regisger */

+#define JH7110_OSC_DIV4             219

+#define JH7110_AON_APB_FUNC         220

+#define JH7110_U0_GMAC5_CLK_AHB     221

+#define JH7110_U0_GMAC5_CLK_AXI     222

+#define JH7110_GMAC0_RMII_RTX       223

+#define JH7110_U0_GMAC5_CLK_TX      224

+#define JH7110_U0_GMAC5_CLK_TX_INV  225

+#define JH7110_U0_GMAC5_CLK_RX      226

+#define JH7110_U0_GMAC5_CLK_RX_INV  227

+#define JH7110_OTPC_CLK_APB         228

+#define JH7110_RTC_HMS_CLK_APB      229

+#define JH7110_RTC_INTERNAL         230

+#define JH7110_RTC_HMS_CLK_OSC32K   231

+#define JH7110_RTC_HMS_CLK_CAL      232

+

+#define JH7110_CLK_REG_END  233

+

+/* sys other */

+#define JH7110_PLL0_OUT                      233

+#define JH7110_PLL1_OUT                      234

+#define JH7110_PLL2_OUT                      235

+#define JH7110_AON_APB                       236

+#define JH7110_RESET1_CTRL_CLK_SRC           237

+#define JH7110_DDR_ROOT                      238

+#define JH7110_VDEC_ROOT                     239

+#define JH7110_VENC_ROOT                     240

+#define JH7110_VOUT_ROOT                     241

+#define JH7110_GMACUSB_ROOT                  242

+#define JH7110_PCLK2_MUX_FUNC_PCLK           243

+#define JH7110_PCLK2_MUX_BIST_PCLK           244

+#define JH7110_APB_BUS                       245

+#define JH7110_APB12                         246

+#define JH7110_AXI_CFG1                      247

+#define JH7110_PLL_WRAP_CRG_GCLK0            248

+#define JH7110_PLL_WRAP_CRG_GCLK1            249

+#define JH7110_PLL_WRAP_CRG_GCLK2            250

+#define JH7110_JTAG2APB_PCLK                 251

+#define JH7110_U7_BUS_CLK                    252

+#define JH7110_U7_IRQ_SYNC_BUS_CLK           253

+#define JH7110_NOC_BUS_CLK2_CPU_AXI          254

+#define JH7110_NOC_BUS_CLK_APB_BUS           255

+#define JH7110_NOC_BUS_CLK2_APB_BUS          256

+#define JH7110_NOC_BUS_CLK2_AXICFG0_AXI      257

+#define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS     258

+#define JH7110_DDR_CLK_OSC                   259

+#define JH7110_DDR_CLK_APB                   260

+#define JH7110_NOC_BUS_CLK_DDRC              261

+#define JH7110_NOC_BUS_CLK2_DDRC             262

+#define JH7110_SYS_AHB_DEC_CLK_AHB           263

+#define JH7110_STG_AHB_DEC_CLK_AHB           264

+#define JH7110_NOC_BUS_CLK2_GPU_AXI          265

+#define JH7110_ISP_TOP_CLK_DVP               266

+#define JH7110_NOC_BUS_CLK2_ISP_AXI          267

+#define JH7110_ISP_TOP_CLK_BIST_APB          268

+#define JH7110_NOC_BUS_CLK2_DISP_AXI         269

+#define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK     270

+#define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS    271

+#define JH7110_VOUT_TOP_CLK_HDMIPHY_REF      272

+#define JH7110_VOUT_TOP_BIST_PCLK            273

+#define JH7110_AXIMEM0_128B_CLK_AXI          274

+#define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI     275

+#define JH7110_NOC_BUS_CLK2_VDEC_AXI         276

+#define JH7110_AXIMEM1_128B_CLK_AXI          277

+#define JH7110_VENC_INTSRAM_CLK_VENC_AXI     278

+#define JH7110_NOC_BUS_CLK2_VENC_AXI         279

+#define JH7110_SRAM_CLK_ROM                  280

+#define JH7110_NOC_BUS_CLK2_STG_AXI          281

+#define JH7110_GMAC5_CLK_RMII                282

+#define JH7110_AON_AHB                       283

+#define JH7110_SYS_CRG_PCLK                  284

+#define JH7110_SYS_SYSCON_PCLK               285

+#define JH7110_SPI0_CLK_CORE                 286

+#define JH7110_SPI1_CLK_CORE                 287

+#define JH7110_SPI2_CLK_CORE                 288

+#define JH7110_SPI3_CLK_CORE                 289

+#define JH7110_SPI4_CLK_CORE                 290

+#define JH7110_SPI5_CLK_CORE                 291

+#define JH7110_SPI6_CLK_CORE                 292

+#define JH7110_I2C0_CLK_CORE                 293

+#define JH7110_I2C1_CLK_CORE                 294

+#define JH7110_I2C2_CLK_CORE                 295

+#define JH7110_I2C3_CLK_CORE                 296

+#define JH7110_I2C4_CLK_CORE                 297

+#define JH7110_I2C5_CLK_CORE                 298

+#define JH7110_I2C6_CLK_CORE                 299

+#define JH7110_I2STX_BCLK_MST                300

+#define JH7110_I2STX_LRCK_MST                301

+#define JH7110_I2SRX_BCLK_MST                302

+#define JH7110_I2SRX_LRCK_MST                303

+#define JH7110_PDM_CLK_DMIC0_BCLK_SLV        304

+#define JH7110_PDM_CLK_DMIC0_LRCK_SLV        305

+#define JH7110_PDM_CLK_DMIC1_BCLK_SLV        306

+#define JH7110_PDM_CLK_DMIC1_LRCK_SLV        307

+#define JH7110_TDM_CLK_MST                   308

+#define JH7110_AHB2APB_CLK_AHB               309

+#define JH7110_P2P_ASYNC_CLK_APBS            310

+#define JH7110_P2P_ASYNC_CLK_APBM            311

+#define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK     312

+#define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK  313

+#define JH7110_E2_DEBUG_SYSTEMJTAG_TCK       314

+#define JH7110_JTAG_CERTIFICATION_TCK        315

+#define JH7110_SEC_SKP_CLK                   316

+#define JH7110_U2_PCLK_MUX_PCLK              317

+

+#define JH7110_CLK_SYS_END  318

+

+/* stg other */

+#define JH7110_PCIE0_CLK_AXI_SLV0    318

+#define JH7110_PCIE0_CLK_AXI_SLV     319

+#define JH7110_PCIE0_CLK_OSC         320

+#define JH7110_PCIE1_CLK_AXI_SLV0    321

+#define JH7110_PCIE1_CLK_AXI_SLV     322

+#define JH7110_PCIE1_CLK_OSC         323

+#define JH7110_E2_IRQ_SYNC_CLK_CORE  324

+#define JH7110_STG_CRG_PCLK          325

+#define JH7110_STG_SYSCON_PCLK       326

+

+#define JH7110_CLK_STG_END  327

+

+/* aon other */

+#define JH7110_U0_GMAC5_CLK_PTP      327

+#define JH7110_U0_GMAC5_CLK_RMII     328

+#define JH7110_AON_SYSCON_PCLK       329

+#define JH7110_AON_IOMUX_PCLK        330

+#define JH7110_AON_CRG_PCLK          331

+#define JH7110_PMU_CLK_APB           332

+#define JH7110_PMU_CLK_WKUP          333

+#define JH7110_RTC_HMS_CLK_OSC32K_G  334

+#define JH7110_32K_OUT               335

+#define JH7110_RESET0_CTRL_CLK_SRC   336

+/* aon other and source */

+#define JH7110_PCLK_MUX_FUNC_PCLK  337

+#define JH7110_PCLK_MUX_BIST_PCLK  338

+

+#define JH7110_CLK_END  339

+

+/* sys external clocks */

+#define JH7110_OSC               (JH7110_CLK_END + 0)

+#define JH7110_GMAC1_RMII_REFIN  (JH7110_CLK_END + 1)

+#define JH7110_GMAC1_RGMII_RXIN  (JH7110_CLK_END + 2)

+#define JH7110_I2STX_BCLK_EXT    (JH7110_CLK_END + 3)

+#define JH7110_I2STX_LRCK_EXT    (JH7110_CLK_END + 4)

+#define JH7110_I2SRX_BCLK_EXT    (JH7110_CLK_END + 5)

+#define JH7110_I2SRX_LRCK_EXT    (JH7110_CLK_END + 6)

+#define JH7110_TDM_EXT           (JH7110_CLK_END + 7)

+#define JH7110_MCLK_EXT          (JH7110_CLK_END + 8)

+#define JH7110_JTAG_TCK_INNER    (JH7110_CLK_END + 9)

+#define JH7110_BIST_APB          (JH7110_CLK_END + 10)

+

+/* stg external clocks */

+#define JH7110_STG_APB  (JH7110_CLK_END + 11)

+

+/* aon external clocks */

+#define JH7110_GMAC0_RMII_REFIN  (JH7110_CLK_END + 12)

+#define JH7110_GMAC0_RGMII_RXIN  (JH7110_CLK_END + 13)

+#define JH7110_CLK_RTC           (JH7110_CLK_END + 14)

+

+#endif /* __DT_BINDINGS_JH7110_CLK_GEN_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h
new file mode 100644
index 000000000000..756c51529a3a
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkIsp.h
@@ -0,0 +1,57 @@
+/** @file

+  This header provide all JH7110 clock isp device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_CLK_ISP_H__

+#define __DT_BINDINGS_JH7110_CLK_ISP_H__

+

+/* register */

+#define JH7110_DOM4_APB_FUNC               0

+#define JH7110_MIPI_RX0_PXL                1

+#define JH7110_DVP_INV                     2

+#define JH7110_U0_M31DPHY_CFGCLK_IN        3

+#define JH7110_U0_M31DPHY_REFCLK_IN        4

+#define JH7110_U0_M31DPHY_TXCLKESC_LAN0    5

+#define JH7110_U0_VIN_PCLK                 6

+#define JH7110_U0_VIN_SYS_CLK              7

+#define JH7110_U0_VIN_PIXEL_CLK_IF0        8

+#define JH7110_U0_VIN_PIXEL_CLK_IF1        9

+#define JH7110_U0_VIN_PIXEL_CLK_IF2        10

+#define JH7110_U0_VIN_PIXEL_CLK_IF3        11

+#define JH7110_U0_VIN_CLK_P_AXIWR          12

+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C  13

+

+#define JH7110_CLK_ISP_REG_END  14

+

+/* other */

+#define JH7110_U3_PCLK_MUX_FUNC_PCLK                14

+#define JH7110_U3_PCLK_MUX_BIST_PCLK                15

+#define JH7110_DOM4_APB                             16

+#define JH7110_U0_VIN_PCLK_FREE                     17

+#define JH7110_U0_VIN_CLK_P_AXIRD                   18

+#define JH7110_U0_VIN_ACLK                          19

+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN  20

+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2      21

+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP         22

+#define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P           23

+#define JH7110_U0_CRG_PCLK                          24

+#define JH7110_U0_SYSCON_PCLK                       25

+#define JH7110_U0_M31DPHY_APBCFG_PCLK               26

+#define JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB       27

+#define JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK    28

+#define JH7110_U3_PCLK_MUX_PCLK                     29

+

+#define JH7110_CLK_ISP_END  30

+

+/* external clocks */

+#define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN  (JH7110_CLK_ISP_END + 0)

+#define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN     (JH7110_CLK_ISP_END + 1)

+#define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN    (JH7110_CLK_ISP_END + 2)

+#define JH7110_ISP_TOP_CLK_DVP_CLKGEN         (JH7110_CLK_ISP_END + 3)

+

+#endif /* __DT_BINDINGS_JH7110_CLK_ISP_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h
new file mode 100644
index 000000000000..9775d9eadbdd
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110ClkVout.h
@@ -0,0 +1,68 @@
+/** @file

+  This header provide all JH7110 clock vout device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_CLK_VOUT_H__

+#define __DT_BINDINGS_JH7110_CLK_VOUT_H__

+

+/* register */

+#define JH7110_APB                       0

+#define JH7110_DC8200_PIX0               1

+#define JH7110_DSI_SYS                   2

+#define JH7110_TX_ESC                    3

+#define JH7110_U0_DC8200_CLK_AXI         4

+#define JH7110_U0_DC8200_CLK_CORE        5

+#define JH7110_U0_DC8200_CLK_AHB         6

+#define JH7110_U0_DC8200_CLK_PIX0        7

+#define JH7110_U0_DC8200_CLK_PIX1        8

+#define JH7110_DOM_VOUT_TOP_LCD_CLK      9

+#define JH7110_U0_CDNS_DSITX_CLK_APB     10

+#define JH7110_U0_CDNS_DSITX_CLK_SYS     11

+#define JH7110_U0_CDNS_DSITX_CLK_DPI     12

+#define JH7110_U0_CDNS_DSITX_CLK_TXESC   13

+#define JH7110_U0_MIPITX_DPHY_CLK_TXESC  14

+#define JH7110_U0_HDMI_TX_CLK_MCLK       15

+#define JH7110_U0_HDMI_TX_CLK_BCLK       16

+#define JH7110_U0_HDMI_TX_CLK_SYS        17

+

+#define JH7110_CLK_VOUT_REG_END  18

+

+/* other */

+#define JH7110_DISP_ROOT     18

+#define JH7110_DISP_AXI      19

+#define JH7110_DISP_AHB      20

+#define JH7110_HDMI_PHY_REF  21

+#define JH7110_HDMITX0_MCLK  22

+#define JH7110_HDMITX0_SCK   23

+

+#define JH7110_MIPI_DPHY_REF                          24

+#define JH7110_U0_PCLK_MUX_BIST_PCLK                  25

+#define JH7110_DISP_APB                               26

+#define JH7110_U0_PCLK_MUX_FUNC_PCLK                  27

+#define JH7110_U0_DOM_VOUT_CRG_PCLK                   28

+#define JH7110_U0_DOM_VOUT_SYSCON_PCLK                29

+#define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB  30

+#define JH7110_U0_AHB2APB_CLK_AHB                     31

+#define JH7110_U0_P2P_ASYNC_CLK_APBS                  32

+#define JH7110_U0_CDNS_DSITX_CLK_RXESC                33

+#define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS             34

+#define JH7110_U0_MIPITX_DPHY_CLK_SYS                 35

+#define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF            36

+#define JH7110_U0_MIPITX_APBIF_PCLK                   37

+#define JH7110_HDMI_TX_CLK_REF                        38

+#define JH7110_U0_DC8200_CLK_PIX0_OUT                 39

+#define JH7110_U0_DC8200_CLK_PIX1_OUT                 40

+

+#define JH7110_CLK_VOUT_END  41

+

+/* external clocks */

+#define JH7110_HDMITX0_PIXELCLK      (JH7110_CLK_VOUT_END + 0)

+#define JH7110_MIPITX_DPHY_RXESC     (JH7110_CLK_VOUT_END + 1)

+#define JH7110_MIPITX_DPHY_TXBYTEHS  (JH7110_CLK_VOUT_END + 2)

+

+#endif /* __DT_BINDINGS_JH7110_CLK_VOUT_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h
new file mode 100755
index 000000000000..0df2e6991548
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110PinCtrl.h
@@ -0,0 +1,1573 @@
+/** @file

+  This header provide all JH7110 pin control device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_PIN_CTRL_H__

+#define __DT_BINDINGS_JH7110_PIN_CTRL_H__

+

+/************************aon_iomux***************************/

+// aon_iomux pin

+#define PAD_TESTEN      0

+#define PAD_RGPIO0      1

+#define PAD_RGPIO1      2

+#define PAD_RGPIO2      3

+#define PAD_RGPIO3      4

+#define PAD_RSTN        5

+#define PAD_GMAC0_MDC   6

+#define PAD_GMAC0_MDIO  7

+#define PAD_GMAC0_RXD0  8

+#define PAD_GMAC0_RXD1  9

+#define PAD_GMAC0_RXD2  10

+#define PAD_GMAC0_RXD3  11

+#define PAD_GMAC0_RXDV  12

+#define PAD_GMAC0_RXC   13

+#define PAD_GMAC0_TXD0  14

+#define PAD_GMAC0_TXD1  15

+#define PAD_GMAC0_TXD2  16

+#define PAD_GMAC0_TXD3  17

+#define PAD_GMAC0_TXEN  18

+#define PAD_GMAC0_TXC   19

+

+// aon_iomux dout

+#define GPO_AON_IOMUX_U0_AON_CRG_CLK_32K_OUT  2

+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_4    3

+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_5    4

+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_6    5

+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_7    6

+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK0    7

+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK1    8

+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK2    9

+// aon_iomux doen

+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_4  2

+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_5  3

+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_6  4

+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_7  5

+// aon_iomux gin

+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0  0

+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1  1

+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2  2

+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3  3

+

+// ===============================GPIO_OUT_SELECT=======================================

+// gpio_out config:

+// every define below is a couple of signal and signal idx

+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_out

+// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOUT_CFG([signal])

+// e.g. SET_AON_IOMUX_GPO0_DOUT_CFG(__LOW)

+// =====================================================================================

+#define __LOW                   0

+#define __HIGH                  1

+#define U0_AON_CRG_CLK_32K_OUT  2

+#define U0_PWM_8CH_PTC_PWM_4    3

+#define U0_PWM_8CH_PTC_PWM_5    4

+#define U0_PWM_8CH_PTC_PWM_6    5

+#define U0_PWM_8CH_PTC_PWM_7    6

+#define U0_SYS_CRG_CLK_GCLK0    7

+#define U0_SYS_CRG_CLK_GCLK1    8

+#define U0_SYS_CRG_CLK_GCLK2    9

+

+// ===============================GPIO_OEN_SELECT=======================================

+// gpio_oen config:

+// every define below is a couple of signal and signal idx

+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_oen

+// e.g. SET_AON_IOMUX_GPO[gpio_num]_DOEN_CFG([signal])

+// e.g. SET_AON_IOMUX_GPO0_DOEN_CFG(__LOW)

+// =====================================================================================

+#define __LOW                  0

+#define __HIGH                 1

+#define U0_PWM_8CH_PTC_OE_N_4  2

+#define U0_PWM_8CH_PTC_OE_N_5  3

+#define U0_PWM_8CH_PTC_OE_N_6  4

+#define U0_PWM_8CH_PTC_OE_N_7  5

+

+// aon_iomux gmac0 syscon

+#define AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR   (0x58U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR   (0x5cU)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR   (0x60U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR  (0x64U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR  (0x68U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR  (0x6cU)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR  (0x70U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR  (0x74U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR  (0x78U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR  (0x7cU)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR  (0x80U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR  (0x84U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR  (0x88U)

+#define AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR  (0x8cU)

+

+#define PADCFG_PAD_GMAC0_MDC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR

+#define PADCFG_PAD_GMAC0_MDIO_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR

+#define PADCFG_PAD_GMAC0_RXD0_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR

+#define PADCFG_PAD_GMAC0_RXD1_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR

+#define PADCFG_PAD_GMAC0_RXD2_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR

+#define PADCFG_PAD_GMAC0_RXD3_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR

+#define PADCFG_PAD_GMAC0_RXDV_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR

+#define PADCFG_PAD_GMAC0_RXC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR

+#define PADCFG_PAD_GMAC0_TXD0_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR

+#define PADCFG_PAD_GMAC0_TXD1_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR

+#define PADCFG_PAD_GMAC0_TXD2_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR

+#define PADCFG_PAD_GMAC0_TXD3_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR

+#define PADCFG_PAD_GMAC0_TXEN_SYSCON  AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR

+#define PADCFG_PAD_GMAC0_TXC_SYSCON   AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR

+

+// aon_iomux func sel

+#define AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR  (0x90U)

+#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT        0x0U

+#define PAD_GMAC0_RXC_FUNC_SEL_MASK         0x3U

+

+#define PAD_GMAC0_RXC_FUNC_SEL             \

+        AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR \

+        PAD_GMAC0_RXC_FUNC_SEL_SHIFT       \

+        PAD_GMAC0_RXC_FUNC_SEL_MASK

+/************************aon_iomux***************************/

+

+/************************sys_iomux***************************/

+// sys_iomux pin

+#define PAD_GPIO0       0

+#define PAD_GPIO1       1

+#define PAD_GPIO2       2

+#define PAD_GPIO3       3

+#define PAD_GPIO4       4

+#define PAD_GPIO5       5

+#define PAD_GPIO6       6

+#define PAD_GPIO7       7

+#define PAD_GPIO8       8

+#define PAD_GPIO9       9

+#define PAD_GPIO10      10

+#define PAD_GPIO11      11

+#define PAD_GPIO12      12

+#define PAD_GPIO13      13

+#define PAD_GPIO14      14

+#define PAD_GPIO15      15

+#define PAD_GPIO16      16

+#define PAD_GPIO17      17

+#define PAD_GPIO18      18

+#define PAD_GPIO19      19

+#define PAD_GPIO20      20

+#define PAD_GPIO21      21

+#define PAD_GPIO22      22

+#define PAD_GPIO23      23

+#define PAD_GPIO24      24

+#define PAD_GPIO25      25

+#define PAD_GPIO26      26

+#define PAD_GPIO27      27

+#define PAD_GPIO28      28

+#define PAD_GPIO29      29

+#define PAD_GPIO30      30

+#define PAD_GPIO31      31

+#define PAD_GPIO32      32

+#define PAD_GPIO33      33

+#define PAD_GPIO34      34

+#define PAD_GPIO35      35

+#define PAD_GPIO36      36

+#define PAD_GPIO37      37

+#define PAD_GPIO38      38

+#define PAD_GPIO39      39

+#define PAD_GPIO40      40

+#define PAD_GPIO41      41

+#define PAD_GPIO42      42

+#define PAD_GPIO43      43

+#define PAD_GPIO44      44

+#define PAD_GPIO45      45

+#define PAD_GPIO46      46

+#define PAD_GPIO47      47

+#define PAD_GPIO48      48

+#define PAD_GPIO49      49

+#define PAD_GPIO50      50

+#define PAD_GPIO51      51

+#define PAD_GPIO52      52

+#define PAD_GPIO53      53

+#define PAD_GPIO54      54

+#define PAD_GPIO55      55

+#define PAD_GPIO56      56

+#define PAD_GPIO57      57

+#define PAD_GPIO58      58

+#define PAD_GPIO59      59

+#define PAD_GPIO60      60

+#define PAD_GPIO61      61

+#define PAD_GPIO62      62

+#define PAD_GPIO63      63

+#define PAD_SD0_CLK     64

+#define PAD_SD0_CMD     65

+#define PAD_SD0_DATA0   66

+#define PAD_SD0_DATA1   67

+#define PAD_SD0_DATA2   68

+#define PAD_SD0_DATA3   69

+#define PAD_SD0_DATA4   70

+#define PAD_SD0_DATA5   71

+#define PAD_SD0_DATA6   72

+#define PAD_SD0_DATA7   73

+#define PAD_SD0_STRB    74

+#define PAD_GMAC1_MDC   75

+#define PAD_GMAC1_MDIO  76

+#define PAD_GMAC1_RXD0  77

+#define PAD_GMAC1_RXD1  78

+#define PAD_GMAC1_RXD2  79

+#define PAD_GMAC1_RXD3  80

+#define PAD_GMAC1_RXDV  81

+#define PAD_GMAC1_RXC   82

+#define PAD_GMAC1_TXD0  83

+#define PAD_GMAC1_TXD1  84

+#define PAD_GMAC1_TXD2  85

+#define PAD_GMAC1_TXD3  86

+#define PAD_GMAC1_TXEN  87

+#define PAD_GMAC1_TXC   88

+#define PAD_QSPI_SCLK   89

+#define PAD_QSPI_CSn0   90

+#define PAD_QSPI_DATA0  91

+#define PAD_QSPI_DATA1  92

+#define PAD_QSPI_DATA2  93

+#define PAD_QSPI_DATA3  94

+

+// oen and out idx is for chosen, in idx is for reg offset

+#define GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT                    2

+#define GPO_SYS_IOMUX_U0_CAN_CTRL_STBY                            3

+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT                    4

+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT                5

+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TXD                             6

+#define GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO                    7

+#define GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1                           8

+#define GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO                        9

+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT  10

+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT  11

+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT  12

+#define GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES                        13

+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A                      14

+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A                     15

+#define GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER                   16

+#define GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN                    17

+#define GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N              18

+#define GPO_SYS_IOMUX_U0_DW_SDIO_RST_N                            19

+#define GPO_SYS_IOMUX_U0_DW_UART_SOUT                             20

+#define GPO_SYS_IOMUX_U0_HIFI4_JTDO                               21

+#define GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO                   22

+#define GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK                       23

+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0                        24

+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1                        25

+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2                        26

+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3                        27

+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT                28

+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT               29

+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT                        30

+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT                        31

+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD                           32

+#define GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY                     33

+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST                   34

+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST                   35

+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST                   36

+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST                   37

+#define GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT                         38

+#define GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST                      39

+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT                    40

+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD                        41

+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0       42

+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1       43

+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2       44

+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3       45

+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF          46

+#define GPO_SYS_IOMUX_U1_CAN_CTRL_STBY                            47

+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT                    48

+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT                49

+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TXD                             50

+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A                      51

+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A                     52

+#define GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER                   53

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN                    54

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT                         55

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N              56

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT                         57

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0                      58

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1                      59

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2                      60

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3                      61

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4                      62

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5                      63

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6                      64

+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7                      65

+#define GPO_SYS_IOMUX_U1_DW_SDIO_RST_N                            66

+#define GPO_SYS_IOMUX_U1_DW_UART_RTS_N                            67

+#define GPO_SYS_IOMUX_U1_DW_UART_SOUT                             68

+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0                           69

+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1                           70

+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2                           71

+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3                           72

+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT                        73

+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT                        74

+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD                           75

+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A                      76

+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A                     77

+#define GPO_SYS_IOMUX_U2_DW_UART_RTS_N                            78

+#define GPO_SYS_IOMUX_U2_DW_UART_SOUT                             79

+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT                        80

+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT                        81

+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD                           82

+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A                      83

+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A                     84

+#define GPO_SYS_IOMUX_U3_DW_UART_SOUT                             85

+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT                        86

+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT                        87

+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD                           88

+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A                      89

+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A                     90

+#define GPO_SYS_IOMUX_U4_DW_UART_RTS_N                            91

+#define GPO_SYS_IOMUX_U4_DW_UART_SOUT                             92

+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT                        93

+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT                        94

+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD                           95

+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A                      96

+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A                     97

+#define GPO_SYS_IOMUX_U5_DW_UART_RTS_N                            98

+#define GPO_SYS_IOMUX_U5_DW_UART_SOUT                             99

+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT                        100

+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT                        101

+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD                           102

+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A                      103

+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A                     104

+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT                        105

+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT                        106

+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD                           107

+

+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN  2

+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN  3

+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN  4

+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE                         5

+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE                        6

+#define GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN                             7

+#define GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE                8

+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0                       9

+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1                       10

+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2                       11

+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3                       12

+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE                        13

+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE                           14

+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE                    15

+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE                     16

+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE                         17

+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE                        18

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN                      19

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0                   20

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1                   21

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2                   22

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3                   23

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4                   24

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5                   25

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6                   26

+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7                   27

+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE                        28

+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE                           29

+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE                         30

+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE                        31

+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE                        32

+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE                           33

+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE                         34

+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE                        35

+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE                        36

+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE                           37

+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE                         38

+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE                        39

+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE                        40

+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE                           41

+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE                         42

+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE                        43

+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE                        44

+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE                           45

+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE                         46

+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE                        47

+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE                        48

+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE                           49

+

+#define GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN                    0

+#define GPI_SYS_IOMUX_U0_CAN_CTRL_RXD                            1

+#define GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO                2

+#define GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI                       3

+#define GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN            4

+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN  5

+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN  6

+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN  7

+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD         8

+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A                      9

+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A                     10

+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N                   11

+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N                      12

+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT                  13

+#define GPI_SYS_IOMUX_U0_DW_UART_SIN                             14

+#define GPI_SYS_IOMUX_U0_HIFI4_JTCK                              15

+#define GPI_SYS_IOMUX_U0_HIFI4_JTDI                              16

+#define GPI_SYS_IOMUX_U0_HIFI4_JTMS                              17

+#define GPI_SYS_IOMUX_U0_HIFI4_JTRSTN                            18

+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI                  19

+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS                  20

+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN                      21

+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN                      22

+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0     23

+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1     24

+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2     25

+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN                        26

+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN                        27

+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD                          28

+#define GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK                    29

+#define GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK                        30

+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV                  31

+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV                  32

+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV                  33

+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV                  34

+#define GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV                     35

+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD                       36

+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN                    37

+#define GPI_SYS_IOMUX_U1_CAN_CTRL_RXD                            38

+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A                      39

+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A                     40

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N                   41

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N                      42

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT                  43

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN                         44

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0                      45

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1                      46

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2                      47

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3                      48

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4                      49

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5                      50

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6                      51

+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7                      52

+#define GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE                     53

+#define GPI_SYS_IOMUX_U1_DW_UART_CTS_N                           54

+#define GPI_SYS_IOMUX_U1_DW_UART_SIN                             55

+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN                        56

+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN                        57

+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD                          58

+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A                      59

+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A                     60

+#define GPI_SYS_IOMUX_U2_DW_UART_CTS_N                           61

+#define GPI_SYS_IOMUX_U2_DW_UART_SIN                             62

+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN                        63

+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN                        64

+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD                          65

+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A                      66

+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A                     67

+#define GPI_SYS_IOMUX_U3_DW_UART_SIN                             68

+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN                        69

+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN                        70

+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD                          71

+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A                      72

+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A                     73

+#define GPI_SYS_IOMUX_U4_DW_UART_CTS_N                           74

+#define GPI_SYS_IOMUX_U4_DW_UART_SIN                             75

+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN                        76

+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN                        77

+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD                          78

+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A                      79

+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A                     80

+#define GPI_SYS_IOMUX_U5_DW_UART_CTS_N                           81

+#define GPI_SYS_IOMUX_U5_DW_UART_SIN                             82

+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN                        83

+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN                        84

+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD                          85

+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A                      86

+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A                     87

+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN                        88

+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN                        89

+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD                          90

+

+// gpo(n)_dout signal pool

+#define GPO_LOW   0

+#define GPO_HIGH  1

+#define GPO_CAN0_CTRL_STBY              \

+        GPO_SYS_IOMUX_U0_CAN_CTRL_STBY

+#define GPO_CAN0_CTRL_TST_NEXT_BIT      \

+        GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT

+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT  \

+        GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT

+#define GPO_CAN0_CTRL_TXD               \

+        GPO_SYS_IOMUX_U0_CAN_CTRL_TXD

+#define GPO_CAN1_CTRL_STBY              \

+        GPO_SYS_IOMUX_U1_CAN_CTRL_STBY

+#define GPO_CAN1_CTRL_TST_NEXT_BIT      \

+        GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT

+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT  \

+        GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT

+#define GPO_CAN1_CTRL_TXD               \

+        GPO_SYS_IOMUX_U1_CAN_CTRL_TXD

+#define GPO_CRG0_MCLK_OUT               \

+        GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT

+#define GPO_GMAC0_CLK_PHY               \

+        GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY

+#define GPO_HDMI0_CEC_SDA_OUT           \

+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT

+#define GPO_HDMI0_DDC_SCL_OUT           \

+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT

+#define GPO_HDMI0_DDC_SDA_OUT           \

+        GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT

+#define GPO_I2C0_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C0_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C1_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C1_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C2_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C2_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C3_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C3_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C4_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C4_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C5_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C5_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2C6_IC_CLK_OUT_A           \

+        GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A

+#define GPO_I2C6_IC_DATA_OUT_A          \

+        GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A

+#define GPO_I2SRX0_BCLK_MST             \

+        GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST

+#define GPO_I2SRX0_LRCK_MST             \

+        GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST

+#define GPO_I2STX_4CH1_SDO0             \

+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0

+#define GPO_I2STX_4CH1_SDO1             \

+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1

+#define GPO_I2STX_4CH1_SDO2             \

+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2

+#define GPO_I2STX_4CH1_SDO3             \

+        GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3

+#define GPO_I2STX0_BCLK_MST             \

+        GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST

+#define GPO_I2STX0_LRCK_MST             \

+        GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST

+#define GPO_JTAG_CPU_CERTIFICATION_TDO  \

+        GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO

+#define GPO_JTAG_DSP_TDO                \

+        GPO_SYS_IOMUX_U0_HIFI4_JTDO

+#define GPO_PDM_4MIC0_DMIC_MCLK         \

+        GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK

+#define GPO_PTC0_PWM_0                  \

+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0

+#define GPO_PTC0_PWM_1                  \

+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1

+#define GPO_PTC0_PWM_2                  \

+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2

+#define GPO_PTC0_PWM_3                  \

+        GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3

+#define GPO_PWMDAC0_LEFT_OUTPUT         \

+        GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT

+#define GPO_PWMDAC0_RIGHT_OUTPUT        \

+        GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT

+#define GPO_QSPI0_CSN1                  \

+        GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1

+#define GPO_SDIO0_BACK_END_POWER        \

+        GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER

+#define GPO_SDIO0_CARD_POWER_EN         \

+        GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN

+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N   \

+        GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N

+#define GPO_SDIO0_RST_N                 \

+        GPO_SYS_IOMUX_U0_DW_SDIO_RST_N

+#define GPO_SDIO1_BACK_END_POWER        \

+        GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER

+#define GPO_SDIO1_CARD_POWER_EN         \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN

+#define GPO_SDIO1_CCLK_OUT              \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT

+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N   \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N

+#define GPO_SDIO1_CCMD_OUT              \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT

+#define GPO_SDIO1_CDATA_OUT_0           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0

+#define GPO_SDIO1_CDATA_OUT_1           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1

+#define GPO_SDIO1_CDATA_OUT_2           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2

+#define GPO_SDIO1_CDATA_OUT_3           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3

+#define GPO_SDIO1_CDATA_OUT_4           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4

+#define GPO_SDIO1_CDATA_OUT_5           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5

+#define GPO_SDIO1_CDATA_OUT_6           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6

+#define GPO_SDIO1_CDATA_OUT_7           \

+        GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7

+#define GPO_SDIO1_RST_N                 \

+        GPO_SYS_IOMUX_U1_DW_SDIO_RST_N

+#define GPO_SPDIF0_SPDIFO               \

+        GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO

+#define GPO_SPI0_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT

+#define GPO_SPI0_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT

+#define GPO_SPI0_SSPTXD                 \

+        GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD

+#define GPO_SPI1_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT

+#define GPO_SPI1_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT

+#define GPO_SPI1_SSPTXD                 \

+        GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD

+#define GPO_SPI2_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT

+#define GPO_SPI2_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT

+#define GPO_SPI2_SSPTXD                 \

+        GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD

+#define GPO_SPI3_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT

+#define GPO_SPI3_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT

+#define GPO_SPI3_SSPTXD                 \

+        GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD

+#define GPO_SPI4_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT

+#define GPO_SPI4_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT

+#define GPO_SPI4_SSPTXD                 \

+        GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD

+#define GPO_SPI5_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT

+#define GPO_SPI5_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT

+#define GPO_SPI5_SSPTXD                 \

+        GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD

+#define GPO_SPI6_SSPCLKOUT              \

+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT

+#define GPO_SPI6_SSPFSSOUT              \

+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT

+#define GPO_SPI6_SSPTXD                 \

+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD

+#define GPO_TDM0_CLK_MST                \

+        GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST

+#define GPO_TDM0_PCM_SYNCOUT            \

+        GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT

+#define GPO_TDM0_PCM_TXD                \

+        GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD

+#define GPO_U7MC_TRACE0_TDATA_0         \

+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0

+#define GPO_U7MC_TRACE0_TDATA_1         \

+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1

+#define GPO_U7MC_TRACE0_TDATA_2         \

+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2

+#define GPO_U7MC_TRACE0_TDATA_3         \

+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3

+#define GPO_U7MC_TRACE0_TREF            \

+        GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF

+#define GPO_UART0_SOUT                  \

+        GPO_SYS_IOMUX_U0_DW_UART_SOUT

+#define GPO_UART1_RTS_N                 \

+        GPO_SYS_IOMUX_U1_DW_UART_RTS_N

+#define GPO_UART1_SOUT                  \

+        GPO_SYS_IOMUX_U1_DW_UART_SOUT

+#define GPO_UART2_RTS_N                 \

+        GPO_SYS_IOMUX_U2_DW_UART_RTS_N

+#define GPO_UART2_SOUT                  \

+        GPO_SYS_IOMUX_U2_DW_UART_SOUT

+#define GPO_UART3_SOUT                  \

+        GPO_SYS_IOMUX_U3_DW_UART_SOUT

+#define GPO_UART4_RTS_N                 \

+        GPO_SYS_IOMUX_U4_DW_UART_RTS_N

+#define GPO_UART4_SOUT                  \

+        GPO_SYS_IOMUX_U4_DW_UART_SOUT

+#define GPO_UART5_RTS_N                 \

+        GPO_SYS_IOMUX_U5_DW_UART_RTS_N

+#define GPO_UART5_SOUT                  \

+        GPO_SYS_IOMUX_U5_DW_UART_SOUT

+#define GPO_USB0_DRIVE_VBUS_IO          \

+        GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO

+#define GPO_WAVE511_0_O_UART_TXSOUT     \

+        GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT

+#define GPO_WDT0_WDOGRES                \

+        GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES

+#define GPO_NONE                        \

+        GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD + 1

+

+// gpo(n)_doen signal pool

+#define OEN_LOW   0

+#define OEN_HIGH  1

+#define OEN_HDMI0_CEC_SDA_OEN               \

+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN

+#define OEN_HDMI0_DDC_SCL_OEN               \

+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN

+#define OEN_HDMI0_DDC_SDA_OEN               \

+        GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN

+#define OEN_I2C0_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE

+#define OEN_I2C0_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE

+#define OEN_I2C1_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE

+#define OEN_I2C1_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE

+#define OEN_I2C2_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE

+#define OEN_I2C2_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE

+#define OEN_I2C3_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE

+#define OEN_I2C3_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE

+#define OEN_I2C4_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE

+#define OEN_I2C4_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE

+#define OEN_I2C5_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE

+#define OEN_I2C5_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE

+#define OEN_I2C6_IC_CLK_OE                  \

+        GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE

+#define OEN_I2C6_IC_DATA_OE                 \

+        GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE

+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE   \

+        GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE

+#define OEN_JTAG_DSP_TDO_OEN                \

+        GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN

+#define OEN_PTC0_PWM_0_OE_N                 \

+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0

+#define OEN_PTC0_PWM_1_OE_N                 \

+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1

+#define OEN_PTC0_PWM_2_OE_N                 \

+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2

+#define OEN_PTC0_PWM_3_OE_N                 \

+        GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3

+#define OEN_SDIO1_CCMD_OUT_EN               \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN

+#define OEN_SDIO1_CDATA_OUT_EN_0            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0

+#define OEN_SDIO1_CDATA_OUT_EN_1            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1

+#define OEN_SDIO1_CDATA_OUT_EN_2            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2

+#define OEN_SDIO1_CDATA_OUT_EN_3            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3

+#define OEN_SDIO1_CDATA_OUT_EN_4            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4

+#define OEN_SDIO1_CDATA_OUT_EN_5            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5

+#define OEN_SDIO1_CDATA_OUT_EN_6            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6

+#define OEN_SDIO1_CDATA_OUT_EN_7            \

+        GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7

+#define OEN_SPI0_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE

+#define OEN_SPI0_NSSPOE                     \

+        GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE

+#define OEN_SPI1_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE

+#define OEN_SPI1_NSSPOE                     \

+        GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE

+#define OEN_SPI2_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE

+#define OEN_SPI2_NSSPOE                     \

+        GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE

+#define OEN_SPI3_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE

+#define OEN_SPI3_NSSPOE                     \

+        GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE

+#define OEN_SPI4_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE

+#define OEN_SPI4_NSSPOE                     \

+        GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE

+#define OEN_SPI5_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE

+#define OEN_SPI5_NSSPOE                     \

+        GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE

+#define OEN_SPI6_NSSPCTLOE                  \

+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE

+#define OEN_SPI6_NSSPOE                     \

+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE

+#define OEN_TDM0_NPCM_SYNCOE                \

+        GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE

+#define OEN_TDM0_NPCM_TXDOE                 \

+        GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE

+#define OEN_NONE                            \

+        GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1

+

+// sys_iomux gpi din

+#define GPI_CAN0_CTRL_RXD                       \

+        GPI_SYS_IOMUX_U0_CAN_CTRL_RXD

+#define GPI_CAN1_CTRL_RXD                       \

+        GPI_SYS_IOMUX_U1_CAN_CTRL_RXD

+#define GPI_CRG0_EXT_MCLK                       \

+        GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK

+#define GPI_HDMI0_CEC_SDA_IN                    \

+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN

+#define GPI_HDMI0_DDC_SCL_IN                    \

+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN

+#define GPI_HDMI0_DDC_SDA_IN                    \

+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN

+#define GPI_HDMI0_HPD                           \

+        GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD

+#define GPI_I2C0_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C0_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C1_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C1_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C2_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C2_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C3_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C3_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C4_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C4_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C5_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C5_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A

+#define GPI_I2C6_IC_CLK_IN_A                    \

+        GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A

+#define GPI_I2C6_IC_DATA_IN_A                   \

+        GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A

+#define GPI_I2SRX0_BCLK_SLV                     \

+        GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV

+#define GPI_I2SRX0_EXT_SDIN0                    \

+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0

+#define GPI_I2SRX0_EXT_SDIN1                    \

+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1

+#define GPI_I2SRX0_EXT_SDIN2                    \

+        GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2

+#define GPI_I2SRX0_LRCK_SLV                     \

+        GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV

+#define GPI_I2STX0_BCLK_SLV                     \

+        GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV

+#define GPI_I2STX0_LRCK_SLV                     \

+        GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV

+#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN \

+        GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN

+#define GPI_JTAG_CPU_CERTIFICATION_TCK          \

+        GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK

+#define GPI_JTAG_CPU_CERTIFICATION_TDI          \

+        GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI

+#define GPI_JTAG_CPU_CERTIFICATION_TMS          \

+        GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS

+#define GPI_JTAG_DSP_TCK                        \

+        GPI_SYS_IOMUX_U0_HIFI4_JTCK

+#define GPI_JTAG_DSP_TDI                        \

+        GPI_SYS_IOMUX_U0_HIFI4_JTDI

+#define GPI_JTAG_DSP_TMS                        \

+        GPI_SYS_IOMUX_U0_HIFI4_JTMS

+#define GPI_JTAG_DSP_TRST_N                     \

+        GPI_SYS_IOMUX_U0_HIFI4_JTRSTN

+#define GPI_PDM_4MIC0_DMIC0_DIN                 \

+        GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN

+#define GPI_PDM_4MIC0_DMIC1_DIN                 \

+        GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN

+#define GPI_SDIO0_CARD_DETECT_N                 \

+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N

+#define GPI_SDIO0_CARD_INT_N                    \

+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N

+#define GPI_SDIO0_CARD_WRITE_PRT                \

+        GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT

+#define GPI_SDIO1_CARD_DETECT_N                 \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N

+#define GPI_SDIO1_CARD_INT_N                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N

+#define GPI_SDIO1_CARD_WRITE_PRT                \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT

+#define GPI_SDIO1_CCMD_IN                       \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN

+#define GPI_SDIO1_CDATA_IN_0                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0

+#define GPI_SDIO1_CDATA_IN_1                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1

+#define GPI_SDIO1_CDATA_IN_2                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2

+#define GPI_SDIO1_CDATA_IN_3                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3

+#define GPI_SDIO1_CDATA_IN_4                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4

+#define GPI_SDIO1_CDATA_IN_5                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5

+#define GPI_SDIO1_CDATA_IN_6                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6

+#define GPI_SDIO1_CDATA_IN_7                    \

+        GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7

+#define GPI_SDIO1_DATA_STROBE                   \

+        GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE

+#define GPI_SPDIF0_SPDIFI                       \

+        GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI

+#define GPI_SPI0_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN

+#define GPI_SPI0_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN

+#define GPI_SPI0_SSPRXD                         \

+        GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD

+#define GPI_SPI1_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN

+#define GPI_SPI1_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN

+#define GPI_SPI1_SSPRXD                         \

+        GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD

+#define GPI_SPI2_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN

+#define GPI_SPI2_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN

+#define GPI_SPI2_SSPRXD                         \

+        GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD

+#define GPI_SPI3_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN

+#define GPI_SPI3_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN

+#define GPI_SPI3_SSPRXD                         \

+        GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD

+#define GPI_SPI4_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN

+#define GPI_SPI4_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN

+#define GPI_SPI4_SSPRXD                         \

+        GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD

+#define GPI_SPI5_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN

+#define GPI_SPI5_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN

+#define GPI_SPI5_SSPRXD                         \

+        GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD

+#define GPI_SPI6_SSPCLKIN                       \

+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN

+#define GPI_SPI6_SSPFSSIN                       \

+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN

+#define GPI_SPI6_SSPRXD                         \

+        GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD

+#define GPI_TDM0_CLK_SLV                        \

+        GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV

+#define GPI_TDM0_PCM_RXD                        \

+        GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD

+#define GPI_TDM0_PCM_SYNCIN                     \

+        GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN

+#define GPI_UART0_SIN                           \

+        GPI_SYS_IOMUX_U0_DW_UART_SIN

+#define GPI_UART1_CTS_N                         \

+        GPI_SYS_IOMUX_U1_DW_UART_CTS_N

+#define GPI_UART1_SIN                           \

+        GPI_SYS_IOMUX_U1_DW_UART_SIN

+#define GPI_UART2_CTS_N                         \

+        GPI_SYS_IOMUX_U2_DW_UART_CTS_N

+#define GPI_UART2_SIN                           \

+        GPI_SYS_IOMUX_U2_DW_UART_SIN

+#define GPI_UART3_SIN                           \

+        GPI_SYS_IOMUX_U3_DW_UART_SIN

+#define GPI_UART4_CTS_N                         \

+        GPI_SYS_IOMUX_U4_DW_UART_CTS_N

+#define GPI_UART4_SIN                           \

+        GPI_SYS_IOMUX_U4_DW_UART_SIN

+#define GPI_UART5_CTS_N                         \

+        GPI_SYS_IOMUX_U5_DW_UART_CTS_N

+#define GPI_UART5_SIN                           \

+        GPI_SYS_IOMUX_U5_DW_UART_SIN

+#define GPI_USB0_OVERCURRENT_N_IO               \

+        GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO

+#define GPI_WAVE511_0_I_UART_RXSIN              \

+        GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN

+#define GPI_NONE  GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD

+

+// sys_iomux syscon

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR  (0x24cU)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR  (0x250U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR  (0x254U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR  (0x258U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR  (0x25cU)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR  (0x260U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR  (0x264U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR  (0x268U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR  (0x26cU)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR  (0x270U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR  (0x274U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR  (0x278U)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR  (0x27cU)

+#define SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR  (0x280U)

+

+#define PADCFG_PAD_GMAC1_MDC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR

+#define PADCFG_PAD_GMAC1_MDIO_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR

+#define PADCFG_PAD_GMAC1_RXD0_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR

+#define PADCFG_PAD_GMAC1_RXD1_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR

+#define PADCFG_PAD_GMAC1_RXD2_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR

+#define PADCFG_PAD_GMAC1_RXD3_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR

+#define PADCFG_PAD_GMAC1_RXDV_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR

+#define PADCFG_PAD_GMAC1_RXC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR

+#define PADCFG_PAD_GMAC1_TXD0_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR

+#define PADCFG_PAD_GMAC1_TXD1_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR

+#define PADCFG_PAD_GMAC1_TXD2_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR

+#define PADCFG_PAD_GMAC1_TXD3_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR

+#define PADCFG_PAD_GMAC1_TXEN_SYSCON  SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR

+#define PADCFG_PAD_GMAC1_TXC_SYSCON   SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR

+

+// sys_iomux func sel setting

+#define SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                 (0x29cU)

+#define PAD_GMAC1_RXC_FUNC_SEL_WIDTH                       0x2U

+#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT                       0x0U

+#define PAD_GMAC1_RXC_FUNC_SEL_MASK                        0x3U

+#define PAD_GPIO10_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO10_FUNC_SEL_SHIFT                          0x2U

+#define PAD_GPIO10_FUNC_SEL_MASK                           0x1CU

+#define PAD_GPIO11_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO11_FUNC_SEL_SHIFT                          0x5U

+#define PAD_GPIO11_FUNC_SEL_MASK                           0xE0U

+#define PAD_GPIO12_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO12_FUNC_SEL_SHIFT                          0x8U

+#define PAD_GPIO12_FUNC_SEL_MASK                           0x700U

+#define PAD_GPIO13_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO13_FUNC_SEL_SHIFT                          0xBU

+#define PAD_GPIO13_FUNC_SEL_MASK                           0x3800U

+#define PAD_GPIO14_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO14_FUNC_SEL_SHIFT                          0xEU

+#define PAD_GPIO14_FUNC_SEL_MASK                           0x1C000U

+#define PAD_GPIO15_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO15_FUNC_SEL_SHIFT                          0x11U

+#define PAD_GPIO15_FUNC_SEL_MASK                           0xE0000U

+#define PAD_GPIO16_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO16_FUNC_SEL_SHIFT                          0x14U

+#define PAD_GPIO16_FUNC_SEL_MASK                           0x700000U

+#define PAD_GPIO17_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO17_FUNC_SEL_SHIFT                          0x17U

+#define PAD_GPIO17_FUNC_SEL_MASK                           0x3800000U

+#define PAD_GPIO18_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO18_FUNC_SEL_SHIFT                          0x1AU

+#define PAD_GPIO18_FUNC_SEL_MASK                           0x1C000000U

+#define PAD_GPIO19_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO19_FUNC_SEL_SHIFT                          0x1DU

+#define PAD_GPIO19_FUNC_SEL_MASK                           0xE0000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                 (0x2a0U)

+#define PAD_GPIO20_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO20_FUNC_SEL_SHIFT                          0x0U

+#define PAD_GPIO20_FUNC_SEL_MASK                           0x7U

+#define PAD_GPIO21_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO21_FUNC_SEL_SHIFT                          0x3U

+#define PAD_GPIO21_FUNC_SEL_MASK                           0x38U

+#define PAD_GPIO22_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO22_FUNC_SEL_SHIFT                          0x6U

+#define PAD_GPIO22_FUNC_SEL_MASK                           0x1C0U

+#define PAD_GPIO23_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO23_FUNC_SEL_SHIFT                          0x9U

+#define PAD_GPIO23_FUNC_SEL_MASK                           0xE00U

+#define PAD_GPIO24_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO24_FUNC_SEL_SHIFT                          0xCU

+#define PAD_GPIO24_FUNC_SEL_MASK                           0x7000U

+#define PAD_GPIO25_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO25_FUNC_SEL_SHIFT                          0xFU

+#define PAD_GPIO25_FUNC_SEL_MASK                           0x38000U

+#define PAD_GPIO26_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO26_FUNC_SEL_SHIFT                          0x12U

+#define PAD_GPIO26_FUNC_SEL_MASK                           0x1C0000U

+#define PAD_GPIO27_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO27_FUNC_SEL_SHIFT                          0x15U

+#define PAD_GPIO27_FUNC_SEL_MASK                           0xE00000U

+#define PAD_GPIO28_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO28_FUNC_SEL_SHIFT                          0x18U

+#define PAD_GPIO28_FUNC_SEL_MASK                           0x7000000U

+#define PAD_GPIO29_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO29_FUNC_SEL_SHIFT                          0x1BU

+#define PAD_GPIO29_FUNC_SEL_MASK                           0x38000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                 (0x2a4U)

+#define PAD_GPIO30_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO30_FUNC_SEL_SHIFT                          0x0U

+#define PAD_GPIO30_FUNC_SEL_MASK                           0x7U

+#define PAD_GPIO31_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO31_FUNC_SEL_SHIFT                          0x3U

+#define PAD_GPIO31_FUNC_SEL_MASK                           0x38U

+#define PAD_GPIO32_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO32_FUNC_SEL_SHIFT                          0x6U

+#define PAD_GPIO32_FUNC_SEL_MASK                           0x1C0U

+#define PAD_GPIO33_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO33_FUNC_SEL_SHIFT                          0x9U

+#define PAD_GPIO33_FUNC_SEL_MASK                           0xE00U

+#define PAD_GPIO34_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO34_FUNC_SEL_SHIFT                          0xCU

+#define PAD_GPIO34_FUNC_SEL_MASK                           0x7000U

+#define PAD_GPIO35_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO35_FUNC_SEL_SHIFT                          0xFU

+#define PAD_GPIO35_FUNC_SEL_MASK                           0x18000U

+#define PAD_GPIO36_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO36_FUNC_SEL_SHIFT                          0x11U

+#define PAD_GPIO36_FUNC_SEL_MASK                           0xE0000U

+#define PAD_GPIO37_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO37_FUNC_SEL_SHIFT                          0x14U

+#define PAD_GPIO37_FUNC_SEL_MASK                           0x700000U

+#define PAD_GPIO38_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO38_FUNC_SEL_SHIFT                          0x17U

+#define PAD_GPIO38_FUNC_SEL_MASK                           0x3800000U

+#define PAD_GPIO39_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO39_FUNC_SEL_SHIFT                          0x1AU

+#define PAD_GPIO39_FUNC_SEL_MASK                           0x1C000000U

+#define PAD_GPIO40_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO40_FUNC_SEL_SHIFT                          0x1DU

+#define PAD_GPIO40_FUNC_SEL_MASK                           0xE0000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                 (0x2a8U)

+#define PAD_GPIO41_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO41_FUNC_SEL_SHIFT                          0x0U

+#define PAD_GPIO41_FUNC_SEL_MASK                           0x7U

+#define PAD_GPIO42_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO42_FUNC_SEL_SHIFT                          0x3U

+#define PAD_GPIO42_FUNC_SEL_MASK                           0x38U

+#define PAD_GPIO43_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO43_FUNC_SEL_SHIFT                          0x6U

+#define PAD_GPIO43_FUNC_SEL_MASK                           0x1C0U

+#define PAD_GPIO44_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO44_FUNC_SEL_SHIFT                          0x9U

+#define PAD_GPIO44_FUNC_SEL_MASK                           0xE00U

+#define PAD_GPIO45_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO45_FUNC_SEL_SHIFT                          0xCU

+#define PAD_GPIO45_FUNC_SEL_MASK                           0x7000U

+#define PAD_GPIO46_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO46_FUNC_SEL_SHIFT                          0xFU

+#define PAD_GPIO46_FUNC_SEL_MASK                           0x38000U

+#define PAD_GPIO47_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO47_FUNC_SEL_SHIFT                          0x12U

+#define PAD_GPIO47_FUNC_SEL_MASK                           0x1C0000U

+#define PAD_GPIO48_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO48_FUNC_SEL_SHIFT                          0x15U

+#define PAD_GPIO48_FUNC_SEL_MASK                           0xE00000U

+#define PAD_GPIO49_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO49_FUNC_SEL_SHIFT                          0x18U

+#define PAD_GPIO49_FUNC_SEL_MASK                           0x7000000U

+#define PAD_GPIO50_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO50_FUNC_SEL_SHIFT                          0x1BU

+#define PAD_GPIO50_FUNC_SEL_MASK                           0x38000000U

+#define PAD_GPIO51_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO51_FUNC_SEL_SHIFT                          0x1EU

+#define PAD_GPIO51_FUNC_SEL_MASK                           0xC0000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                 (0x2acU)

+#define PAD_GPIO52_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO52_FUNC_SEL_SHIFT                          0x0U

+#define PAD_GPIO52_FUNC_SEL_MASK                           0x3U

+#define PAD_GPIO53_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO53_FUNC_SEL_SHIFT                          0x2U

+#define PAD_GPIO53_FUNC_SEL_MASK                           0xCU

+#define PAD_GPIO54_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO54_FUNC_SEL_SHIFT                          0x4U

+#define PAD_GPIO54_FUNC_SEL_MASK                           0x30U

+#define PAD_GPIO55_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO55_FUNC_SEL_SHIFT                          0x6U

+#define PAD_GPIO55_FUNC_SEL_MASK                           0x1C0U

+#define PAD_GPIO56_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO56_FUNC_SEL_SHIFT                          0x9U

+#define PAD_GPIO56_FUNC_SEL_MASK                           0xE00U

+#define PAD_GPIO57_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO57_FUNC_SEL_SHIFT                          0xCU

+#define PAD_GPIO57_FUNC_SEL_MASK                           0x7000U

+#define PAD_GPIO58_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO58_FUNC_SEL_SHIFT                          0xFU

+#define PAD_GPIO58_FUNC_SEL_MASK                           0x38000U

+#define PAD_GPIO59_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO59_FUNC_SEL_SHIFT                          0x12U

+#define PAD_GPIO59_FUNC_SEL_MASK                           0x1C0000U

+#define PAD_GPIO60_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO60_FUNC_SEL_SHIFT                          0x15U

+#define PAD_GPIO60_FUNC_SEL_MASK                           0xE00000U

+#define PAD_GPIO61_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO61_FUNC_SEL_SHIFT                          0x18U

+#define PAD_GPIO61_FUNC_SEL_MASK                           0x7000000U

+#define PAD_GPIO62_FUNC_SEL_WIDTH                          0x3U

+#define PAD_GPIO62_FUNC_SEL_SHIFT                          0x1BU

+#define PAD_GPIO62_FUNC_SEL_MASK                           0x38000000U

+#define PAD_GPIO63_FUNC_SEL_WIDTH                          0x2U

+#define PAD_GPIO63_FUNC_SEL_SHIFT                          0x1EU

+#define PAD_GPIO63_FUNC_SEL_MASK                           0xC0000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                 (0x2b0U)

+#define PAD_GPIO6_FUNC_SEL_WIDTH                           0x2U

+#define PAD_GPIO6_FUNC_SEL_SHIFT                           0x0U

+#define PAD_GPIO6_FUNC_SEL_MASK                            0x3U

+#define PAD_GPIO7_FUNC_SEL_WIDTH                           0x3U

+#define PAD_GPIO7_FUNC_SEL_SHIFT                           0x2U

+#define PAD_GPIO7_FUNC_SEL_MASK                            0x1CU

+#define PAD_GPIO8_FUNC_SEL_WIDTH                           0x3U

+#define PAD_GPIO8_FUNC_SEL_SHIFT                           0x5U

+#define PAD_GPIO8_FUNC_SEL_MASK                            0xE0U

+#define PAD_GPIO9_FUNC_SEL_WIDTH                           0x3U

+#define PAD_GPIO9_FUNC_SEL_SHIFT                           0x8U

+#define PAD_GPIO9_FUNC_SEL_MASK                            0x700U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT   0xBU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK    0x3800U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_WIDTH  0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT  0xEU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK   0x1C000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_WIDTH  0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT  0x11U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK   0xE0000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT   0x14U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK    0x700000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT   0x17U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK    0x3800000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT   0x1AU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK    0x1C000000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT   0x1DU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK    0xE0000000U

+#define SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                 (0x2b4U)

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT   0x0U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK    0x7U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK    0x38U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT   0x6U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK    0x1C0U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT   0x9U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK    0xE00U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_WIDTH   0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT   0xCU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK    0x7000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_WIDTH  0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT  0xFU

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK   0x38000U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_WIDTH  0x3U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT  0x12U

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK   0x1C0000U

+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_WIDTH                  0x3U

+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT                  0x15U

+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK                   0xE00000U

+

+#define PAD_GMAC1_RXC_FUNC_SEL                              \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GMAC1_RXC_FUNC_SEL_SHIFT                        \

+        PAD_GMAC1_RXC_FUNC_SEL_MASK

+#define PAD_GPIO10_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO10_FUNC_SEL_SHIFT                           \

+        PAD_GPIO10_FUNC_SEL_MASK

+#define PAD_GPIO11_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO11_FUNC_SEL_SHIFT                           \

+        PAD_GPIO11_FUNC_SEL_MASK

+#define PAD_GPIO12_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO12_FUNC_SEL_SHIFT                           \

+        PAD_GPIO12_FUNC_SEL_MASK

+#define PAD_GPIO13_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO13_FUNC_SEL_SHIFT                           \

+        PAD_GPIO13_FUNC_SEL_MASK

+#define PAD_GPIO14_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO14_FUNC_SEL_SHIFT                           \

+        PAD_GPIO14_FUNC_SEL_MASK

+#define PAD_GPIO15_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO15_FUNC_SEL_SHIFT                           \

+        PAD_GPIO15_FUNC_SEL_MASK

+#define PAD_GPIO16_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO16_FUNC_SEL_SHIFT                           \

+        PAD_GPIO16_FUNC_SEL_MASK

+#define PAD_GPIO17_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO17_FUNC_SEL_SHIFT                           \

+        PAD_GPIO17_FUNC_SEL_MASK

+#define PAD_GPIO18_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO18_FUNC_SEL_SHIFT                           \

+        PAD_GPIO18_FUNC_SEL_MASK

+#define PAD_GPIO19_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR                  \

+        PAD_GPIO19_FUNC_SEL_SHIFT                           \

+        PAD_GPIO19_FUNC_SEL_MASK

+#define PAD_GPIO20_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO20_FUNC_SEL_SHIFT                           \

+        PAD_GPIO20_FUNC_SEL_MASK

+#define PAD_GPIO21_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO21_FUNC_SEL_SHIFT                           \

+        PAD_GPIO21_FUNC_SEL_MASK

+#define PAD_GPIO22_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO22_FUNC_SEL_SHIFT                           \

+        PAD_GPIO22_FUNC_SEL_MASK

+#define PAD_GPIO23_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO23_FUNC_SEL_SHIFT                           \

+        PAD_GPIO23_FUNC_SEL_MASK

+#define PAD_GPIO24_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO24_FUNC_SEL_SHIFT                           \

+        PAD_GPIO24_FUNC_SEL_MASK

+#define PAD_GPIO25_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO25_FUNC_SEL_SHIFT                           \

+        PAD_GPIO25_FUNC_SEL_MASK

+#define PAD_GPIO26_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO26_FUNC_SEL_SHIFT                           \

+        PAD_GPIO26_FUNC_SEL_MASK

+#define PAD_GPIO27_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO27_FUNC_SEL_SHIFT                           \

+        PAD_GPIO27_FUNC_SEL_MASK

+#define PAD_GPIO28_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO28_FUNC_SEL_SHIFT                           \

+        PAD_GPIO28_FUNC_SEL_MASK

+#define PAD_GPIO29_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR                  \

+        PAD_GPIO29_FUNC_SEL_SHIFT                           \

+        PAD_GPIO29_FUNC_SEL_MASK

+#define PAD_GPIO30_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO30_FUNC_SEL_SHIFT                           \

+        PAD_GPIO30_FUNC_SEL_MASK

+#define PAD_GPIO31_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO31_FUNC_SEL_SHIFT                           \

+        PAD_GPIO31_FUNC_SEL_MASK

+#define PAD_GPIO32_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO32_FUNC_SEL_SHIFT                           \

+        PAD_GPIO32_FUNC_SEL_MASK

+#define PAD_GPIO33_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO33_FUNC_SEL_SHIFT                           \

+        PAD_GPIO33_FUNC_SEL_MASK

+#define PAD_GPIO34_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO34_FUNC_SEL_SHIFT                           \

+        PAD_GPIO34_FUNC_SEL_MASK

+#define PAD_GPIO35_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO35_FUNC_SEL_SHIFT                           \

+        PAD_GPIO35_FUNC_SEL_MASK

+#define PAD_GPIO36_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO36_FUNC_SEL_SHIFT                           \

+        PAD_GPIO36_FUNC_SEL_MASK

+#define PAD_GPIO37_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO37_FUNC_SEL_SHIFT                           \

+        PAD_GPIO37_FUNC_SEL_MASK

+#define PAD_GPIO38_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO38_FUNC_SEL_SHIFT                           \

+        PAD_GPIO38_FUNC_SEL_MASK

+#define PAD_GPIO39_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO39_FUNC_SEL_SHIFT                           \

+        PAD_GPIO39_FUNC_SEL_MASK

+#define PAD_GPIO40_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR                  \

+        PAD_GPIO40_FUNC_SEL_SHIFT                           \

+        PAD_GPIO40_FUNC_SEL_MASK

+#define PAD_GPIO41_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO41_FUNC_SEL_SHIFT                           \

+        PAD_GPIO41_FUNC_SEL_MASK

+#define PAD_GPIO42_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO42_FUNC_SEL_SHIFT                           \

+        PAD_GPIO42_FUNC_SEL_MASK

+#define PAD_GPIO43_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO43_FUNC_SEL_SHIFT                           \

+        PAD_GPIO43_FUNC_SEL_MASK

+#define PAD_GPIO44_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO44_FUNC_SEL_SHIFT                           \

+        PAD_GPIO44_FUNC_SEL_MASK

+#define PAD_GPIO45_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO45_FUNC_SEL_SHIFT                           \

+        PAD_GPIO45_FUNC_SEL_MASK

+#define PAD_GPIO46_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO46_FUNC_SEL_SHIFT                           \

+        PAD_GPIO46_FUNC_SEL_MASK

+#define PAD_GPIO47_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO47_FUNC_SEL_SHIFT                           \

+        PAD_GPIO47_FUNC_SEL_MASK

+#define PAD_GPIO48_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO48_FUNC_SEL_SHIFT                           \

+        PAD_GPIO48_FUNC_SEL_MASK

+#define PAD_GPIO49_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO49_FUNC_SEL_SHIFT                           \

+        PAD_GPIO49_FUNC_SEL_MASK

+#define PAD_GPIO50_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO50_FUNC_SEL_SHIFT                           \

+        PAD_GPIO50_FUNC_SEL_MASK

+#define PAD_GPIO51_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR                  \

+        PAD_GPIO51_FUNC_SEL_SHIFT                           \

+        PAD_GPIO51_FUNC_SEL_MASK

+#define PAD_GPIO52_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO52_FUNC_SEL_SHIFT                           \

+        PAD_GPIO52_FUNC_SEL_MASK

+#define PAD_GPIO53_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO53_FUNC_SEL_SHIFT                           \

+        PAD_GPIO53_FUNC_SEL_MASK

+#define PAD_GPIO54_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO54_FUNC_SEL_SHIFT                           \

+        PAD_GPIO54_FUNC_SEL_MASK

+#define PAD_GPIO55_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO55_FUNC_SEL_SHIFT                           \

+        PAD_GPIO55_FUNC_SEL_MASK

+#define PAD_GPIO56_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO56_FUNC_SEL_SHIFT                           \

+        PAD_GPIO56_FUNC_SEL_MASK

+#define PAD_GPIO57_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO57_FUNC_SEL_SHIFT                           \

+        PAD_GPIO57_FUNC_SEL_MASK

+#define PAD_GPIO58_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO58_FUNC_SEL_SHIFT                           \

+        PAD_GPIO58_FUNC_SEL_MASK

+#define PAD_GPIO59_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO59_FUNC_SEL_SHIFT                           \

+        PAD_GPIO59_FUNC_SEL_MASK

+#define PAD_GPIO60_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO60_FUNC_SEL_SHIFT                           \

+        PAD_GPIO60_FUNC_SEL_MASK

+#define PAD_GPIO61_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO61_FUNC_SEL_SHIFT                           \

+        PAD_GPIO61_FUNC_SEL_MASK

+#define PAD_GPIO62_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO62_FUNC_SEL_SHIFT                           \

+        PAD_GPIO62_FUNC_SEL_MASK

+#define PAD_GPIO63_FUNC_SEL                                 \

+        SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR                  \

+        PAD_GPIO63_FUNC_SEL_SHIFT                           \

+        PAD_GPIO63_FUNC_SEL_MASK

+#define PAD_GPIO6_FUNC_SEL                                  \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        PAD_GPIO6_FUNC_SEL_SHIFT                            \

+        PAD_GPIO6_FUNC_SEL_MASK

+#define PAD_GPIO7_FUNC_SEL                                  \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        PAD_GPIO7_FUNC_SEL_SHIFT                            \

+        PAD_GPIO7_FUNC_SEL_MASK

+#define PAD_GPIO8_FUNC_SEL                                  \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        PAD_GPIO8_FUNC_SEL_SHIFT                            \

+        PAD_GPIO8_FUNC_SEL_MASK

+#define PAD_GPIO9_FUNC_SEL                                  \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        PAD_GPIO9_FUNC_SEL_SHIFT                            \

+        PAD_GPIO9_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL         \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT   \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL         \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT   \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL          \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT    \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL         \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT   \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK

+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL         \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT   \

+        U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK

+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL                         \

+        SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR                  \

+        U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT                   \

+        U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK

+/************************sys_iomux***************************/

+// aon ioconfig

+

+// POS[0]

+#define TESTEN_POS(data)  ((data << 0x0U) & 0x1U)

+

+// SMT[0] POS[1]

+#define RSTN_SMT(data)  ((data << 0x0U) & 0x1U)

+#define RSTN_POS(data)  ((data << 0x1U) & 0x2U)

+

+// DS[1:0]

+#define OSC_DS(data)  ((data << 0x0U) & 0x3U)

+

+// sys ioconfig

+// IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7]

+#define GPIO_IE(data)    ((data << 0x0U) & 0x1U)

+#define GPIO_DS(data)    ((data << 0x1U) & 0x6U)

+#define GPIO_PU(data)    ((data << 0x3U) & 0x8U)

+#define GPIO_PD(data)    ((data << 0x4U) & 0x10U)

+#define GPIO_SLEW(data)  ((data << 0x5U) & 0x20U)

+#define GPIO_SMT(data)   ((data << 0x6U) & 0x40U)

+#define GPIO_POS(data)   ((data << 0x7U) & 0x80U)

+

+#define IO(config)    ((config) & 0xFF)

+#define DOUT(dout)    ((dout) & 0xFF)

+#define DOEN(doen)    ((doen) & 0xFF)

+#define DIN(din_reg)  ((din_reg) & 0xFF)

+

+// syscon value

+#define IO_3_3V  0 /*00:3.3v*/

+#define IO_2_5V  1 /*01:2.5v*/

+#define IO_1_8V  2 /*10:1.8v*/

+

+#endif /* __DT_BINDINGS_JH7110_PIN_CTRL_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h
new file mode 100755
index 000000000000..4763c4de1f22
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Power.h
@@ -0,0 +1,22 @@
+/** @file

+  This header provide all JH7110 power device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_POWER_H__

+#define __DT_BINDINGS_JH7110_POWER_H__

+

+#define JH7110_PD_SYSTOP  0

+#define JH7110_PD_CPU     1

+#define JH7110_PD_GPUA    2

+#define JH7110_PD_VDEC    3

+#define JH7110_PD_VOUT    4

+#define JH7110_PD_ISP     5

+#define JH7110_PD_VENC    6

+#define JH7110_PD_GPUB    7

+

+#endif /* __DT_BINDINGS_JH7110_POWER_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h
new file mode 100644
index 000000000000..fc9a2ff01a00
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/JH7110Rst.h
@@ -0,0 +1,228 @@
+/** @file

+  This header provide all JH7110 reset device tree bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_JH7110_RESET_H__

+#define __DT_BINDINGS_JH7110_RESET_H__

+

+/*

+ * group[0]: syscrg: assert0

+ */

+#define RSTN_U0_JTAG2APB_PRESETN       0

+#define RSTN_U0_SYS_SYSCON_PRESETN     1

+#define RSTN_U0_SYS_IOMUX_PRESETN      2

+#define RSTN_U0_U7MC_RST_BUS           3

+#define RSTN_U0_U7MC_DEBUG             4

+#define RSTN_U0_U7MC_CORE0             5

+#define RSTN_U0_U7MC_CORE1             6

+#define RSTN_U0_U7MC_CORE2             7

+#define RSTN_U0_U7MC_CORE3             8

+#define RSTN_U0_U7MC_CORE4             9

+#define RSTN_U0_U7MC_CORE0_ST          10

+#define RSTN_U0_U7MC_CORE1_ST          11

+#define RSTN_U0_U7MC_CORE2_ST          12

+#define RSTN_U0_U7MC_CORE3_ST          13

+#define RSTN_U0_U7MC_CORE4_ST          14

+#define RSTN_U0_U7MC_TRACE_RST0        15

+#define RSTN_U0_U7MC_TRACE_RST1        16

+#define RSTN_U0_U7MC_TRACE_RST2        17

+#define RSTN_U0_U7MC_TRACE_RST3        18

+#define RSTN_U0_U7MC_TRACE_RST4        19

+#define RSTN_U0_U7MC_TRACE_COM         20

+#define RSTN_U0_IMG_GPU_APB            21

+#define RSTN_U0_IMG_GPU_DOMA           22

+#define RSTN_U0_NOC_BUS_APB_BUS_N      23

+#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N  24

+#define RSTN_U0_NOC_BUS_CPU_AXI_N      25

+#define RSTN_U0_NOC_BUS_DISP_AXI_N     26

+#define RSTN_U0_NOC_BUS_GPU_AXI_N      27

+#define RSTN_U0_NOC_BUS_ISP_AXI_N      28

+#define RSTN_U0_NOC_BUS_DDRC_N         29

+#define RSTN_U0_NOC_BUS_STG_AXI_N      30

+#define RSTN_U0_NOC_BUS_VDEC_AXI_N     31

+

+/*

+ * group[1]: syscrg: assert1

+ */

+#define RSTN_U0_NOC_BUS_VENC_AXI_N     32

+#define RSTN_U0_AXI_CFG1_DEC_AHB       33

+#define RSTN_U0_AXI_CFG1_DEC_MAIN      34

+#define RSTN_U0_AXI_CFG0_DEC_MAIN      35

+#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV  36

+#define RSTN_U0_AXI_CFG0_DEC_HIFI4     37

+#define RSTN_U0_DDR_AXI                38

+#define RSTN_U0_DDR_OSC                39

+#define RSTN_U0_DDR_APB                40

+#define RSTN_U0_DOM_ISP_TOP_N          41

+#define RSTN_U0_DOM_ISP_TOP_AXI        42

+#define RSTN_U0_DOM_VOUT_TOP_SRC       43

+#define RSTN_U0_CODAJ12_AXI            44

+#define RSTN_U0_CODAJ12_CORE           45

+#define RSTN_U0_CODAJ12_APB            46

+#define RSTN_U0_WAVE511_AXI            47

+#define RSTN_U0_WAVE511_BPU            48

+#define RSTN_U0_WAVE511_VCE            49

+#define RSTN_U0_WAVE511_APB            50

+#define RSTN_U0_VDEC_JPG_ARB_JPG       51

+#define RSTN_U0_VDEC_JPG_ARB_MAIN      52

+#define RSTN_U0_AXIMEM_128B_AXI        53

+#define RSTN_U0_WAVE420L_AXI           54

+#define RSTN_U0_WAVE420L_BPU           55

+#define RSTN_U0_WAVE420L_VCE           56

+#define RSTN_U0_WAVE420L_APB           57

+#define RSTN_U1_AXIMEM_128B_AXI        58

+#define RSTN_U2_AXIMEM_128B_AXI        59

+#define RSTN_U0_INTMEM_ROM_SRAM_ROM    60

+#define RSTN_U0_CDNS_QSPI_AHB          61

+#define RSTN_U0_CDNS_QSPI_APB          62

+#define RSTN_U0_CDNS_QSPI_REF          63

+

+/*

+ * group[2]: syscrg: assert2

+ */

+#define RSTN_U0_DW_SDIO_AHB         64

+#define RSTN_U1_DW_SDIO_AHB         65

+#define RSTN_U1_DW_GMAC5_AXI64_A_I  66

+#define RSTN_U1_DW_GMAC5_AXI64_H_N  67

+#define RSTN_U0_MAILBOX_RRESETN     68

+#define RSTN_U0_SSP_SPI_APB         69

+#define RSTN_U1_SSP_SPI_APB         70

+#define RSTN_U2_SSP_SPI_APB         71

+#define RSTN_U3_SSP_SPI_APB         72

+#define RSTN_U4_SSP_SPI_APB         73

+#define RSTN_U5_SSP_SPI_APB         74

+#define RSTN_U6_SSP_SPI_APB         75

+#define RSTN_U0_DW_I2C_APB          76

+#define RSTN_U1_DW_I2C_APB          77

+#define RSTN_U2_DW_I2C_APB          78

+#define RSTN_U3_DW_I2C_APB          79

+#define RSTN_U4_DW_I2C_APB          80

+#define RSTN_U5_DW_I2C_APB          81

+#define RSTN_U6_DW_I2C_APB          82

+#define RSTN_U0_DW_UART_APB         83

+#define RSTN_U0_DW_UART_CORE        84

+#define RSTN_U1_DW_UART_APB         85

+#define RSTN_U1_DW_UART_CORE        86

+#define RSTN_U2_DW_UART_APB         87

+#define RSTN_U2_DW_UART_CORE        88

+#define RSTN_U3_DW_UART_APB         89

+#define RSTN_U3_DW_UART_CORE        90

+#define RSTN_U4_DW_UART_APB         91

+#define RSTN_U4_DW_UART_CORE        92

+#define RSTN_U5_DW_UART_APB         93

+#define RSTN_U5_DW_UART_CORE        94

+#define RSTN_U0_CDNS_SPDIF_APB      95

+

+/*

+ * group[3]: syscrg: assert3

+ */

+#define RSTN_U0_PWMDAC_APB            96

+#define RSTN_U0_PDM_4MIC_DMIC         97

+#define RSTN_U0_PDM_4MIC_APB          98

+#define RSTN_U0_I2SRX_3CH_APB         99

+#define RSTN_U0_I2SRX_3CH_BCLK        100

+#define RSTN_U0_I2STX_4CH_APB         101

+#define RSTN_U0_I2STX_4CH_BCLK        102

+#define RSTN_U1_I2STX_4CH_APB         103

+#define RSTN_U1_I2STX_4CH_BCLK        104

+#define RSTN_U0_TDM16SLOT_AHB         105

+#define RSTN_U0_TDM16SLOT_TDM         106

+#define RSTN_U0_TDM16SLOT_APB         107

+#define RSTN_U0_PWM_8CH_APB           108

+#define RSTN_U0_DSKIT_WDT_APB         109

+#define RSTN_U0_DSKIT_WDT_CORE        110

+#define RSTN_U0_CAN_CTRL_APB          111

+#define RSTN_U0_CAN_CTRL_CORE         112

+#define RSTN_U0_CAN_CTRL_TIMER        113

+#define RSTN_U1_CAN_CTRL_APB          114

+#define RSTN_U1_CAN_CTRL_CORE         115

+#define RSTN_U1_CAN_CTRL_TIMER        116

+#define RSTN_U0_TIMER_APB             117

+#define RSTN_U0_TIMER_TIMER0          118

+#define RSTN_U0_TIMER_TIMER1          119

+#define RSTN_U0_TIMER_TIMER2          120

+#define RSTN_U0_TIMER_TIMER3          121

+#define RSTN_U0_INT_CTRL_APB          122

+#define RSTN_U0_TEMP_SENSOR_APB       123

+#define RSTN_U0_TEMP_SENSOR_TEMP      124

+#define RSTN_U0_JTAG_CERTIFICATION_N  125

+

+/*

+ * group[4]: stgcrg

+ */

+#define RSTN_U0_STG_SYSCON_PRESETN  128

+#define RSTN_U0_HIFI4_CORE          129

+#define RSTN_U0_HIFI4_AXI           130

+#define RSTN_U0_SEC_TOP_HRESETN     131

+#define RSTN_U0_E24_CORE            132

+#define RSTN_U0_DW_DMA1P_AXI        133

+#define RSTN_U0_DW_DMA1P_AHB        134

+#define RSTN_U0_CDN_USB_AXI         135

+#define RSTN_U0_CDN_USB_APB         136

+#define RSTN_U0_CDN_USB_UTMI_APB    137

+#define RSTN_U0_CDN_USB_PWRUP       138

+#define RSTN_U0_PLDA_PCIE_AXI_MST0  139

+#define RSTN_U0_PLDA_PCIE_AXI_SLV0  140

+#define RSTN_U0_PLDA_PCIE_AXI_SLV   141

+#define RSTN_U0_PLDA_PCIE_BRG       142

+#define RSTN_U0_PLDA_PCIE_CORE      143

+#define RSTN_U0_PLDA_PCIE_APB       144

+#define RSTN_U1_PLDA_PCIE_AXI_MST0  145

+#define RSTN_U1_PLDA_PCIE_AXI_SLV0  146

+#define RSTN_U1_PLDA_PCIE_AXI_SLV   147

+#define RSTN_U1_PLDA_PCIE_BRG       148

+#define RSTN_U1_PLDA_PCIE_CORE      149

+#define RSTN_U1_PLDA_PCIE_APB       150

+

+/*

+ * group[5]: aoncrg

+ */

+#define RSTN_U0_DW_GMAC5_AXI64_AXI  160

+#define RSTN_U0_DW_GMAC5_AXI64_AHB  161

+#define RSTN_U0_AON_IOMUX_PRESETN   162

+#define RSTN_U0_PMU_APB             163

+#define RSTN_U0_PMU_WKUP            164

+#define RSTN_U0_RTC_HMS_APB         165

+#define RSTN_U0_RTC_HMS_CAL         166

+#define RSTN_U0_RTC_HMS_OSC32K      167

+

+/*

+ * group[6]: ispcrg

+ */

+#define RSTN_U0_ISPV2_TOP_WRAPPER_P    192

+#define RSTN_U0_ISPV2_TOP_WRAPPER_C    193

+#define RSTN_U0_M31DPHY_HW             194

+#define RSTN_U0_M31DPHY_B09_ALWAYS_ON  195

+#define RSTN_U0_VIN_N_PCLK             196

+#define RSTN_U0_VIN_N_PIXEL_CLK_IF0    197

+#define RSTN_U0_VIN_N_PIXEL_CLK_IF1    198

+#define RSTN_U0_VIN_N_PIXEL_CLK_IF2    199

+#define RSTN_U0_VIN_N_PIXEL_CLK_IF3    200

+#define RSTN_U0_VIN_N_SYS_CLK          201

+#define RSTN_U0_VIN_P_AXIRD            202

+#define RSTN_U0_VIN_P_AXIWR            203

+

+/*

+ * group[7]: voutcrg

+ */

+#define RSTN_U0_DC8200_AXI            224

+#define RSTN_U0_DC8200_AHB            225

+#define RSTN_U0_DC8200_CORE           226

+#define RSTN_U0_CDNS_DSITX_DPI        227

+#define RSTN_U0_CDNS_DSITX_APB        228

+#define RSTN_U0_CDNS_DSITX_RXESC      229

+#define RSTN_U0_CDNS_DSITX_SYS        230

+#define RSTN_U0_CDNS_DSITX_TXBYTEHS   231

+#define RSTN_U0_CDNS_DSITX_TXESC      232

+#define RSTN_U0_HDMI_TX_HDMI          233

+#define RSTN_U0_MIPITX_DPHY_SYS       234

+#define RSTN_U0_MIPITX_DPHY_TXBYTEHS  235

+

+#define RSTN_JH7110_RESET_END  236

+

+#endif /* __DT_BINDINGS_JH7110_RESET_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Led.h b/Platform/StarFive/VisionFive2/DeviceTree/Led.h
new file mode 100644
index 000000000000..53d636e17215
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Led.h
@@ -0,0 +1,90 @@
+/** @file

+  This header provide all the LEDs bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_LEDS_H__

+#define __DT_BINDINGS_LEDS_H__

+

+/* External trigger type */

+#define LEDS_TRIG_TYPE_EDGE   0

+#define LEDS_TRIG_TYPE_LEVEL  1

+

+/* Boost modes */

+#define LEDS_BOOST_OFF       0

+#define LEDS_BOOST_ADAPTIVE  1

+#define LEDS_BOOST_FIXED     2

+

+/* Standard LED colors */

+#define LED_COLOR_ID_WHITE   0

+#define LED_COLOR_ID_RED     1

+#define LED_COLOR_ID_GREEN   2

+#define LED_COLOR_ID_BLUE    3

+#define LED_COLOR_ID_AMBER   4

+#define LED_COLOR_ID_VIOLET  5

+#define LED_COLOR_ID_YELLOW  6

+#define LED_COLOR_ID_IR      7

+#define LED_COLOR_ID_MULTI   8   /* For multicolor LEDs */

+#define LED_COLOR_ID_RGB     9   /* For multicolor LEDs that can do arbitrary color, \

+                                    so this would include RGBW and similar */

+#define LED_COLOR_ID_MAX     10

+

+/* Standard LED functions */

+/* Keyboard LEDs, usually it would be input4::capslock etc. */

+#define LED_FUNCTION_CAPSLOCK       "capslock"

+#define LED_FUNCTION_SCROLLLOCK     "scrolllock"

+#define LED_FUNCTION_NUMLOCK        "numlock"

+#define LED_FUNCTION_KBD_BACKLIGHT  "kbd_backlight"

+

+/* System LEDs, usually found on system body.

+   platform:: mute (etc) is sometimes seen, : mute would be better */

+#define LED_FUNCTION_POWER  "power"

+#define LED_FUNCTION_DISK   "disk"

+

+/*   Obsolete: "platform:*:charging" (allwinner sun50i) */

+#define LED_FUNCTION_CHARGING  "charging"

+

+/*   Used RGB notification LEDs common on phones.

+     Obsolete equivalents: "status-led:{red,green,blue}" (Motorola Droid 4),

+     "lp5523:{r,g,b}" (Nokia N900) */

+#define LED_FUNCTION_STATUS  "status"

+

+#define LED_FUNCTION_MICMUTE  "micmute"

+#define LED_FUNCTION_MUTE     "mute"

+

+/* Miscelleaus functions. Use functions above if you can. */

+#define LED_FUNCTION_ACTIVITY       "activity"

+#define LED_FUNCTION_ALARM          "alarm"

+#define LED_FUNCTION_BACKLIGHT      "backlight"

+#define LED_FUNCTION_BLUETOOTH      "bluetooth"

+#define LED_FUNCTION_BOOT           "boot"

+#define LED_FUNCTION_CPU            "cpu"

+#define LED_FUNCTION_DEBUG          "debug"

+#define LED_FUNCTION_DISK_ACTIVITY  "disk-activity"

+#define LED_FUNCTION_DISK_ERR       "disk-err"

+#define LED_FUNCTION_DISK_READ      "disk-read"

+#define LED_FUNCTION_DISK_WRITE     "disk-write"

+#define LED_FUNCTION_FAULT          "fault"

+#define LED_FUNCTION_FLASH          "flash"

+#define LED_FUNCTION_HEARTBEAT      "heartbeat"

+#define LED_FUNCTION_INDICATOR      "indicator"

+#define LED_FUNCTION_LAN            "lan"

+#define LED_FUNCTION_MAIL           "mail"

+#define LED_FUNCTION_MTD            "mtd"

+#define LED_FUNCTION_PANIC          "panic"

+#define LED_FUNCTION_PROGRAMMING    "programming"

+#define LED_FUNCTION_RX             "rx"

+#define LED_FUNCTION_SD             "sd"

+#define LED_FUNCTION_STANDBY        "standby"

+#define LED_FUNCTION_TORCH          "torch"

+#define LED_FUNCTION_TX             "tx"

+#define LED_FUNCTION_USB            "usb"

+#define LED_FUNCTION_WAN            "wan"

+#define LED_FUNCTION_WLAN           "wlan"

+#define LED_FUNCTION_WPS            "wps"

+

+#endif /* __DT_BINDINGS_LEDS_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi
new file mode 100755
index 000000000000..be3bfe405d99
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveClk.dtsi
@@ -0,0 +1,130 @@
+/** @file

+  Device tree defination for all JH7110 clocks used in StarFive VisionFive 2 platform

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+/ {

+    osc: osc {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <24000000>;

+    };

+

+    clk_ext_camera: clk-ext-camera {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <24000000>;

+    };

+

+    gmac1_rmii_refin: gmac1_rmii_refin {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <50000000>;

+    };

+

+    gmac1_rgmii_rxin: gmac1_rgmii_rxin {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <125000000>;

+    };

+

+    i2stx_bclk_ext: i2stx_bclk_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <12288000>;

+    };

+

+    i2stx_lrck_ext: i2stx_lrck_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <192000>;

+    };

+

+    i2srx_bclk_ext: i2srx_bclk_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <12288000>;

+    };

+

+    i2srx_lrck_ext: i2srx_lrck_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <192000>;

+    };

+

+    tdm_ext: tdm_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <49152000>;

+    };

+

+    mclk_ext: mclk_ext {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <12288000>;

+    };

+

+    jtag_tck_inner: jtag_tck_inner {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <50000000>;

+    };

+

+    bist_apb: bist_apb {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <50000000>;

+    };

+

+    gmac0_rmii_refin: gmac0_rmii_refin {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <50000000>;

+    };

+

+    gmac0_rgmii_rxin: gmac0_rgmii_rxin {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <125000000>;

+    };

+

+    clk_rtc: clk_rtc {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <32768>;

+    };

+

+    hdmitx0_pixelclk: hdmitx0_pixelclk {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <297000000>;

+    };

+

+    mipitx_dphy_rxesc: mipitx_dphy_rxesc {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <10000000>;

+    };

+

+    mipitx_dphy_txbytehs: mipitx_dphy_txbytehs {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <297000000>;

+    };

+

+    wm8960_mclk: wm8960_mclk {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <24576000>;

+    };

+

+    ac108_mclk: ac108_mclk {

+        compatible = "fixed-clock";

+        #clock-cells = <0>;

+        clock-frequency = <24000000>;

+    };

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi
new file mode 100644
index 000000000000..ca96fa954ab4
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveHdmi.dtsi
@@ -0,0 +1,28 @@
+/** @file

+  Device tree defination all JH7110 display audio for StarFive VisionFive 2 platform

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+&sound1 {

+    /* i2s + hdmi */

+    simple-audio-card,dai-link@0 {

+        reg = <0>;

+        format = "i2s";

+        bitclock-master = <&sndi2s0>;

+        frame-master = <&sndi2s0>;

+        mclk-fs = <256>;

+        status = "okay";

+

+        sndi2s0: cpu {

+            sound-dai = <&i2stx_4ch0>;

+        };

+

+        sndhdmi0: codec {

+            sound-dai = <&hdmi>;

+        };

+    };

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi
new file mode 100644
index 000000000000..d216c0357a4b
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveJH7110.dtsi
@@ -0,0 +1,1812 @@
+/** @file

+  Device tree defination for JH7110 SoC

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+/dts-v1/;

+#include "StarFiveClk.dtsi"

+#include "JH7110ClkGen.h"

+#include "JH7110ClkVout.h"

+#include "JH7110ClkIsp.h"

+#include "JH7110Rst.h"

+#include "JH7110Power.h"

+#include "Thermal.h"

+#include "Irq.h"

+

+/ {

+    compatible = "starfive,jh7110";

+    #address-cells = <2>;

+    #size-cells = <2>;

+

+    cluster0_opp: opp-table-0 {

+            compatible = "operating-points-v2";

+            opp-shared;

+            opp-375000000 {

+                    opp-hz = /bits/ 64 <375000000>;

+                    opp-microvolt = <800000>;

+            };

+            opp-500000000 {

+                    opp-hz = /bits/ 64 <500000000>;

+                    opp-microvolt = <800000>;

+            };

+            opp-750000000 {

+                    opp-hz = /bits/ 64 <750000000>;

+                    opp-microvolt = <800000>;

+                    opp-suspend;

+            };

+            opp-1500000000 {

+                    opp-hz = /bits/ 64 <1500000000>;

+                    opp-microvolt = <1040000>;

+            };

+    };

+

+    cpus {

+        #address-cells = <1>;

+        #size-cells = <0>;

+

+        cpu0: cpu@0 {

+            compatible = "sifive,u74-mc", "riscv";

+            reg = <0>;

+            d-cache-block-size = <64>;

+            d-cache-sets = <64>;

+            d-cache-size = <8192>;

+            d-tlb-sets = <1>;

+            d-tlb-size = <40>;

+            device_type = "cpu";

+            i-cache-block-size = <64>;

+            i-cache-sets = <64>;

+            i-cache-size = <16384>;

+            i-tlb-sets = <1>;

+            i-tlb-size = <40>;

+            mmu-type = "riscv,sv39";

+            next-level-cache = <&cachectrl>;

+            riscv,isa = "rv64imac";

+            tlb-split;

+            #cooling-cells = <2>;

+            status = "disabled";

+

+            cpu0intctrl: interrupt-controller {

+                #interrupt-cells = <1>;

+                compatible = "riscv,cpu-intc";

+                interrupt-controller;

+            };

+        };

+

+        cpu1: cpu@1 {

+            compatible = "sifive,u74-mc", "riscv";

+            reg = <1>;

+            d-cache-block-size = <64>;

+            d-cache-sets = <64>;

+            d-cache-size = <32768>;

+            d-tlb-sets = <1>;

+            d-tlb-size = <40>;

+            device_type = "cpu";

+            i-cache-block-size = <64>;

+            i-cache-sets = <64>;

+            i-cache-size = <32768>;

+            i-tlb-sets = <1>;

+            i-tlb-size = <40>;

+            mmu-type = "riscv,sv39";

+            next-level-cache = <&cachectrl>;

+            riscv,isa = "rv64imafdc";

+            tlb-split;

+            #cooling-cells = <2>;

+            status = "okay";

+            operating-points-v2 = <&cluster0_opp>;

+

+            cpu1intctrl: interrupt-controller {

+                #interrupt-cells = <1>;

+                compatible = "riscv,cpu-intc";

+                interrupt-controller;

+            };

+        };

+

+        cpu2: cpu@2 {

+            compatible = "sifive,u74-mc", "riscv";

+            reg = <2>;

+            d-cache-block-size = <64>;

+            d-cache-sets = <64>;

+            d-cache-size = <32768>;

+            d-tlb-sets = <1>;

+            d-tlb-size = <40>;

+            device_type = "cpu";

+            i-cache-block-size = <64>;

+            i-cache-sets = <64>;

+            i-cache-size = <32768>;

+            i-tlb-sets = <1>;

+            i-tlb-size = <40>;

+            mmu-type = "riscv,sv39";

+            next-level-cache = <&cachectrl>;

+            riscv,isa = "rv64imafdc";

+            tlb-split;

+            #cooling-cells = <2>;

+            status = "okay";

+            operating-points-v2 = <&cluster0_opp>;

+

+            cpu2intctrl: interrupt-controller {

+                #interrupt-cells = <1>;

+                compatible = "riscv,cpu-intc";

+                interrupt-controller;

+            };

+        };

+

+        cpu3: cpu@3 {

+            compatible = "sifive,u74-mc", "riscv";

+            reg = <3>;

+            d-cache-block-size = <64>;

+            d-cache-sets = <64>;

+            d-cache-size = <32768>;

+            d-tlb-sets = <1>;

+            d-tlb-size = <40>;

+            device_type = "cpu";

+            i-cache-block-size = <64>;

+            i-cache-sets = <64>;

+            i-cache-size = <32768>;

+            i-tlb-sets = <1>;

+            i-tlb-size = <40>;

+            mmu-type = "riscv,sv39";

+            next-level-cache = <&cachectrl>;

+            riscv,isa = "rv64imafdc";

+            tlb-split;

+            #cooling-cells = <2>;

+            status = "okay";

+            operating-points-v2 = <&cluster0_opp>;

+

+            cpu3intctrl: interrupt-controller {

+                #interrupt-cells = <1>;

+                compatible = "riscv,cpu-intc";

+                interrupt-controller;

+            };

+        };

+

+        cpu4: cpu@4 {

+            compatible = "sifive,u74-mc", "riscv";

+            reg = <4>;

+            d-cache-block-size = <64>;

+            d-cache-sets = <64>;

+            d-cache-size = <32768>;

+            d-tlb-sets = <1>;

+            d-tlb-size = <40>;

+            device_type = "cpu";

+            i-cache-block-size = <64>;

+            i-cache-sets = <64>;

+            i-cache-size = <32768>;

+            i-tlb-sets = <1>;

+            i-tlb-size = <40>;

+            mmu-type = "riscv,sv39";

+            next-level-cache = <&cachectrl>;

+            riscv,isa = "rv64imafdc";

+            tlb-split;

+            #cooling-cells = <2>;

+            status = "okay";

+            operating-points-v2 = <&cluster0_opp>;

+

+            cpu4intctrl: interrupt-controller {

+                #interrupt-cells = <1>;

+                compatible = "riscv,cpu-intc";

+                interrupt-controller;

+            };

+        };

+    };

+

+    soc: soc {

+        compatible = "simple-bus";

+        interrupt-parent = <&plic>;

+        #address-cells = <2>;

+        #size-cells = <2>;

+        #clock-cells = <1>;

+        ranges;

+

+        cachectrl: cache-controller@2010000 {

+            compatible = "sifive,fu740-c000-ccache", "cache";

+            reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;

+            reg-names = "control", "sideband";

+            interrupts = <1 3 4 2>;

+            cache-block-size = <64>;

+            cache-level = <2>;

+            cache-sets = <2048>;

+            cache-size = <2097152>;

+            cache-unified;

+        };

+

+        aon_syscon: aon_syscon@17010000 {

+            compatible = "syscon";

+            reg = <0x0 0x17010000 0x0 0x1000>;

+        };

+

+        phyctrl0: multi-phyctrl@10210000 {

+            compatible = "starfive,phyctrl";

+            reg = <0x0 0x10210000 0x0 0x10000>;

+        };

+

+        phyctrl1: pcie1-phyctrl@10220000 {

+            compatible = "starfive,phyctrl";

+            reg = <0x0 0x10220000 0x0 0x10000>;

+        };

+

+        stg_syscon: stg_syscon@10240000 {

+            compatible = "syscon";

+            reg = <0x0 0x10240000 0x0 0x1000>;

+        };

+

+        sys_syscon: sys_syscon@13030000 {

+            compatible = "syscon";

+            reg = <0x0 0x13030000 0x0 0x1000>;

+        };

+

+        clint: clint@2000000 {

+            compatible = "riscv,clint0";

+            reg = <0x0 0x2000000 0x0 0x10000>;

+            reg-names = "control";

+            interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7

+                        &cpu1intctrl 3 &cpu1intctrl 7

+                        &cpu2intctrl 3 &cpu2intctrl 7

+                        &cpu3intctrl 3 &cpu3intctrl 7

+                        &cpu4intctrl 3 &cpu4intctrl 7>;

+            #interrupt-cells = <1>;

+        };

+

+        plic: plic@c000000 {

+            compatible = "riscv,plic0";

+            reg = <0x0 0xc000000 0x0 0x4000000>;

+            reg-names = "control";

+            interrupts-extended = <&cpu0intctrl 11

+                        &cpu1intctrl 11 &cpu1intctrl 9

+                        &cpu2intctrl 11 &cpu2intctrl 9

+                        &cpu3intctrl 11 &cpu3intctrl 9

+                        &cpu4intctrl 11 &cpu4intctrl 9>;

+            interrupt-controller;

+            #interrupt-cells = <1>;

+            riscv,max-priority = <7>;

+            riscv,ndev = <136>;

+        };

+

+        clkgen: clock-controller {

+            compatible = "starfive,jh7110-clkgen";

+            reg = <0x0 0x13020000 0x0 0x10000>,

+                <0x0 0x10230000 0x0 0x10000>,

+                <0x0 0x17000000 0x0 0x10000>;

+            reg-names = "sys", "stg", "aon";

+            clocks = <&osc>, <&gmac1_rmii_refin>,

+                 <&gmac1_rgmii_rxin>,

+                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

+                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,

+                 <&tdm_ext>, <&mclk_ext>,

+                 <&jtag_tck_inner>, <&bist_apb>,

+                 <&clk_rtc>,

+                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;

+            clock-names = "osc", "gmac1_rmii_refin",

+                "gmac1_rgmii_rxin",

+                "i2stx_bclk_ext", "i2stx_lrck_ext",

+                "i2srx_bclk_ext", "i2srx_lrck_ext",

+                "tdm_ext", "mclk_ext",

+                "jtag_tck_inner", "bist_apb",

+                "clk_rtc",

+                "gmac0_rmii_refin", "gmac0_rgmii_rxin";

+            #clock-cells = <1>;

+            starfive,sys-syscon = <&sys_syscon 0x18 0x1c

+                    0x20 0x24 0x28 0x2c 0x30 0x34>;

+            status = "okay";

+        };

+

+        clkvout: clock-controller@295C0000 {

+            compatible = "starfive,jh7110-clk-vout";

+            reg = <0x0 0x295C0000 0x0 0x10000>;

+            reg-names = "vout";

+            clocks = <&hdmitx0_pixelclk>,

+                 <&mipitx_dphy_rxesc>,

+                 <&mipitx_dphy_txbytehs>,

+                 <&clkgen JH7110_VOUT_SRC>,

+                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;

+            clock-names = "hdmitx0_pixelclk",

+                      "mipitx_dphy_rxesc",

+                      "mipitx_dphy_txbytehs",

+                      "vout_src",

+                      "vout_top_ahb";

+            resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;

+            reset-names = "vout_src";

+            #clock-cells = <1>;

+            power-domains = <&pwrc JH7110_PD_VOUT>;

+            status = "okay";

+        };

+

+        clkisp: clock-controller@19810000 {

+            compatible = "starfive,jh7110-clk-isp";

+            reg = <0x0 0x19810000 0x0 0x10000>;

+            reg-names = "isp";

+            #clock-cells = <1>;

+            clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,

+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,

+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,

+                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;

+            clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",

+                      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",

+                      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",

+                      "u0_sft7110_noc_bus_clk_isp_axi";

+            resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,

+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,

+                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;

+            reset-names = "rst_isp_top_n", "rst_isp_top_axi",

+                      "rst_isp_noc_bus_n";

+            power-domains = <&pwrc JH7110_PD_ISP>;

+            status = "okay";

+        };

+

+        qspi: spi@13010000 {

+            compatible = "cdns,qspi-nor";

+            #address-cells = <1>;

+            #size-cells = <0>;

+            reg = <0x0 0x13010000 0x0 0x10000

+                0x0 0x21000000 0x0 0x400000>;

+            interrupts = <25>;

+            clocks = <&clkgen JH7110_QSPI_CLK_REF>,

+                 <&clkgen JH7110_QSPI_CLK_APB>,

+                 <&clkgen JH7110_AHB1>,

+                 <&clkgen JH7110_QSPI_CLK_AHB>;

+            clock-names = "clk_ref",

+                      "clk_apb",

+                      "ahb1",

+                      "clk_ahb";

+            resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,

+                 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,

+                 <&rstgen RSTN_U0_CDNS_QSPI_REF>;

+            cdns,fifo-depth = <256>;

+            cdns,fifo-width = <4>;

+            cdns,trigger-address = <0x0>;

+            spi-max-frequency = <250000000>;

+

+            nor_flash: nor-flash@0 {

+                compatible = "jedec,spi-nor";

+                reg=<0>;

+                cdns,read-delay = <5>;

+                spi-max-frequency = <100000000>;

+                cdns,tshsl-ns = <1>;

+                cdns,tsd2d-ns = <1>;

+                cdns,tchsh-ns = <1>;

+                cdns,tslch-ns = <1>;

+

+                partitions {

+                    compatible = "fixed-partitions";

+                    #address-cells = <1>;

+                    #size-cells = <1>;

+

+                    spl@0 {

+                        reg = <0x0 0x40000>;

+                    };

+                    uboot@100000 {

+                        reg = <0x100000 0x300000>;

+                    };

+                    data@f00000 {

+                        reg = <0xf00000 0x100000>;

+                    };

+                };

+            };

+        };

+

+        otp: otp@17050000 {

+            compatible = "starfive,jh7110-otp";

+            reg = <0x0 0x17050000 0x0 0x10000>;

+            clock-frequency = <4000000>;

+            clocks = <&clkgen JH7110_OTPC_CLK_APB>;

+            clock-names = "apb";

+        };

+

+        usbdrd30: usbdrd{

+            compatible = "starfive,jh7110-cdns3";

+            reg = <0x0 0x10210000 0x0 0x1000>,

+                  <0x0 0x10200000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_USB_125M>,

+                 <&clkgen JH7110_USB0_CLK_APP_125>,

+                 <&clkgen JH7110_USB0_CLK_LPM>,

+                 <&clkgen JH7110_USB0_CLK_STB>,

+                 <&clkgen JH7110_USB0_CLK_USB_APB>,

+                 <&clkgen JH7110_USB0_CLK_AXI>,

+                 <&clkgen JH7110_USB0_CLK_UTMI_APB>,

+                 <&clkgen JH7110_PCIE0_CLK_APB>;

+            clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";

+            resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,

+                 <&rstgen RSTN_U0_CDN_USB_APB>,

+                 <&rstgen RSTN_U0_CDN_USB_AXI>,

+                 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_APB>;

+            reset-names = "pwrup","apb","axi","utmi", "phy";

+            starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;

+            starfive,sys-syscon = <&sys_syscon 0x18>;

+            status = "disabled";

+            #address-cells = <2>;

+            #size-cells = <2>;

+            #interrupt-cells = <1>;

+            ranges;

+            usbdrd_cdns3: usb@10100000 {

+                compatible = "cdns,usb3";

+                reg = <0x0 0x10100000 0x0 0x10000>,

+                      <0x0 0x10110000 0x0 0x10000>,

+                      <0x0 0x10120000 0x0 0x10000>;

+                reg-names = "otg", "xhci", "dev";

+                interrupts = <100>, <108>, <110>;

+                interrupt-names = "host", "peripheral", "otg";

+                phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";

+                maximum-speed = "super-speed";

+            };

+        };

+

+        timer: timer@13050000 {

+            compatible = "starfive,jh7110-timers";

+            reg = <0x0 0x13050000 0x0 0x10000>;

+            interrupts = <69>, <70>, <71> ,<72>;

+            interrupt-names = "timer0", "timer1",

+                      "timer2", "timer3";

+            clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,

+                 <&clkgen JH7110_TIMER_CLK_TIMER1>,

+                 <&clkgen JH7110_TIMER_CLK_TIMER2>,

+                 <&clkgen JH7110_TIMER_CLK_TIMER3>,

+                 <&clkgen JH7110_TIMER_CLK_APB>;

+            clock-names = "timer0", "timer1",

+                      "timer2", "timer3", "apb_clk";

+            resets = <&rstgen RSTN_U0_TIMER_TIMER0>,

+                 <&rstgen RSTN_U0_TIMER_TIMER1>,

+                 <&rstgen RSTN_U0_TIMER_TIMER2>,

+                 <&rstgen RSTN_U0_TIMER_TIMER3>,

+                 <&rstgen RSTN_U0_TIMER_APB>;

+            reset-names = "timer0", "timer1",

+                      "timer2", "timer3", "apb_rst";

+            clock-frequency = <24000000>;

+            status = "okay";

+        };

+

+        wdog: wdog@13070000 {

+            compatible = "starfive,jh7110-wdt";

+            reg = <0x0 0x13070000 0x0 0x10000>;

+            interrupts = <68>;

+            interrupt-names = "wdog";

+            clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,

+                 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;

+            clock-names = "core_clk", "apb_clk";

+            resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,

+                 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;

+            reset-names = "rst_apb", "rst_core";

+            timeout-sec = <15>;

+            status = "okay";

+        };

+

+        rtc: rtc@17040000 {

+            compatible = "starfive,jh7110-rtc";

+            reg = <0x0 0x17040000 0x0 0x10000>;

+            interrupts = <10>, <11>, <12>;

+            interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";

+            clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,

+                 <&clkgen JH7110_RTC_HMS_CLK_CAL>;

+            clock-names = "pclk", "cal_clk";

+            resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,

+                 <&rstgen RSTN_U0_RTC_HMS_APB>,

+                 <&rstgen RSTN_U0_RTC_HMS_CAL>;

+            reset-names = "rst_osc", "rst_apb", "rst_cal";

+            rtc,cal-clock-freq = <1000000>;

+            status = "okay";

+        };

+

+        pwrc: power-controller@17030000 {

+            compatible = "starfive,jh7110-pmu";

+            reg = <0x0 0x17030000 0x0 0x10000>;

+            interrupts = <111>;

+            #power-domain-cells = <1>;

+            status = "okay";

+        };

+

+        uart0: serial@10000000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x10000000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART0_CLK_CORE>,

+                 <&clkgen JH7110_UART0_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U0_DW_UART_APB>,

+                <&rstgen RSTN_U0_DW_UART_CORE>;

+            interrupts = <32>;

+            status = "disabled";

+        };

+

+        uart1: serial@10010000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x10010000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART1_CLK_CORE>,

+                 <&clkgen JH7110_UART1_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U1_DW_UART_APB>,

+                <&rstgen RSTN_U1_DW_UART_CORE>;

+            interrupts = <33>;

+            status = "disabled";

+        };

+

+        uart2: serial@10020000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x10020000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART2_CLK_CORE>,

+                 <&clkgen JH7110_UART2_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U2_DW_UART_APB>,

+                <&rstgen RSTN_U2_DW_UART_CORE>;

+            interrupts = <34>;

+            status = "disabled";

+        };

+

+        uart3: serial@12000000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x12000000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART3_CLK_CORE>,

+                 <&clkgen JH7110_UART3_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U3_DW_UART_APB>,

+                <&rstgen RSTN_U3_DW_UART_CORE>;

+            interrupts = <45>;

+            status = "disabled";

+        };

+

+        uart4: serial@12010000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x12010000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART4_CLK_CORE>,

+                 <&clkgen JH7110_UART4_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U4_DW_UART_APB>,

+                <&rstgen RSTN_U4_DW_UART_CORE>;

+            interrupts = <46>;

+            status = "disabled";

+        };

+

+        uart5: serial@12020000 {

+            compatible = "snps,dw-apb-uart";

+            reg = <0x0 0x12020000 0x0 0x10000>;

+            reg-io-width = <4>;

+            reg-shift = <2>;

+            clocks = <&clkgen JH7110_UART5_CLK_CORE>,

+                 <&clkgen JH7110_UART5_CLK_APB>;

+            clock-names = "baudclk", "apb_pclk";

+            resets = <&rstgen RSTN_U5_DW_UART_APB>,

+                <&rstgen RSTN_U5_DW_UART_CORE>;

+            interrupts = <47>;

+            status = "disabled";

+        };

+

+        dma: dma-controller@16050000 {

+            compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";

+            reg = <0x0 0x16050000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,

+                 <&clkgen JH7110_DMA1P_CLK_AHB>,

+                 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;

+            clock-names = "core-clk", "cfgr-clk", "stg_clk";

+            resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,

+                 <&rstgen RSTN_U0_DW_DMA1P_AHB>,

+                 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;

+            reset-names = "rst_axi", "rst_ahb", "rst_stg";

+            interrupts = <73>;

+            #dma-cells = <2>;

+            dma-channels = <4>;

+            snps,dma-masters = <1>;

+            snps,data-width = <3>;

+            snps,num-hs-if = <56>;

+            snps,block-size = <65536 65536 65536 65536>;

+            snps,priority = <0 1 2 3>;

+            snps,axi-max-burst-len = <16>;

+            status = "disabled";

+        };

+

+        gpio: gpio@13040000 {

+            compatible = "starfive,jh7110-sys-pinctrl";

+            reg = <0x0 0x13040000 0x0 0x10000>;

+            reg-names = "control";

+            clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;

+            resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;

+            interrupts = <86>;

+            interrupt-controller;

+            #gpio-cells = <2>;

+            ngpios = <64>;

+            status = "okay";

+        };

+

+        gpioa: gpio@17020000 {

+            compatible = "starfive,jh7110-aon-pinctrl";

+            reg = <0x0 0x17020000 0x0 0x10000>;

+            reg-names = "control";

+            resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;

+            interrupts = <85>;

+            interrupt-controller;

+            #gpio-cells = <2>;

+            ngpios = <4>;

+            status = "okay";

+        };

+

+        sfctemp: tmon@120e0000  {

+            compatible = "starfive,jh7110-temp";

+            reg = <0x0 0x120e0000 0x0 0x10000>;

+            interrupts = <81>;

+            clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,

+                 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;

+            clock-names = "sense", "bus";

+            resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,

+                 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;

+            reset-names = "sense", "bus";

+            #thermal-sensor-cells = <0>;

+            status = "disabled";

+        };

+

+        thermal-zones {

+            cpu-thermal {

+                polling-delay-passive = <250>;

+                polling-delay = <15000>;

+

+                thermal-sensors = <&sfctemp>;

+

+                trips {

+                    cpu_alert0: cpu_alert0 {

+                        /* milliCelsius */

+                        temperature = <75000>;

+                        hysteresis = <2000>;

+                        type = "passive";

+                    };

+

+                    cpu_crit: cpu_crit {

+                        /* milliCelsius */

+                        temperature = <90000>;

+                        hysteresis = <2000>;

+                        type = "critical";

+                    };

+                };

+

+                cooling-maps {

+                    map0 {

+                        trip = <&cpu_alert0>;

+                        cooling-device =

+                            <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

+                            <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

+                            <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

+                            <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

+                    };

+                };

+            };

+        };

+

+        trng: trng@1600C000 {

+            compatible = "starfive,jh7110-trng";

+            reg = <0x0 0x1600C000 0x0 0x4000>;

+            clocks = <&clkgen JH7110_SEC_HCLK>,

+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;

+            clock-names = "hclk", "ahb";

+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;

+            interrupts = <30>;

+            status = "disabled";

+        };

+

+        sec_dma: sec_dma@16008000 {

+            compatible = "arm,pl080", "arm,primecell";

+            arm,primecell-periphid = <0x00041080>;

+            reg = <0x0 0x16008000 0x0 0x4000>;

+            reg-names = "sec_dma";

+            interrupts = <29>;

+            clocks = <&clkgen JH7110_SEC_HCLK>,

+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;

+            clock-names = "sec_hclk","apb_pclk";

+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;

+            reset-names = "sec_hre";

+            lli-bus-interface-ahb1;

+            mem-bus-interface-ahb1;

+            memcpy-burst-size = <256>;

+            memcpy-bus-width = <32>;

+            #dma-cells = <2>;

+            status = "disabled";

+        };

+

+        crypto: crypto@16000000 {

+            compatible = "starfive,jh7110-sec";

+            reg = <0x0 0x16000000 0x0 0x4000>,

+                  <0x0 0x16008000 0x0 0x4000>;

+            reg-names = "secreg","secdma";

+            interrupts = <28>, <29>;

+            interrupt-names = "secirq", "dmairq";

+            clocks = <&clkgen JH7110_SEC_HCLK>,

+                 <&clkgen JH7110_SEC_MISCAHB_CLK>;

+            clock-names = "sec_hclk","sec_ahb";

+            resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;

+            reset-names = "sec_hre";

+            enable-side-channel-mitigation = "true";

+            enable-dma = "true";

+            dmas = <&sec_dma 1 2>,

+                   <&sec_dma 0 2>;

+            dma-names = "sec_m","sec_p";

+            status = "disabled";

+        };

+

+        i2c0: i2c@10030000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x10030000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C0_CLK_CORE>,

+                 <&clkgen JH7110_I2C0_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U0_DW_I2C_APB>;

+            interrupts = <35>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c1: i2c@10040000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x10040000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C1_CLK_CORE>,

+                 <&clkgen JH7110_I2C1_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U1_DW_I2C_APB>;

+            interrupts = <36>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c2: i2c@10050000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x10050000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C2_CLK_CORE>,

+                 <&clkgen JH7110_I2C2_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U2_DW_I2C_APB>;

+            interrupts = <37>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c3: i2c@12030000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x12030000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C3_CLK_CORE>,

+                 <&clkgen JH7110_I2C3_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U3_DW_I2C_APB>;

+            interrupts = <48>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c4: i2c@12040000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x12040000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C4_CLK_CORE>,

+                 <&clkgen JH7110_I2C4_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U4_DW_I2C_APB>;

+            interrupts = <49>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c5: i2c@12050000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x12050000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C5_CLK_CORE>,

+                 <&clkgen JH7110_I2C5_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U5_DW_I2C_APB>;

+            interrupts = <50>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        i2c6: i2c@12060000 {

+            compatible = "snps,designware-i2c";

+            reg = <0x0 0x12060000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_I2C6_CLK_CORE>,

+                 <&clkgen JH7110_I2C6_CLK_APB>;

+            clock-names = "ref", "pclk";

+            resets = <&rstgen RSTN_U6_DW_I2C_APB>;

+            interrupts = <51>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        /* unremovable emmc as mmcblk0 */

+        sdio0: sdio0@16010000 {

+            compatible = "starfive,jh7110-sdio";

+            reg = <0x0 0x16010000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,

+                 <&clkgen JH7110_SDIO0_CLK_SDCARD>;

+            clock-names = "biu","ciu";

+            resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;

+            reset-names = "reset";

+            interrupts = <74>;

+            fifo-depth = <32>;

+            fifo-watermark-aligned;

+            data-addr = <0>;

+            starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;

+            status = "disabled";

+        };

+

+        sdio1: sdio1@16020000 {

+            compatible = "starfive,jh7110-sdio";

+            reg = <0x0 0x16020000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,

+                 <&clkgen JH7110_SDIO1_CLK_SDCARD>;

+            clock-names = "biu","ciu";

+            resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;

+            reset-names = "reset";

+            interrupts = <75>;

+            fifo-depth = <32>;

+            fifo-watermark-aligned;

+            data-addr = <0>;

+            starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;

+            status = "disabled";

+        };

+

+        vin_sysctl: vin_sysctl@19800000 {

+            compatible = "starfive,jh7110-vin";

+            reg = <0x0 0x19800000 0x0 0x10000>,

+                <0x0 0x19810000 0x0 0x10000>,

+                <0x0 0x19820000 0x0 0x10000>,

+                <0x0 0x19840000 0x0 0x10000>,

+                <0x0 0x19870000 0x0 0x30000>,

+                <0x0 0x11840000 0x0 0x10000>,

+                <0x0 0x17030000 0x0 0x10000>,

+                <0x0 0x13020000 0x0 0x10000>;

+            reg-names = "csi2rx", "vclk", "vrst", "sctrl",

+                "isp", "trst", "pmu", "syscrg";

+            clocks = <&clkisp JH7110_DOM4_APB_FUNC>,

+                 <&clkisp JH7110_U0_VIN_PCLK>,

+                 <&clkisp JH7110_U0_VIN_SYS_CLK>,

+                 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,

+                 <&clkisp JH7110_DVP_INV>,

+                 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,

+                 <&clkisp JH7110_MIPI_RX0_PXL>,

+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,

+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,

+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,

+                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,

+                 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,

+                 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,

+                 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,

+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,

+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;

+            clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",

+                "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",

+                "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",

+                "clk_pixel_clk_if1", "clk_pixel_clk_if2",

+                "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",

+                "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",

+                "clk_ispcore_2x", "clk_isp_axi";

+            resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,

+                 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,

+                 <&rstgen RSTN_U0_VIN_N_PCLK>,

+                 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,

+                 <&rstgen RSTN_U0_VIN_P_AXIRD>,

+                 <&rstgen RSTN_U0_VIN_P_AXIWR>,

+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,

+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,

+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,

+                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,

+                 <&rstgen RSTN_U0_M31DPHY_HW>,

+                 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,

+                 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,

+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;

+            reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",

+                "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",

+                "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",

+                "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",

+                "rst_isp_top_n", "rst_isp_top_axi";

+            starfive,aon-syscon = <&aon_syscon 0x00>;

+            power-domains = <&pwrc JH7110_PD_ISP>;

+            /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */

+            interrupts = <92 87 88 89 90>;

+            status = "disabled";

+        };

+

+        jpu: jpu@11900000 {

+            compatible = "starfive,jpu";

+            reg = <0x0 0x13090000 0x0 0x300>;

+            interrupts = <14>;

+            clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,

+                 <&clkgen JH7110_CODAJ12_CLK_CORE>,

+                 <&clkgen JH7110_CODAJ12_CLK_APB>,

+                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;

+            clock-names = "axi_clk", "core_clk",

+                      "apb_clk", "noc_bus";

+            resets = <&rstgen RSTN_U0_CODAJ12_AXI>,

+                 <&rstgen RSTN_U0_CODAJ12_CORE>,

+                 <&rstgen RSTN_U0_CODAJ12_APB>;

+            reset-names = "rst_axi", "rst_core", "rst_apb";

+            power-domains = <&pwrc JH7110_PD_VDEC>;

+            status = "disabled";

+        };

+

+        vpu_dec: vpu_dec@130A0000 {

+            compatible = "starfive,vdec";

+            reg = <0x0 0x130A0000 0x0 0x10000>;

+            interrupts = <13>;

+            clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,

+                 <&clkgen JH7110_WAVE511_CLK_BPU>,

+                 <&clkgen JH7110_WAVE511_CLK_VCE>,

+                 <&clkgen JH7110_WAVE511_CLK_APB>,

+                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;

+            clock-names = "axi_clk", "bpu_clk", "vce_clk",

+                      "apb_clk", "noc_bus";

+            resets = <&rstgen RSTN_U0_WAVE511_AXI>,

+                <&rstgen RSTN_U0_WAVE511_BPU>,

+                <&rstgen RSTN_U0_WAVE511_VCE>,

+                <&rstgen RSTN_U0_WAVE511_APB>,

+                <&rstgen RSTN_U0_AXIMEM_128B_AXI>;

+            reset-names = "rst_axi", "rst_bpu", "rst_vce",

+                      "rst_apb", "rst_sram";

+            starfive,vdec_noc_ctrl;

+            power-domains = <&pwrc JH7110_PD_VDEC>;

+            status = "disabled";

+        };

+

+        vpu_enc: vpu_enc@130B0000 {

+            compatible = "starfive,venc";

+            reg = <0x0 0x130B0000 0x0 0x10000>;

+            interrupts = <15>;

+            clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,

+                 <&clkgen JH7110_WAVE420L_CLK_BPU>,

+                 <&clkgen JH7110_WAVE420L_CLK_VCE>,

+                 <&clkgen JH7110_WAVE420L_CLK_APB>,

+                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;

+            clock-names = "axi_clk", "bpu_clk", "vce_clk",

+                      "apb_clk", "noc_bus";

+            resets = <&rstgen RSTN_U0_WAVE420L_AXI>,

+                 <&rstgen RSTN_U0_WAVE420L_BPU>,

+                 <&rstgen RSTN_U0_WAVE420L_VCE>,

+                 <&rstgen RSTN_U0_WAVE420L_APB>,

+                 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;

+            reset-names = "rst_axi", "rst_bpu", "rst_vce",

+                      "rst_apb", "rst_sram";

+            starfive,venc_noc_ctrl;

+            power-domains = <&pwrc JH7110_PD_VENC>;

+            status = "disabled";

+        };

+

+        rstgen: reset-controller {

+            compatible = "starfive,jh7110-reset";

+            reg = <0x0 0x13020000 0x0 0x10000>,

+                <0x0 0x10230000 0x0 0x10000>,

+                <0x0 0x17000000 0x0 0x10000>,

+                <0x0 0x19810000 0x0 0x10000>,

+                <0x0 0x295C0000 0x0 0x10000>;

+            reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";

+            #reset-cells = <1>;

+            status = "okay";

+        };

+

+        stmmac_axi_setup: stmmac-axi-config {

+            snps,wr_osr_lmt = <0xf>;

+            snps,rd_osr_lmt = <0xf>;

+            snps,blen = <256 128 64 32 0 0 0>;

+        };

+

+        gmac0: ethernet@16030000 {

+            compatible = "starfive,dwmac","snps,dwmac-5.10a";

+            reg = <0x0 0x16030000 0x0 0x10000>;

+            clock-names = "gtx",

+                "tx",

+                "ptp_ref",

+                "stmmaceth",

+                "pclk",

+                "gtxc",

+                "rmii_rtx";

+            clocks = <&clkgen JH7110_GMAC0_GTXCLK>,

+                 <&clkgen JH7110_U0_GMAC5_CLK_TX>,

+                 <&clkgen JH7110_GMAC0_PTP>,

+                 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,

+                 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,

+                 <&clkgen JH7110_GMAC0_GTXC>,

+                 <&clkgen JH7110_GMAC0_RMII_RTX>;

+            resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,

+                 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;

+            reset-names = "ahb", "stmmaceth";

+            interrupts = <7>, <6>, <5> ;

+            interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

+            max-frame-size = <9000>;

+            phy-mode = "rgmii-id";

+            snps,multicast-filter-bins = <64>;

+            snps,perfect-filter-entries = <128>;

+            rx-fifo-depth = <2048>;

+            tx-fifo-depth = <2048>;

+            snps,fixed-burst;

+            snps,no-pbl-x8;

+            snps,force_thresh_dma_mode;

+            snps,axi-config = <&stmmac_axi_setup>;

+            snps,tso;

+            snps,en-tx-lpi-clockgating;

+            snps,en-lpi;

+            snps,write-requests = <4>;

+            snps,read-requests = <4>;

+            snps,burst-map = <0x7>;

+            snps,txpbl = <16>;

+            snps,rxpbl = <16>;

+            status = "disabled";

+        };

+

+        gmac1: ethernet@16040000 {

+            compatible = "starfive,dwmac","snps,dwmac-5.10a";

+            reg = <0x0 0x16040000 0x0 0x10000>;

+            clock-names = "gtx",

+                "tx",

+                "ptp_ref",

+                "stmmaceth",

+                "pclk",

+                "gtxc",

+                "rmii_rtx";

+            clocks = <&clkgen JH7110_GMAC1_GTXCLK>,

+                 <&clkgen JH7110_GMAC5_CLK_TX>,

+                 <&clkgen JH7110_GMAC5_CLK_PTP>,

+                 <&clkgen JH7110_GMAC5_CLK_AHB>,

+                 <&clkgen JH7110_GMAC5_CLK_AXI>,

+                 <&clkgen JH7110_GMAC1_GTXC>,

+                 <&clkgen JH7110_GMAC1_RMII_RTX>;

+            resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,

+                 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;

+            reset-names = "ahb", "stmmaceth";

+            interrupts = <78>, <77>, <76> ;

+            interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

+            max-frame-size = <9000>;

+            phy-mode = "rgmii-id";

+            snps,multicast-filter-bins = <64>;

+            snps,perfect-filter-entries = <128>;

+            rx-fifo-depth = <2048>;

+            tx-fifo-depth = <2048>;

+            snps,fixed-burst;

+            snps,no-pbl-x8;

+            snps,force_thresh_dma_mode;

+            snps,axi-config = <&stmmac_axi_setup>;

+            snps,tso;

+            snps,en-tx-lpi-clockgating;

+            snps,en-lpi;

+            snps,write-requests = <4>;

+            snps,read-requests = <4>;

+            snps,burst-map = <0x7>;

+            snps,txpbl = <16>;

+            snps,rxpbl = <16>;

+            status = "disabled";

+        };

+

+        gpu: gpu@18000000 {

+            compatible = "img-gpu";

+            reg = <0x0 0x18000000 0x0 0x100000>,

+                <0x0 0x130C000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_GPU_CORE>,

+                 <&clkgen JH7110_GPU_CLK_APB>,

+                 <&clkgen JH7110_GPU_RTC_TOGGLE>,

+                 <&clkgen JH7110_GPU_CORE_CLK>,

+                 <&clkgen JH7110_GPU_SYS_CLK>,

+                 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;

+            clock-names = "clk_bv", "clk_apb", "clk_rtc",

+                    "clk_core", "clk_sys", "clk_axi";

+            resets = <&rstgen RSTN_U0_IMG_GPU_APB>,

+                 <&rstgen RSTN_U0_IMG_GPU_DOMA>;

+            reset-names = "rst_apb", "rst_doma";

+            power-domains = <&pwrc JH7110_PD_GPUA>;

+            interrupts = <82>;

+            current-clock = <8000000>;

+            status = "disabled";

+        };

+

+        can0: can@130d0000 {

+            compatible = "starfive,jh7110-can", "ipms,can";

+            reg = <0x0 0x130d0000 0x0 0x1000>;

+            interrupts = <112>;

+            clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,

+                 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,

+                 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;

+            clock-names = "apb_clk", "core_clk", "timer_clk";

+            resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,

+                 <&rstgen RSTN_U0_CAN_CTRL_CORE>,

+                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;

+            reset-names = "rst_apb", "rst_core", "rst_timer";

+            frequency = <40000000>;

+            starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;

+            syscon,can_or_canfd = <0>;

+            status = "disabled";

+        };

+

+        can1: can@130e0000 {

+            compatible = "starfive,jh7110-can", "ipms,can";

+            reg = <0x0 0x130e0000 0x0 0x1000>;

+            interrupts = <113>;

+            clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,

+                 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,

+                 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;

+            clock-names = "apb_clk", "core_clk", "timer_clk";

+            resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,

+                 <&rstgen RSTN_U1_CAN_CTRL_CORE>,

+                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;

+            reset-names = "rst_apb", "rst_core", "rst_timer";

+            frequency = <40000000>;

+            starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;

+            syscon,can_or_canfd = <1>;

+            status = "disabled";

+        };

+

+        tdm: tdm@10090000 {

+            compatible = "starfive,jh7110-tdm";

+            reg = <0x0 0x10090000 0x0 0x1000>;

+            reg-names = "tdm";

+            clocks = <&clkgen JH7110_TDM_CLK_AHB>,

+                 <&clkgen JH7110_TDM_CLK_APB>,

+                 <&clkgen JH7110_TDM_INTERNAL>,

+                 <&tdm_ext>,

+                 <&clkgen JH7110_TDM_CLK_TDM>,

+                 <&clkgen JH7110_MCLK_INNER>;

+            clock-names = "clk_tdm_ahb", "clk_tdm_apb",

+                      "clk_tdm_internal", "clk_tdm_ext",

+                      "clk_tdm", "mclk_inner";

+            resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,

+                 <&rstgen RSTN_U0_TDM16SLOT_APB>,

+                 <&rstgen RSTN_U0_TDM16SLOT_TDM>;

+            reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";

+            dmas = <&dma 20 1>, <&dma 21 1>;

+            dma-names = "rx","tx";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        spdif0: spdif0@100a0000 {

+            compatible = "starfive,jh7110-spdif";

+            reg = <0x0 0x100a0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_SPDIF_CLK_APB>,

+                 <&clkgen JH7110_SPDIF_CLK_CORE>,

+                 <&clkgen JH7110_AUDIO_ROOT>,

+                 <&clkgen JH7110_MCLK_INNER>,

+                 <&mclk_ext>, <&clkgen JH7110_MCLK>;

+            clock-names = "spdif-apb", "spdif-core",

+                      "audroot", "mclk_inner",

+                      "mclk_ext", "mclk";

+            resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;

+            reset-names = "rst_apb";

+            interrupts = <84>;

+            interrupt-names = "tx";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        pwmdac: pwmdac@100b0000 {

+            compatible = "starfive,jh7110-pwmdac";

+            reg = <0x0 0x100b0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_APB0>,

+                 <&clkgen JH7110_PWMDAC_CLK_APB>,

+                 <&clkgen JH7110_PWMDAC_CLK_CORE>;

+            clock-names = "apb0", "pwmdac-apb", "pwmdac-core";

+            resets = <&rstgen RSTN_U0_PWMDAC_APB>;

+            reset-names = "rst-apb";

+            dmas = <&dma 22 1>;

+            dma-names = "tx";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        i2stx: i2stx@100c0000 {

+            compatible = "snps,designware-i2stx";

+            reg = <0x0 0x100c0000 0x0 0x1000>;

+            interrupt-names = "tx";

+            #sound-dai-cells = <0>;

+            dmas = <&dma 28 1>;

+            dma-names = "rx";

+            status = "disabled";

+        };

+

+        pdm: pdm@100d0000 {

+            compatible = "starfive,jh7110-pdm";

+            reg = <0x0 0x100d0000 0x0 0x1000>;

+            reg-names = "pdm";

+            clocks = <&clkgen JH7110_PDM_CLK_DMIC>,

+                 <&clkgen JH7110_PDM_CLK_APB>,

+                 <&clkgen JH7110_MCLK>,

+                 <&mclk_ext>;

+            clock-names = "pdm_mclk",

+                      "pdm_apb", "clk_mclk",

+                      "mclk_ext";

+            resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,

+                 <&rstgen RSTN_U0_PDM_4MIC_APB>;

+            reset-names = "pdm_dmic", "pdm_apb";

+            #sound-dai-cells = <0>;

+        };

+

+        i2srx_mst: i2srx_mst@100e0000 {

+            compatible = "starfive,jh7110-i2srx-master";

+            reg = <0x0 0x100e0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_APB0>,

+                 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,

+                 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,

+                 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,

+                 <&clkgen JH7110_I2SRX0_3CH_BCLK>,

+                 <&clkgen JH7110_I2SRX0_3CH_LRCK>,

+                 <&clkgen JH7110_MCLK>,

+                 <&mclk_ext>;

+            clock-names = "apb0", "i2srx_apb",

+                      "i2srx_bclk_mst", "i2srx_lrck_mst",

+                      "i2srx_bclk", "i2srx_lrck",

+                      "mclk", "mclk_ext";

+            resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,

+                 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;

+            reset-names = "rst_apb_rx", "rst_bclk_rx";

+            dmas = <&dma 24 1>;

+            dma-names = "rx";

+            starfive,sys-syscon = <&sys_syscon 0x18 0x34>;

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        i2srx_3ch: i2srx_3ch@100e0000 {

+            compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";

+            reg = <0x0 0x100e0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_APB0>,

+                 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,

+                 <&clkgen JH7110_AUDIO_ROOT>,

+                 <&clkgen JH7110_MCLK_INNER>,

+                 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,

+                 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,

+                 <&clkgen JH7110_I2SRX0_3CH_BCLK>,

+                 <&clkgen JH7110_I2SRX0_3CH_LRCK>,

+                 <&clkgen JH7110_MCLK>,

+                 <&mclk_ext>,

+                 <&i2srx_bclk_ext>,

+                 <&i2srx_lrck_ext>;

+            clock-names = "apb0", "3ch-apb",

+                      "audioroot", "mclk-inner",

+                      "bclk_mst", "3ch-lrck",

+                      "rx-bclk", "rx-lrck",

+                      "mclk", "mclk_ext",

+                      "bclk-ext", "lrck-ext";

+            resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,

+                 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;

+            dmas = <&dma 24 1>;

+            dma-names = "rx";

+            starfive,sys-syscon = <&sys_syscon 0x18 0x34>;

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        i2stx_4ch0: i2stx_4ch0@120b0000 {

+            compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";

+            reg = <0x0 0x120b0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_MCLK_INNER>,

+                 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,

+                 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,

+                 <&clkgen JH7110_MCLK>,

+                 <&clkgen JH7110_I2STX0_4CHBCLK>,

+                 <&clkgen JH7110_I2STX0_4CHLRCK>,

+                 <&clkgen JH7110_I2STX0_4CHCLK_APB>,

+                 <&mclk_ext>;

+            clock-names = "inner", "bclk-mst",

+                    "lrck-mst", "mclk",

+                    "bclk0", "lrck0",

+                    "i2s_apb", "mclk_ext";

+            resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,

+                 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;

+            reset-names = "rst_apb", "rst_bclk";

+            dmas = <&dma 47 1>;

+            dma-names = "tx";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        i2stx_4ch1: i2stx_4ch1@120c0000 {

+            compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";

+            reg = <0x0 0x120c0000 0x0 0x1000>;

+            clocks = <&clkgen JH7110_AUDIO_ROOT>,

+                 <&clkgen JH7110_MCLK_INNER>,

+                 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,

+                 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,

+                 <&clkgen JH7110_MCLK>,

+                 <&clkgen JH7110_I2STX1_4CHBCLK>,

+                 <&clkgen JH7110_I2STX1_4CHLRCK>,

+                 <&clkgen JH7110_MCLK_OUT>,

+                 <&clkgen JH7110_APB0>,

+                 <&clkgen JH7110_I2STX1_4CHCLK_APB>,

+                 <&mclk_ext>,

+                 <&i2stx_bclk_ext>,

+                 <&i2stx_lrck_ext>;

+            clock-names = "audroot", "mclk_inner", "bclk_mst",

+                      "lrck_mst", "mclk", "4chbclk",

+                      "4chlrck", "mclk_out",

+                      "apb0", "clk_apb",

+                      "mclk_ext", "bclk_ext", "lrck_ext";

+            resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,

+                 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;

+            dmas = <&dma 48 1>;

+            dma-names = "tx";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        ptc: pwm@120d0000 {

+            compatible = "starfive,jh7110-pwm";

+            reg = <0x0 0x120d0000 0x0 0x10000>;

+            reg-names = "control";

+            clocks = <&clkgen JH7110_PWM_CLK_APB>;

+            resets = <&rstgen RSTN_U0_PWM_8CH_APB>;

+            starfive,approx-freq = <2000000>;

+            #pwm-cells=<3>;

+            starfive,npwm = <8>;

+            status = "disabled";

+        };

+

+        spdif_transmitter: spdif_transmitter {

+            compatible = "linux,spdif-dit";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        pwmdac_codec: pwmdac-transmitter {

+            compatible = "starfive,jh7110-pwmdac-dit";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        dmic_codec: dmic_codec {

+            compatible = "dmic-codec";

+            #sound-dai-cells = <0>;

+            status = "disabled";

+        };

+

+        spi0: spi@10060000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x10060000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI0_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U0_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <38>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 14 1>, <&dma 15 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi1: spi@10070000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x10070000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI1_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U1_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <39>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 16 1>, <&dma 17 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi2: spi@10080000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x10080000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI2_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U2_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <40>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 18 1>, <&dma 19 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi3: spi@12070000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x12070000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI3_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U3_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <52>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 39 1>, <&dma 40 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi4: spi@12080000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x12080000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI4_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U4_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <53>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 41 1>, <&dma 42 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi5: spi@12090000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x12090000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI5_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U5_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <54>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 43 1>, <&dma 44 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        spi6: spi@120A0000 {

+            compatible = "arm,pl022", "arm,primecell";

+            reg = <0x0 0x120A0000 0x0 0x10000>;

+            clocks = <&clkgen JH7110_SPI6_CLK_APB>;

+            clock-names = "apb_pclk";

+            resets = <&rstgen RSTN_U6_SSP_SPI_APB>;

+            reset-names = "rst_apb";

+            interrupts = <55>;

+            /* shortage of dma channel that not be used */

+            /*dmas = <&dma 45 1>, <&dma 46 1>;*/

+            /*dma-names = "rx","tx";*/

+            arm,primecell-periphid = <0x00041022>;

+            num-cs = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+            status = "disabled";

+        };

+

+        pcie0: pcie@2B000000 {

+            compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";

+            #address-cells = <3>;

+            #size-cells = <2>;

+            #interrupt-cells = <1>;

+            reg = <0x0 0x2B000000 0x0 0x1000000

+                   0x9 0x40000000 0x0 0x10000000>;

+            reg-names = "reg", "config";

+            device_type = "pci";

+            starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;

+            starfive,phyctrl = <&phyctrl0 0x28 0x80>;

+            bus-range = <0x0 0xff>;

+            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,

+                 <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;

+            msi-parent = <&plic>;

+            interrupts = <56>;

+            interrupt-controller;

+            interrupt-names = "msi";

+            interrupt-parent = <&plic>;

+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;

+            interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,

+                    <0x0 0x0 0x0 0x2 &plic 0x2>,

+                    <0x0 0x0 0x0 0x3 &plic 0x3>,

+                    <0x0 0x0 0x0 0x4 &plic 0x4>;

+            resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,

+                 <&rstgen RSTN_U0_PLDA_PCIE_APB>;

+            reset-names = "rst_mst0", "rst_slv0", "rst_slv",

+                      "rst_brg", "rst_core", "rst_apb";

+            clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,

+                 <&clkgen JH7110_PCIE0_CLK_TL>,

+                 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,

+                 <&clkgen JH7110_PCIE0_CLK_APB>;

+            clock-names = "noc", "tl", "axi_mst0", "apb";

+            status = "disabled";

+        };

+

+        pcie1: pcie@2C000000 {

+            compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";

+            #address-cells = <3>;

+            #size-cells = <2>;

+            #interrupt-cells = <1>;

+            reg = <0x0 0x2C000000 0x0 0x1000000

+                   0x9 0xc0000000 0x0 0x10000000>;

+            reg-names = "reg", "config";

+            device_type = "pci";

+            starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;

+            starfive,phyctrl = <&phyctrl1 0x28 0x80>;

+            bus-range = <0x0 0xff>;

+            ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,

+                 <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;

+            msi-parent = <&plic>;

+            interrupts = <57>;

+            interrupt-controller;

+            interrupt-names = "msi";

+            interrupt-parent = <&plic>;

+            interrupt-map-mask = <0x0 0x0 0x0 0x7>;

+            interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,

+                    <0x0 0x0 0x0 0x2 &plic 0x2>,

+                    <0x0 0x0 0x0 0x3 &plic 0x3>,

+                    <0x0 0x0 0x0 0x4 &plic 0x4>;

+            resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,

+                 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,

+                 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,

+                 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,

+                 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,

+                 <&rstgen RSTN_U1_PLDA_PCIE_APB>;

+            reset-names = "rst_mst0", "rst_slv0", "rst_slv",

+                      "rst_brg", "rst_core", "rst_apb";

+            clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,

+                 <&clkgen JH7110_PCIE1_CLK_TL>,

+                 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,

+                 <&clkgen JH7110_PCIE1_CLK_APB>;

+            clock-names = "noc", "tl", "axi_mst0", "apb";

+            status = "disabled";

+        };

+

+        mailbox_contrl0: mailbox@0 {

+            compatible = "starfive,mail_box";

+            reg = <0x0 0x13060000 0x0 0x0001000>;

+            clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;

+            clock-names = "clk_apb";

+            resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;

+            reset-names = "mbx_rre";

+            interrupts = <26 27>;

+            #mbox-cells = <2>;

+            status = "disabled";

+        };

+

+        mailbox_client0: mailbox_client@0 {

+            compatible = "starfive,mailbox-test";

+            mbox-names = "rx", "tx";

+            mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;

+            status = "disabled";

+        };

+

+        display: display-subsystem {

+            compatible = "starfive,jh7110-display","verisilicon,display-subsystem";

+            ports = <&dc_out_dpi0>;

+            status = "disabled";

+        };

+

+        dssctrl: dssctrl@295B0000 {

+            compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";

+            reg = <0 0x295B0000 0 0x90>;

+        };

+

+        tda988x_pin: tda988x_pin {

+            compatible = "starfive,tda998x_rgb_pin";

+            status = "disabled";

+        };

+

+        rgb_output: rgb-output {

+            compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";

+            //verisilicon,dss-syscon = <&dssctrl>;

+            //verisilicon,mux-mask = <0x70 0x380>;

+            //verisilicon,mux-val = <0x40 0x280>;

+            status = "disabled";

+        };

+

+        dc8200: dc8200@29400000 {

+            compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";

+            verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon

+            reg = <0x0 0x29400000 0x0 0x100>,

+                  <0x0 0x29400800 0x0 0x2000>,

+                  <0x0 0x17030000 0x0 0x1000>;

+            interrupts = <95>;

+            status = "disabled";

+            clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,

+            <&clkgen JH7110_VOUT_SRC>,

+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,

+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,

+            <&clkvout JH7110_U0_DC8200_CLK_PIX0>,

+            <&clkvout JH7110_U0_DC8200_CLK_PIX1>,

+            <&clkvout JH7110_U0_DC8200_CLK_AXI>,

+            <&clkvout JH7110_U0_DC8200_CLK_CORE>,

+            <&clkvout JH7110_U0_DC8200_CLK_AHB>,

+            <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,

+            <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,

+            <&hdmitx0_pixelclk>,

+            <&clkvout JH7110_DC8200_PIX0>,

+            <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,

+            <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;

+            clock-names = "noc_disp","vout_src",

+               "top_vout_axi","top_vout_ahb",

+               "pix_clk","vout_pix1",

+               "axi_clk","core_clk","vout_ahb",

+               "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",

+               "dc8200_pix0_out","dc8200_pix1_out";

+            resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,

+                 <&rstgen RSTN_U0_DC8200_AXI>,

+                 <&rstgen RSTN_U0_DC8200_AHB>,

+                 <&rstgen RSTN_U0_DC8200_CORE>,

+                 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;

+            reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",

+                    "rst_noc_disp";

+        };

+

+        dsi_output: dsi-output {

+            compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";

+            status = "disabled";

+        };

+

+        mipi_dphy: mipi-dphy@295e0000{

+            compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";

+            reg = <0x0 0x295e0000 0x0 0x10000>;

+            clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;

+            clock-names = "dphy_txesc";

+            resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,

+                 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;

+            reset-names = "dphy_sys", "dphy_txbytehs";

+            #phy-cells = <0>;

+            status = "disabled";

+        };

+

+         mipi_dsi: mipi@295d0000 {

+            compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";

+            reg = <0x0 0x295d0000 0x0 0x10000>;

+            interrupts = <98>;

+            reg-names = "dsi";

+            clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,

+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,

+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,

+                 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;

+            clock-names = "sys", "apb", "txesc", "dpi";

+            resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,

+                 <&rstgen RSTN_U0_CDNS_DSITX_APB>,

+                 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,

+                 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,

+                 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,

+                 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;

+            reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",

+                    "dsi_sys", "dsi_txbytehs", "dsi_txesc";

+            phys = <&mipi_dphy>;

+            phy-names = "dphy";

+            status = "disabled";

+

+        };

+

+        hdmi: hdmi@29590000 {

+            compatible = "starfive,jh7110-hdmi","inno,hdmi";

+            reg = <0x0 0x29590000 0x0 0x4000>;

+            interrupts = <99>;

+            /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/

+            /*clocks = <&cru  PCLK_HDMI>;*/

+            /*clock-names = "pclk";*/

+            /*pinctrl-names = "default";*/

+            /*pinctrl-0 = <&hdmi_ctl>;*/

+            status = "disabled";

+            clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,

+                 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,

+                 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,

+                 <&hdmitx0_pixelclk>;

+            clock-names = "sysclk", "mclk","bclk","pclk";

+            resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;

+            reset-names = "hdmi_tx";

+            #sound-dai-cells = <0>;

+        };

+

+        sound0: snd-card0 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-AC108-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound1: snd-card1 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-HDMI-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound2: snd-card2 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-PDM-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound3: snd-card3 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound4: snd-card4 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-SPDIF-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound5: snd-card5 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-TDM-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        sound6: snd-card6 {

+            compatible = "simple-audio-card";

+            simple-audio-card,name = "Starfive-WM8960-Sound-Card";

+            #address-cells = <1>;

+            #size-cells = <0>;

+        };

+

+        co_process: e24@0 {

+            compatible = "starfive,e24";

+            reg = <0x0 0xc0110000 0x0 0x00001000>,

+                <0x0 0xc0111000 0x0 0x0001f000>;

+            reg-names = "ecmd", "espace";

+            clocks = <&clkgen JH7110_E2_RTC_CLK>,

+                 <&clkgen JH7110_E2_CLK_CORE>,

+                 <&clkgen JH7110_E2_CLK_DBG>;

+            clock-names = "clk_rtc", "clk_core", "clk_dbg";

+            resets = <&rstgen RSTN_U0_E24_CORE>;

+            reset-names = "e24_core";

+            starfive,stg-syscon = <&stg_syscon>;

+            interrupt-parent = <&plic>;

+            firmware-name = "e24_elf";

+            irq-mode = <1>;

+            mbox-names = "tx", "rx";

+            mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;

+            #address-cells = <1>;

+            #size-cells = <1>;

+            ranges = <0xc0000000 0x0 0xc0000000 0x200000>;

+            status = "disabled";

+            dsp@0 {};

+        };

+

+        xrp: xrp@0 {

+            compatible = "cdns,xrp";

+            reg = <0x0  0x10230000 0x0 0x00010000

+                0x0  0x10240000 0x0 0x00010000>;

+            memory-region = <&xrp_reserved>;

+            clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;

+            clock-names = "core_clk";

+            resets = <&rstgen RSTN_U0_HIFI4_CORE>,

+                 <&rstgen RSTN_U0_HIFI4_AXI>;

+            reset-names = "rst_core","rst_axi";

+            starfive,stg-syscon = <&stg_syscon>;

+            firmware-name = "hifi4_elf";

+            #address-cells = <1>;

+            #size-cells = <1>;

+            ranges = <0x40000000 0x0 0x20000000 0x040000

+                0xf0000000 0x0 0xf0000000 0x03000000>;

+            status = "disabled";

+            dsp@0 {

+            };

+        };

+

+        starfive_cpufreq: starfive,jh7110-cpufreq {

+            compatible = "starfive,jh7110-cpufreq";

+            clocks = <&clkgen JH7110_CPU_CORE>;

+            clock-names = "cpu_clk";

+        };

+    };

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi
new file mode 100644
index 000000000000..ed2883b5d02f
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFivePwmDac.dtsi
@@ -0,0 +1,26 @@
+/** @file

+  Device tree defination all JH7110 pwmdac audio for StarFive VisionFive 2 platform

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+&sound3 {

+    simple-audio-card,dai-link@0 {

+        reg = <0>;

+        format = "left_j";

+        bitclock-master = <&sndcpu0>;

+        frame-master = <&sndcpu0>;

+        status = "okay";

+

+        sndcpu0: cpu {

+            sound-dai = <&pwmdac>;

+        };

+

+        codec {

+            sound-dai = <&pwmdac_codec>;

+        };

+    };

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts
new file mode 100644
index 000000000000..6649c5b9dc00
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dts
@@ -0,0 +1,211 @@
+/** @file

+  Device tree defination for StarFive VisionFive 2 platform

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+/dts-v1/;

+#include "StarFiveVisionFive2.dtsi"

+#include "StarFiveHdmi.dtsi"

+

+/ {

+    model = "StarFive VisionFive V2";

+    compatible = "starfive,visionfive-v2", "starfive,jh7110";

+

+    gpio-restart {

+        compatible = "gpio-restart";

+        gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;

+        priority = <160>;

+    };

+

+};

+

+&gpio {

+    uart0_pins: uart0-pins {

+        uart0-pins-tx {

+            starfive,pins = <PAD_GPIO5>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_UART0_SOUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+

+        uart0-pins-rx {

+            starfive,pins = <PAD_GPIO6>;

+            starfive,pinmux = <PAD_GPIO6_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | GPIO_PU(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+            starfive,pin-gpio-din =  <GPI_UART0_SIN>;

+        };

+    };

+

+    i2c2_pins: i2c2-pins {

+        i2c2-pins-scl {

+            starfive,pins = <PAD_GPIO3>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C2_IC_CLK_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C2_IC_CLK_IN_A>;

+        };

+

+        i2c2-pins-sda {

+            starfive,pins = <PAD_GPIO2>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C2_IC_DATA_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C2_IC_DATA_IN_A>;

+        };

+    };

+

+    mmc0_pins: mmc0-pins {

+         mmc0-pins-rest {

+            starfive,pins = <PAD_GPIO62>;

+            starfive,pinmux = <PAD_GPIO62_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_SDIO0_RST_N>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    sdcard1_pins: sdcard1-pins {

+        sdcard1-pins0 {

+            starfive,pins = <PAD_GPIO10>;

+            starfive,pinmux = <PAD_GPIO10_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+

+        sdcard1-pins1 {

+            starfive,pins = <PAD_GPIO9>;

+            starfive,pinmux = <PAD_GPIO9_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;

+            starfive,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;

+            starfive,pin-gpio-din =  <GPI_SDIO1_CCMD_IN>;

+        };

+

+        sdcard1-pins2 {

+            starfive,pins = <PAD_GPIO11>;

+            starfive,pinmux = <PAD_GPIO11_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;

+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;

+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_0>;

+        };

+

+        sdcard1-pins3 {

+            starfive,pins = <PAD_GPIO12>;

+            starfive,pinmux = <PAD_GPIO12_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;

+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;

+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_1>;

+        };

+

+        sdcard1-pins4 {

+            starfive,pins = <PAD_GPIO7>;

+            starfive,pinmux = <PAD_GPIO7_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;

+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;

+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_2>;

+        };

+

+        sdcard1-pins5 {

+            starfive,pins = <PAD_GPIO8>;

+            starfive,pinmux = <PAD_GPIO8_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)) | GPIO_DS(3))>;

+            starfive,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;

+            starfive,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;

+            starfive,pin-gpio-din =  <GPI_SDIO1_CDATA_IN_3>;

+        };

+    };

+

+    inno_hdmi_pins: inno_hdmi-pins {

+        inno_hdmi-scl {

+            starfive,pins = <PAD_GPIO0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SCL_OUT>;

+            starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SCL_OEN>;

+            starfive,pin-gpio-din =  <GPI_HDMI0_DDC_SCL_IN>;

+        };

+

+        inno_hdmi-sda {

+            starfive,pins = <PAD_GPIO1>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_HDMI0_DDC_SDA_OUT>;

+            starfive,pin-gpio-doen = <OEN_HDMI0_DDC_SDA_OEN>;

+            starfive,pin-gpio-din =  <GPI_HDMI0_DDC_SDA_IN>;

+        };

+        inno_hdmi-cec-pins {

+            starfive,pins = <PAD_GPIO14>;

+            //starfive,pinmux = <PAD_GPIO14_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-doen = <OEN_HDMI0_CEC_SDA_OEN>;

+            starfive,pin-gpio-dout = <GPO_HDMI0_CEC_SDA_OUT>;

+            starfive,pin-gpio-din =  <GPI_HDMI0_CEC_SDA_IN>;

+        };

+        inno_hdmi-hpd-pins {

+            starfive,pins = <PAD_GPIO15>;

+            //starfive,pinmux = <PAD_GPIO15_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+            starfive,pin-gpio-din =  <GPI_HDMI0_HPD>;

+        };

+    };

+

+    mclk_ext_pins: mclk_ext_pins {

+        mclk_ext_pins {

+            starfive,pins = <PAD_GPIO4>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-din = <GPI_CRG0_EXT_MCLK>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+};

+

+&uart0 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&uart0_pins>;

+    status = "okay";

+};

+

+&i2c2 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2c2_pins>;

+    status = "okay";

+};

+

+&sdio0 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&mmc0_pins>;

+    status = "okay";

+};

+

+&sdio1 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&sdcard1_pins>;

+    //cd-gpios = <&gpio 41 0>;

+    status = "okay";

+};

+

+&hdmi {

+    status = "okay";

+    pinctrl-names = "default";

+    pinctrl-0 = <&inno_hdmi_pins>;

+};

+

+&i2stx_4ch0 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&mclk_ext_pins>;

+    status = "okay";

+};

+

+&cpu1 {

+    cpu-supply = <&cpu_vdd>;

+    clocks = <&clkgen JH7110_CPU_CORE>;

+    clock-names = "cpu";

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi
new file mode 100755
index 000000000000..f56307568874
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/StarFiveVisionFive2.dtsi
@@ -0,0 +1,838 @@
+/** @file

+  Device tree defination for StarFive VisionFive 2 platform

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+/dts-v1/;

+#include "StarFiveJH7110.dtsi"

+#include "StarFivePwmDac.dtsi"

+#include "JH7110PinCtrl.h"

+#include "Gpio.h"

+#include "Led.h"

+

+/ {

+    model = "StarFive VisionFive V2";

+    compatible = "starfive,visionfive-v2", "starfive,jh7110";

+

+    aliases {

+        spi0 = &qspi;

+        gpio0 = &gpio;

+        ethernet0 = &gmac0;

+        ethernet1 = &gmac1;

+        mmc0 = &sdio0;

+        mmc1 = &sdio1;

+        serial0 = &uart0;

+        serial3 = &uart3;

+        i2c0 = &i2c0;

+        i2c1 = &i2c1;

+        i2c2 = &i2c2;

+        i2c3 = &i2c3;

+        i2c4 = &i2c4;

+        i2c5 = &i2c5;

+        i2c6 = &i2c6;

+    };

+

+    chosen {

+        linux,initrd-start = <0x0 0x46100000>;

+        linux,initrd-end = <0x0 0x4c000000>;

+        stdout-path = "serial0:115200";

+        #bootargs = "debug console=ttyS0 rootwait";

+    };

+

+    cpus {

+        timebase-frequency = <4000000>;

+    };

+

+    memory@40000000 {

+        device_type = "memory";

+        reg = <0x0 0x40000000 0x1 0x0>;

+    };

+

+    reserved-memory {

+        #address-cells = <2>;

+        #size-cells = <2>;

+        ranges;

+

+        linux,cma {

+            compatible = "shared-dma-pool";

+            reusable;

+            size = <0x0 0x20000000>;

+            alignment = <0x0 0x1000>;

+            alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;

+            linux,cma-default;

+        };

+

+        e24_mem: e24@c0000000 {

+            no-map;

+            reg = <0x0 0xc0110000 0x0 0xf0000>;

+        };

+

+        xrp_reserved: xrpbuffer@f0000000 {

+            reg = <0x0 0xf0000000 0x0 0x01ffffff

+                0x0 0xf2000000 0x0 0x00001000

+                0x0 0xf2001000 0x0 0x00fff000

+                0x0 0xf3000000 0x0 0x00001000>;

+        };

+

+    };

+

+    leds {

+        compatible = "gpio-leds";

+

+        led-ack {

+            gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;

+            color = <LED_COLOR_ID_GREEN>;

+            function = LED_FUNCTION_HEARTBEAT;

+            linux,default-trigger = "heartbeat";

+            label = "ack";

+        };

+    };

+};

+

+&gpio {

+    i2c0_pins: i2c0-pins {

+        i2c0-pins-scl {

+            starfive,pins = <PAD_GPIO57>;

+            starfive,pinmux = <PAD_GPIO57_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C0_IC_CLK_IN_A>;

+        };

+

+        i2c0-pins-sda {

+            starfive,pins = <PAD_GPIO58>;

+            starfive,pinmux = <PAD_GPIO58_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C0_IC_DATA_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C0_IC_DATA_IN_A>;

+        };

+    };

+

+    i2c5_pins: i2c5-pins {

+        i2c5-pins-scl {

+            starfive,pins = <PAD_GPIO19>;

+            starfive,pinmux = <PAD_GPIO19_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C5_IC_CLK_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C5_IC_CLK_IN_A>;

+        };

+

+        i2c5-pins-sda {

+            starfive,pins = <PAD_GPIO20>;

+            starfive,pinmux = <PAD_GPIO20_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C5_IC_DATA_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C5_IC_DATA_IN_A>;

+        };

+    };

+

+    i2c6_pins: i2c6-pins {

+        i2c6-pins-scl {

+            starfive,pins = <PAD_GPIO16>;

+            starfive,pinmux = <PAD_GPIO16_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C6_IC_CLK_IN_A>;

+        };

+

+        i2c6-pins-sda {

+            starfive,pins = <PAD_GPIO17>;

+            starfive,pinmux = <PAD_GPIO17_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_I2C6_IC_DATA_OE>;

+            starfive,pin-gpio-din =  <GPI_I2C6_IC_DATA_IN_A>;

+        };

+    };

+

+    csi_pins: csi-pins {

+        csi-pins-pwdn {

+            starfive,pins = <PAD_GPIO18>;

+            starfive,pinmux = <PAD_GPIO18_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_HIGH>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pwmdac0_pins: pwmdac0-pins {

+        pwmdac0-pins-left {

+            starfive,pins = <PAD_GPIO33>;

+            starfive,pinmux = <PAD_GPIO33_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+

+        pwmdac0-pins-right {

+            starfive,pins = <PAD_GPIO34>;

+            starfive,pinmux = <PAD_GPIO34_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1) | (GPIO_PU(1)))>;

+            starfive,pin-gpio-dout = <GPO_PWMDAC0_RIGHT_OUTPUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pwm_pins: pwm-pins {

+        pwm_ch0-pins {

+            starfive,pins = <PAD_GPIO46>;

+            starfive,pinmux = <PAD_GPIO46_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_PTC0_PWM_0>;

+            starfive,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;

+        };

+

+        pwm_ch1-pins {

+            starfive,pins = <PAD_GPIO59>;

+            starfive,pinmux = <PAD_GPIO59_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_PTC0_PWM_1>;

+            starfive,pin-gpio-doen = <OEN_PTC0_PWM_1_OE_N>;

+        };

+    };

+

+    ssp0_pins: ssp0-pins {

+        ssp0-pins_tx {

+            starfive,pins = <PAD_GPIO52>;

+            starfive,pinmux = <PAD_GPIO52_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_SPI0_SSPTXD>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+

+        ssp0-pins_rx {

+            starfive,pins = <PAD_GPIO53>;

+            starfive,pinmux = <PAD_GPIO53_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+            starfive,pin-gpio-din =  <GPI_SPI0_SSPRXD>;

+        };

+

+        ssp0-pins_clk {

+            starfive,pins = <PAD_GPIO48>;

+            starfive,pinmux = <PAD_GPIO48_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+

+        ssp0-pins_cs {

+            starfive,pins = <PAD_GPIO49>;

+            starfive,pinmux = <PAD_GPIO49_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pcie0_perst_default: pcie0_perst_default {

+        perst-pins {

+            starfive,pins = <PAD_GPIO26>;

+            starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_HIGH>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pcie0_perst_active: pcie0_perst_active {

+        perst-pins {

+            starfive,pins = <PAD_GPIO26>;

+            starfive,pinmux = <PAD_GPIO26_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pcie0_wake_default: pcie0_wake_default {

+        wake-pins {

+            starfive,pins = <PAD_GPIO32>;

+            starfive,pinmux = <PAD_GPIO32_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+

+    pcie0_clkreq_default: pcie0_clkreq_default {

+        clkreq-pins {

+            starfive,pins = <PAD_GPIO27>;

+            starfive,pinmux = <PAD_GPIO27_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+

+    pcie1_perst_default: pcie1_perst_default {

+        perst-pins {

+            starfive,pins = <PAD_GPIO28>;

+            starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_HIGH>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pcie1_perst_active: pcie1_perst_active {

+        perst-pins {

+            starfive,pins = <PAD_GPIO28>;

+            starfive,pinmux = <PAD_GPIO28_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_LOW>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    pcie1_wake_default: pcie1_wake_default {

+        wake-pins {

+            starfive,pins = <PAD_GPIO21>;

+            starfive,pinmux = <PAD_GPIO21_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+

+    pcie1_clkreq_default: pcie1_clkreq_default {

+        clkreq-pins {

+            starfive,pins = <PAD_GPIO29>;

+            starfive,pinmux = <PAD_GPIO29_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+

+    usb_pins: usb-pins {

+        drive-vbus-pin {

+            starfive,pins = <PAD_GPIO25>;

+            starfive,pinmux = <PAD_GPIO25_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_USB0_DRIVE_VBUS_IO>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+

+    i2srx_pins: i2srx-pins {

+        i2srx-pins0 {

+            starfive,pins = <PAD_GPIO61>;

+            starfive,pinmux = <PAD_GPIO61_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+            starfive,pin-gpio-din =  <GPI_I2SRX0_EXT_SDIN0>;

+        };

+    };

+

+    i2s_clk_pins: i2s-clk0 {

+        i2s-clk0_bclk {

+            starfive,pins = <PAD_GPIO38>;

+            starfive,pinmux = <PAD_GPIO38_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-din = <GPI_I2STX0_BCLK_SLV GPI_I2SRX0_BCLK_SLV>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+

+        i2s-clk0_lrclk {

+            starfive,pins = <PAD_GPIO63>;

+            starfive,pinmux = <PAD_GPIO63_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-din = <GPI_I2STX0_LRCK_SLV GPI_I2SRX0_LRCK_SLV>;

+            starfive,pin-gpio-doen = <OEN_HIGH>;

+        };

+    };

+

+    i2stx_pins: i2stx-pins {

+        i2stx-pins0 {

+            starfive,pins = <PAD_GPIO44>;

+            starfive,pinmux = <PAD_GPIO44_FUNC_SEL 0>;

+            starfive,pin-ioconfig = <IO(GPIO_IE(1))>;

+            starfive,pin-gpio-dout = <GPO_I2STX_4CH1_SDO0>;

+            starfive,pin-gpio-doen = <OEN_LOW>;

+        };

+    };

+};

+

+&uart0 {

+    status = "okay";

+};

+

+&dma {

+    status = "okay";

+};

+

+&trng {

+    status = "okay";

+};

+

+&crypto {

+    status = "okay";

+};

+

+&sec_dma {

+    status = "okay";

+};

+

+&i2c0 {

+    clock-frequency = <100000>;

+    i2c-sda-hold-time-ns = <300>;

+    i2c-sda-falling-time-ns = <510>;

+    i2c-scl-falling-time-ns = <510>;

+    auto_calc_scl_lhcnt;

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2c0_pins>;

+    status = "okay";

+};

+

+&i2c2 {

+    clock-frequency = <100000>;

+    i2c-sda-hold-time-ns = <300>;

+    i2c-sda-falling-time-ns = <510>;

+    i2c-scl-falling-time-ns = <510>;

+    auto_calc_scl_lhcnt;

+    status = "okay";

+

+    seeed_plane_i2c@45 {

+        compatible = "seeed_panel";

+        reg = <0x45>;

+

+        port {

+            panel_out0: endpoint {

+                remote-endpoint = <&dsi0_output>;

+            };

+        };

+    };

+

+    tinker_ft5406: tinker_ft5406@38 {

+        compatible = "tinker_ft5406";

+        reg = <0x38>;

+    };

+

+    panel_radxa@19 {

+        compatible ="starfive_jadard";

+        reg = <0x19>;

+        reset-gpio = <&gpio 23 0>;

+        enable-gpio = <&gpio 22 0>;

+

+        port {

+            panel_out1: endpoint {

+                remote-endpoint = <&dsi1_output>;

+                };

+        };

+    };

+

+    touchscreen@14 {

+        compatible = "goodix,gt911";

+        reg = <0x14>;

+        irq-gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;

+        reset-gpios = <&gpio 31 GPIO_ACTIVE_HIGH>;

+    };

+};

+

+&i2c5 {

+    clock-frequency = <100000>;

+    i2c-sda-hold-time-ns = <300>;

+    i2c-sda-falling-time-ns = <510>;

+    i2c-scl-falling-time-ns = <510>;

+    auto_calc_scl_lhcnt;

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2c5_pins>;

+    status = "okay";

+

+    eeprom@50 {

+        compatible = "atmel,24c04";

+        reg = <0x50>;

+        pagesize = <16>;

+    };

+

+    pmic: axp15060_reg@36 {

+        compatible = "stf,axp15060-regulator";

+        reg = <0x36>;

+

+        regulators {

+            mipi_0p9: ALDO1 {

+                regulator-boot-on;

+                regulator-compatible = "mipi_0p9";

+                regulator-name = "mipi_0p9";

+                regulator-min-microvolt = <900000>;

+                regulator-max-microvolt = <900000>;

+            };

+            hdmi_0p9: ALDO5 {

+                regulator-boot-on;

+                regulator-compatible = "hdmi_0p9";

+                regulator-name = "hdmi_0p9";

+                regulator-min-microvolt = <900000>;

+                regulator-max-microvolt = <900000>;

+            };

+            hdmi_1p8: ALDO3 {

+                regulator-boot-on;

+                regulator-compatible = "hdmi_1p8";

+                regulator-name = "hdmi_1p8";

+                regulator-min-microvolt = <1800000>;

+                regulator-max-microvolt = <1800000>;

+            };

+            cpu_vdd: DCDC2 {

+                regulator-boot-on;

+                regulator-always-on;

+                regulator-compatible = "cpu_vdd";

+                regulator-name = "cpu_vdd";

+                regulator-min-microvolt = <500000>;

+                regulator-max-microvolt = <1540000>;

+            };

+        };

+    };

+};

+

+&i2c6 {

+    clock-frequency = <100000>;

+    i2c-sda-hold-time-ns = <300>;

+    i2c-sda-falling-time-ns = <510>;

+    i2c-scl-falling-time-ns = <510>;

+    auto_calc_scl_lhcnt;

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2c6_pins>;

+    status = "okay";

+

+    imx219: imx219@10 {

+        compatible = "sony,imx219";

+        reg = <0x10>;

+        clocks = <&clk_ext_camera>;

+        clock-names = "xclk";

+        //reset-gpio = <&gpio 18 0>;

+        //DOVDD-supply = <&v2v8>;

+        pinctrl-names = "default";

+        pinctrl-0 = <&csi_pins>;

+        rotation = <0>;

+        orientation = <1>; //CAMERA_ORIENTATION_BACK

+

+        port {

+            /* CSI2 bus endpoint */

+            imx219_to_csi2rx0: endpoint {

+                remote-endpoint = <&csi2rx0_from_imx219>;

+                bus-type = <4>;      /* MIPI CSI-2 D-PHY */

+                clock-lanes = <4>;

+                data-lanes = <0 1>;

+                lane-polarities = <0 0 0>;

+                link-frequencies = /bits/ 64 <456000000>;

+            };

+        };

+    };

+};

+

+&sdio0 {

+    max-frequency = <100000000>;

+    card-detect-delay = <300>;

+    bus-width = <8>;

+    cap-mmc-highspeed;

+    mmc-ddr-1_8v;

+    mmc-hs200-1_8v;

+    non-removable;

+    cap-mmc-hw-reset;

+    post-power-on-delay-ms = <200>;

+    status = "okay";

+};

+

+&sdio1 {

+    max-frequency = <100000000>;

+    card-detect-delay = <300>;

+    bus-width = <4>;

+    no-sdio;

+    no-mmc;

+    broken-cd;

+    cap-sd-highspeed;

+    post-power-on-delay-ms = <200>;

+    status = "okay";

+};

+

+&vin_sysctl {

+    /* when use dvp open this pinctrl*/

+    status = "okay";

+

+    ports {

+        #address-cells = <1>;

+        #size-cells = <0>;

+

+        port@1 {

+            reg = <1>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+

+            /* CSI2 bus endpoint */

+            csi2rx0_from_imx219: endpoint@0 {

+                reg = <0>;

+                remote-endpoint = <&imx219_to_csi2rx0>;

+                bus-type = <4>;      /* MIPI CSI-2 D-PHY */

+                clock-lanes = <4>;

+                data-lanes = <0 1>;

+                lane-polarities = <0 0 0>;

+                status = "okay";

+            };

+        };

+    };

+};

+

+&sfctemp {

+    status = "okay";

+};

+

+&jpu {

+    status = "okay";

+};

+

+&vpu_dec {

+    status = "okay";

+};

+

+&vpu_enc {

+    status = "okay";

+};

+

+&gmac0 {

+    status = "okay";

+    #address-cells = <1>;

+    #size-cells = <0>;

+    phy0: ethernet-phy@0 {

+        rxc_dly_en = <1>;

+        tx_delay_sel_fe = <5>;

+        tx_delay_sel = <0xa>;

+        tx_inverted_10 = <0x1>;

+        tx_inverted_100 = <0x1>;

+        tx_inverted_1000 = <0x1>;

+    };

+};

+

+&gmac1 {

+    #address-cells = <1>;

+    #size-cells = <0>;

+    status = "okay";

+    phy1: ethernet-phy@1 {

+        tx_delay_sel_fe = <5>;

+        tx_delay_sel = <0>;

+        rxc_dly_en = <0>;

+        tx_inverted_10 = <0x1>;

+        tx_inverted_100 = <0x1>;

+        tx_inverted_1000 = <0x0>;

+    };

+};

+

+&gpu {

+    status = "okay";

+};

+

+&pwmdac {

+    pinctrl-names = "default";

+    pinctrl-0 = <&pwmdac0_pins>;

+    status = "okay";

+};

+

+&i2srx_3ch {

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2s_clk_pins &i2srx_pins>;

+    status = "disabled";

+};

+

+&i2stx_4ch1 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&i2stx_pins>;

+    status = "disabled";

+};

+

+&pwmdac_codec {

+    status = "okay";

+};

+

+&spi0 {

+    pinctrl-names = "default";

+    pinctrl-0 = <&ssp0_pins>;

+    status = "okay";

+

+    spi_dev0: spi@0 {

+        compatible = "rohm,dh2228fv";

+        pl022,com-mode = <1>;

+        spi-max-frequency = <10000000>;

+        reg = <0>;

+        status = "okay";

+    };

+};

+

+&pcie0 {

+    pinctrl-names = "default", "perst-default", "perst-active";

+    pinctrl-0 = <&pcie0_wake_default>,

+            <&pcie0_clkreq_default>;

+    pinctrl-1 = <&pcie0_perst_default>;

+    pinctrl-2 = <&pcie0_perst_active>;

+    status = "okay";

+};

+

+&pcie1 {

+    pinctrl-names = "default", "perst-default", "perst-active";

+    pinctrl-0 = <&pcie1_wake_default>,

+            <&pcie1_clkreq_default>;

+    pinctrl-1 = <&pcie1_perst_default>;

+    pinctrl-2 = <&pcie1_perst_active>;

+    status = "okay";

+};

+

+&mailbox_contrl0 {

+    status = "okay";

+};

+

+&mailbox_client0 {

+    status = "okay";

+};

+

+&display {

+    status = "okay";

+};

+

+&hdmi {

+    status = "okay";

+

+    hdmi_in: port {

+        #address-cells = <1>;

+        #size-cells = <0>;

+        hdmi_in_lcdc: endpoint@0 {

+            reg = <0>;

+            remote-endpoint = <&dc_out_dpi1>;

+        };

+    };

+};

+

+&dc8200 {

+    status = "okay";

+

+    dc_out: port {

+        #address-cells = <1>;

+        #size-cells = <0>;

+        dc_out_dpi0: endpoint@0 {

+            reg = <0>;

+            remote-endpoint = <&hdmi_input0>;

+        };

+        dc_out_dpi1: endpoint@1 {

+            reg = <1>;

+            remote-endpoint = <&hdmi_in_lcdc>;

+        };

+

+        dc_out_dpi2: endpoint@2 {

+            reg = <2>;

+            remote-endpoint = <&mipi_in>;

+        };

+    };

+};

+

+&rgb_output {

+    status = "disabled";

+

+    ports {

+        #address-cells = <1>;

+        #size-cells = <0>;

+        port@0 {

+            #address-cells = <1>;

+            #size-cells = <0>;

+            reg = <0>;

+            hdmi_input0:endpoint@0 {

+                reg = <0>;

+                remote-endpoint = <&dc_out_dpi0>;

+            };

+        };

+    };

+};

+

+&dsi_output {

+    status = "okay";

+

+    ports {

+        #address-cells = <1>;

+        #size-cells = <0>;

+

+        port@0 {

+            reg = <0>;

+            mipi_in: endpoint {

+                remote-endpoint = <&dc_out_dpi2>;

+            };

+        };

+

+        port@1 {

+            reg = <1>;

+            sf_dpi_output: endpoint {

+                remote-endpoint = <&dsi_in_port>;

+            };

+        };

+    };

+};

+

+&mipi_dsi {

+    status = "okay";

+

+    ports {

+        #address-cells = <1>;

+        #size-cells = <0>;

+

+        port@0 {

+            reg = <0>;

+            #address-cells = <1>;

+            #size-cells = <0>;

+

+            dsi0_output: endpoint@0 {

+                reg = <0>;

+                remote-endpoint = <&panel_out0>;

+            };

+

+            dsi1_output: endpoint@1 {

+                reg = <1>;

+                remote-endpoint = <&panel_out1>;

+            };

+        };

+

+        port@1{

+            reg = <1>;

+            dsi_in_port: endpoint {

+                remote-endpoint = <&sf_dpi_output>;

+            };

+        };

+

+    };

+};

+

+&mipi_dphy {

+    status = "okay";

+};

+

+&co_process {

+    status = "okay";

+};

+

+&usbdrd30 {

+    clocks = <&clkgen JH7110_USB_125M>,

+         <&clkgen JH7110_USB0_CLK_APP_125>,

+         <&clkgen JH7110_USB0_CLK_LPM>,

+         <&clkgen JH7110_USB0_CLK_STB>,

+         <&clkgen JH7110_USB0_CLK_USB_APB>,

+         <&clkgen JH7110_USB0_CLK_AXI>,

+         <&clkgen JH7110_USB0_CLK_UTMI_APB>;

+    clock-names = "125m","app","lpm","stb","apb","axi","utmi";

+    resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,

+         <&rstgen RSTN_U0_CDN_USB_APB>,

+         <&rstgen RSTN_U0_CDN_USB_AXI>,

+         <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;

+    reset-names = "pwrup","apb","axi","utmi";

+    starfive,usb2-only;

+    dr_mode = "peripheral"; /*host or peripheral*/

+    status = "okay";

+};

+

+&xrp {

+    status = "okay";

+};

+

+&ptc {

+    pinctrl-names = "default";

+    pinctrl-0 = <&pwm_pins>;

+    status = "okay";

+};

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h b/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h
new file mode 100644
index 000000000000..48af62f5722e
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/Thermal.h
@@ -0,0 +1,16 @@
+/** @file

+  This header provide all the thermal bindings

+

+  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __DT_BINDINGS_THERMAL_H__

+#define __DT_BINDINGS_THERMAL_H__

+

+/* On cooling devices upper and lower limits */

+#define THERMAL_NO_LIMIT  (~0)

+

+#endif /* __DT_BINDINGS_THERMAL_H__ */

diff --git a/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf
new file mode 100644
index 000000000000..75256cbf6406
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf
@@ -0,0 +1,36 @@
+## @file

+#  Device tree description of the StarFive VisionFive 2 platform

+#

+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  INF_VERSION    = 0x0001001A

+  BASE_NAME      = VisionFive2DeviceTree

+  FILE_GUID      = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #gDtPlatformDefaultDtbFileGuid

+  MODULE_TYPE    = USER_DEFINED

+  VERSION_STRING = 1.0

+

+[Sources]

+  StarFiveClk.dtsi

+  StarFiveHdmi.dtsi

+  StarFiveVisionFive2.dtsi

+  StarFivePwmDac.dtsi

+  StarFiveVisionFive2.dts

+  StarFiveVisionFive2.dtsi

+  JH7110Rst.h

+  JH7110Power.h

+  JH7110ClkGen.h

+  JH7110ClkIsp.h

+  JH7110ClkVout.h

+  JH7110PinCtrl.h

+  Led.h

+  Irq.h

+  Gpio.h

+  Thermal.h

+

+[Packages]

+  MdePkg/MdePkg.dec

diff --git a/Platform/StarFive/VisionFive2/VarStore.fdf.inc b/Platform/StarFive/VisionFive2/VarStore.fdf.inc
new file mode 100644
index 000000000000..62b4baa43e98
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VarStore.fdf.inc
@@ -0,0 +1,77 @@
+## @file

+#  FDF include file with Layout Regions that define an empty variable store.

+#

+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+$(VARS_OFFSET)|$(VARS_SIZE)

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize

+#

+# NV_VARIABLE_STORE

+#

+DATA = {

+  ## This is the EFI_FIRMWARE_VOLUME_HEADER

+  # ZeroVector []

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  # FileSystemGuid: gEfiSystemNvDataFvGuid =

+  #   { 0xFFF12B8D, 0x7696, 0x4C8B,

+  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}

+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,

+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,

+  # FvLength: 0xC0000

+  0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,

+  # Signature "_FVH"       # Attributes

+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,

+  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision

+  0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02,

+  # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block

+  0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,

+  # Blockmap[1]: End

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  ## This is the VARIABLE_STORE_HEADER

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  # Signature: gEfiAuthenticatedVariableGuid =

+  #   { 0xaaf32c78, 0x947b, 0x439a,

+  #     { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}

+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,

+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,

+!else

+  # Signature: gEfiVariableGuid =

+  #   { 0xddcf3616, 0x3275, 0x4164,

+  #     { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}

+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,

+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,

+!endif

+  # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -

+  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3FFB8

+  # This can speed up the Variable Dispatch a bit.

+  0xB8, 0xFF, 0x03, 0x00,

+  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32

+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+}

+

+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize

+#

+# NV_FTW_WORKING

+#

+DATA = {

+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =

+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}

+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,

+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,

+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved

+  0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,

+  # WriteQueueSize: UINT64

+  0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00

+}

+

+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize

+#

+# NV_FTW_SPARE

+#

diff --git a/Platform/StarFive/VisionFive2/VisionFive2.dsc b/Platform/StarFive/VisionFive2/VisionFive2.dsc
new file mode 100644
index 000000000000..9135a11fec23
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.dsc
@@ -0,0 +1,596 @@
+## @file

+#  RISC-V EFI on StarFive VisionFive 2 platform

+#

+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+################################################################################

+#

+# Defines Section - statements that will be processed to create a Makefile.

+#

+################################################################################

+[Defines]

+  PLATFORM_NAME                  = VisionFive2

+  PLATFORM_GUID                  = 8317E90F-428B-403F-9057-112B0C19008E

+  PLATFORM_VERSION               = 0.1

+  DSC_SPECIFICATION              = 0x0001001c

+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)

+  SUPPORTED_ARCHITECTURES        = RISCV64

+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT

+  SKUID_IDENTIFIER               = DEFAULT

+  FLASH_DEFINITION               = Platform/StarFive/VisionFive2/VisionFive2.fdf

+

+  #

+  # Enable below options may cause build error or may not work on

+  # the initial version of RISC-V package

+  # Defines for default states.  These can be changed on the command line.

+  # -D FLAG=VALUE

+  #

+  DEFINE SECURE_BOOT_ENABLE      = FALSE

+  DEFINE DEBUG_ON_SERIAL_PORT    = FALSE

+

+  #

+  # Network definition

+  #

+  DEFINE NETWORK_SNP_ENABLE       = FALSE

+  DEFINE NETWORK_IP6_ENABLE       = FALSE

+  DEFINE NETWORK_TLS_ENABLE       = FALSE

+  DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE

+  DEFINE NETWORK_ISCSI_ENABLE     = FALSE

+

+[BuildOptions]

+  GCC:RELEASE_*_*_CC_FLAGS       = -DMDEPKG_NDEBUG

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  GCC:*_*_RISCV64_GENFW_FLAGS    = --keepexceptiontable

+!endif

+

+################################################################################

+#

+# SKU Identification section - list of all SKU IDs supported by this Platform.

+#

+################################################################################

+[SkuIds]

+  0|DEFAULT

+

+################################################################################

+#

+# Library Class section - list of all Library Classes needed by this Platform.

+#

+################################################################################

+

+!include MdePkg/MdeLibs.dsc.inc

+

+[LibraryClasses]

+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf

+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf

+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf

+  SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf

+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf

+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf

+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf

+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf

+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf

+  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf

+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf

+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf

+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf

+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf

+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf

+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf

+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf

+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf

+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf

+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf

+  SerialPortLib|MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf

+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf

+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf

+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf

+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf

+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf

+  DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf

+  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf

+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf

+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf

+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf

+  SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf

+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf

+  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf

+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf

+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf

+  VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf

+  VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf

+  NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf

+

+# RISC-V Platform Library

+  TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf

+  RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf

+

+# RISC-V Core Library

+  RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf

+

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf

+  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf

+!else

+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf

+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf

+!endif

+

+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf

+

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf

+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf

+  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf

+  AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf

+  SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf

+  SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf

+  PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf

+!else

+  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf

+  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf

+!endif

+  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf

+

+!if $(HTTP_BOOT_ENABLE) == TRUE

+  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf

+!endif

+

+  # ACPI not supported yet.

+  #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf

+  SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf

+  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf

+

+[LibraryClasses.common]

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf

+!endif

+  RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf

+  RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf

+  RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf

+  MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf

+  CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf

+  # Pci dependencies

+  PciHostBridgeLib|Silicon/StarFive/JH7110Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf

+  PciSegmentLib|Silicon/StarFive/JH7110Pkg/Library/PciSegmentLib/PciSegmentLib.inf

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+

+  # Flattened Device Tree (FDT) access library

+  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf

+

+[LibraryClasses.common.SEC]

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+

+  ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf

+

+[LibraryClasses.common.DXE_CORE]

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf

+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf

+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf

+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf

+!endif

+

+[LibraryClasses.common.DXE_RUNTIME_DRIVER]

+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf

+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf

+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf

+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf

+  ResetSystemLib|Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf

+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf

+!endif

+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf

+  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf

+

+[LibraryClasses.common.UEFI_DRIVER]

+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf

+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf

+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf

+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf

+  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf

+

+[LibraryClasses.common.DXE_DRIVER]

+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf

+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf

+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf

+!endif

+  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf

+  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf

+  PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

+  PlatformBmPrintScLib|OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf

+  PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf

+  PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf

+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf

+

+[LibraryClasses.common.UEFI_APPLICATION]

+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf

+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf

+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf

+!ifdef $(DEBUG_ON_SERIAL_PORT)

+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf

+!else

+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+!endif

+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf

+

+################################################################################

+#

+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.

+#

+################################################################################

+[PcdsFeatureFlag]

+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

+

+[PcdsFixedAtBuild]

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1

+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE

+  gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10

+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000

+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0

+

+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17

+!else

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F

+!endif

+

+!ifdef $(SOURCE_DEBUG_ENABLE)

+  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2

+!endif

+

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot

+  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04

+  gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04

+  gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04

+!endif

+

+  # F2 for UI APP

+  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }

+

+  # PCIE

+  gJH7110TokenSpaceGuid.PcdPciBusMin|0x00

+  gJH7110TokenSpaceGuid.PcdPciBusMax|0xFF

+  gJH7110TokenSpaceGuid.PcdPciIoBase|0x01

+  gJH7110TokenSpaceGuid.PcdPciIoSize|0x00 #Disable PIO

+  gJH7110TokenSpaceGuid.PcdPciIoOffset|0x00

+  gJH7110TokenSpaceGuid.PcdPci0Mmio32Base|0x30000000

+  gJH7110TokenSpaceGuid.PcdPci0Mmio32Size|0x80000000

+  gJH7110TokenSpaceGuid.PcdPci0Mmio64Base|0x900000000

+  gJH7110TokenSpaceGuid.PcdPci0Mmio64Size|0x40000000

+  gJH7110TokenSpaceGuid.PcdPci1Mmio32Base|0x38000000

+  gJH7110TokenSpaceGuid.PcdPci1Mmio32Size|0x80000000

+  gJH7110TokenSpaceGuid.PcdPci1Mmio64Base|0x980000000

+  gJH7110TokenSpaceGuid.PcdPci1Mmio64Size|0x40000000

+

+  # DW MMC/SD card controller

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0x16010000

+  gDesignWareTokenSpaceGuid.PcdDwSdDxeBaseAddress|0x16020000

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|198000000

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeMaxClockFreqInHz|198000000

+  gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|32

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeUHSEn|FALSE

+  gDesignWareTokenSpaceGuid.PcdDwEmmcDxeCPULittleEndian|TRUE

+

+  # SPI

+  gJH7110TokenSpaceGuid.PcdSpiFlashRegBase|0x13010000

+  gJH7110TokenSpaceGuid.PcdSpiFlashAhbBase|0x21000000

+  gJH7110TokenSpaceGuid.PcdSpiFlashFifoWidth|4

+  gJH7110TokenSpaceGuid.PcdSpiFlashRefClkHz|100000000

+  gJH7110TokenSpaceGuid.PcdSpiFlashTshslNs|1

+  gJH7110TokenSpaceGuid.PcdSpiFlashTsd2dNs|1

+  gJH7110TokenSpaceGuid.PcdSpiFlashTchshNs|1

+  gJH7110TokenSpaceGuid.PcdSpiFlashTslchNs|1

+

+################################################################################

+#

+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform

+#

+################################################################################

+

+[PcdsDynamicDefault]

+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0

+

+  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600

+

+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0

+

+  #

+  # Set video resolution for boot options and for text setup.

+  # PlatformDxe can set the former at runtime.

+  #

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0

+

+  # Set video resolution for text setup.

+  # gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480

+

+################################################################################

+#

+# Components Section - list of all EDK II Modules needed by this Platform.

+#

+################################################################################

+[Components]

+

+  #

+  # SEC Phase modules

+  #

+  OvmfPkg/RiscVVirt/Sec/SecMain.inf {

+    <LibraryClasses>

+      ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf

+      LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf

+      PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf

+      HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf

+      PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf

+      MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf

+  }

+

+  #

+  # DXE Phase modules

+  #

+  MdeModulePkg/Core/Dxe/DxeMain.inf {

+    <LibraryClasses>

+      NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf

+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf

+  }

+

+  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf

+  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf

+

+   MdeModulePkg/Universal/PCD/Dxe/Pcd.inf  {

+   <LibraryClasses>

+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf

+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf

+  }

+

+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

+

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {

+    <LibraryClasses>

+      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf

+  }

+!else

+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf

+!endif

+

+  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf

+  MdeModulePkg/Universal/Metronome/Metronome.inf

+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {

+    <LibraryClasses>

+      ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf

+  }

+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf

+

+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf

+  # MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

+  # MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

+  # MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+  #

+  # RISC-V Platform module

+  #

+  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf

+

+  #

+  # RISC-V Core module

+  #

+  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf

+  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf

+

+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf

+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {

+    <LibraryClasses>

+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf

+      VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf

+  }

+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf

+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf

+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf

+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf

+

+  #

+  # Emulator for x64 OpRoms, etc.

+  #

+  #MultiArchUefiPkg/Drivers/Emulator/Emulator.inf {

+  #    <LibraryClasses>

+  #    UnicornEngineLib|unicorn/efi/UnicornEngineLib.inf

+  #    UnicornStubLib|unicorn/efi/UnicornStubLib.inf

+  #    UnicornX86Lib|unicorn/efi/UnicornX86Lib.inf

+  #}

+

+  # No graphic console supported yet.

+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {

+  <LibraryClasses>

+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  }

+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {

+    <LibraryClasses>

+      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf

+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

+  }

+  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf

+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf

+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf

+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf

+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf

+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

+  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf

+  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf

+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+

+  #

+  # Network Support

+  #

+  !include NetworkPkg/Network.dsc.inc

+

+  #

+  # sdio/mmc support

+  #

+  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf

+  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf {

+    <BuildOptions>

+      GCC:*_*_*_CC_FLAGS       = -DCONFIG_DWEMMC

+  }

+  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf {

+    <BuildOptions>

+      GCC:*_*_*_CC_FLAGS       = -DCONFIG_DWSDMMC

+  }

+

+  #

+  # PCIe support

+  #

+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {

+    <LibraryClasses>

+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf

+  }

+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+

+  #

+  # NVMe boot devices

+  #

+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

+

+  #

+  # Usb Support

+  #

+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf

+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf

+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf

+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf

+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

+

+  #

+  # FAT filesystem + GPT/MBR partitioning + UDF filesystem

+  #

+  FatPkg/EnhancedFatDxe/Fat.inf

+  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf

+

+  #

+  # QSPI Flash Support

+  #

+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf

+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf

+  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf

+

+  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {

+    <PcdsFixedAtBuild>

+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE

+    <LibraryClasses>

+      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf

+      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf

+  }

+

+  ShellPkg/Application/Shell/Shell.inf {

+    <LibraryClasses>

+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf

+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf

+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf

+      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf

+      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf

+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf

+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf

+

+    <PcdsFixedAtBuild>

+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF

+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE

+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000

+  }

+

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf

+!endif

+

+  MdeModulePkg/Logo/LogoDxe.inf

+  MdeModulePkg/Application/UiApp/UiApp.inf {

+    <LibraryClasses>

+      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf

+      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf

+      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf

+  }

+

+  #

+  # Device Tree Binary

+  # - Compile by EDK2, and will embed into OpenSBI .rodata section using FW_FDT_PATH

+  #   when compiling OpenSBI. EDK2 will get the start address of the device tree from

+  #   register 'a1'

+  #

+  Platform/StarFive/VisionFive2/DeviceTree/VisionFive2DeviceTree.inf

diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf b/Platform/StarFive/VisionFive2/VisionFive2.fdf
new file mode 100644
index 000000000000..4007258ea588
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf
@@ -0,0 +1,284 @@
+# @file

+#  Flash definition file on StarFive VisionFive 2 platform

+#

+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+!include VisionFive2.fdf.inc

+

+#

+# Build the variable store and the firmware code as one unified flash device

+# image.

+#

+[FD.VisionFive2]

+BaseAddress   = $(FW_BASE_OFFSET)

+Size          = $(FW_SIZE)

+ErasePolarity = 1

+BlockSize     = $(BLOCK_SIZE)

+NumBlocks     = $(BLOCK_NUM)

+

+

+$(FVMAIN_OFFSET)|$(FVMAIN_SIZE)

+gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize

+FV = FVMAIN_COMPACT

+

+!include VarStore.fdf.inc

+

+################################################################################

+

+[FV.DXEFV]

+BlockSize          = 0x10000

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 27A72E80-3118-4c0c-8673-AA5B4EFA9613

+

+APRIORI DXE {

+  INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf

+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf

+  INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf

+}

+

+#

+# DXE Phase modules

+#

+INF  MdeModulePkg/Core/Dxe/DxeMain.inf

+

+INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf

+INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf

+INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf

+

+#

+# Emulator for x64 OpRoms, etc.

+#

+#INF  MultiArchUefiPkg/Drivers/Emulator/Emulator.inf

+

+INF  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf

+INF  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf

+INF  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf

+INF  MdeModulePkg/Universal/Metronome/Metronome.inf

+INF  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf

+

+# RISC-V Core Drivers

+INF  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf

+INF  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf

+

+INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf

+

+INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf

+!if $(SECURE_BOOT_ENABLE) == TRUE

+  INF  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf

+!endif

+

+INF  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf

+INF  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf

+INF  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf

+INF  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf

+#

+# Multiple Console IO support

+#

+INF  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

+INF  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf

+INF  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

+INF  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf

+INF  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf

+INF  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf

+INF  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf

+INF  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf

+INF  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf

+INF  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf

+INF  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf

+INF  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+# INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

+# INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

+INF  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf

+INF  FatPkg/EnhancedFatDxe/Fat.inf

+INF  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf

+

+# !ifndef $(SOURCE_DEBUG_ENABLE)

+# INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf

+# !endif

+

+INF  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf

+INF  ShellPkg/Application/Shell/Shell.inf

+

+#

+# Bds

+#

+INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

+INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

+INF  MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf

+INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf

+INF  MdeModulePkg/Application/UiApp/UiApp.inf

+

+#

+# Network modules

+#

+!if $(E1000_ENABLE)

+  FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {

+    SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI

+  }

+!endif

+

+!include NetworkPkg/Network.fdf.inc

+

+#

+# SDIO/MMC support

+#

+INF  EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf

+INF  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf

+INF  Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwSdmmcDxe.inf

+

+#

+# PCIe support

+#

+INF  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf

+INF  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+

+# NVMe boot devices

+INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

+

+#

+# Usb Support

+#

+INF  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf

+INF  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

+INF  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

+INF  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf

+INF  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf

+INF  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf

+INF  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf

+

+#

+# TianoCore logo (splash screen)

+#

+INF  MdeModulePkg/Logo/LogoDxe.inf

+

+#

+# QSPI Flash Support

+#

+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiDxe/SpiDxe.inf

+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/SpiFlashDxe/SpiFlashDxe.inf

+INF  Silicon/StarFive/JH7110Pkg/Driver/SpiFvbServicesDxe/FvbDxe/FvbDxe.inf

+################################################################################

+

+[FV.FVMAIN_COMPACT]

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+

+INF OvmfPkg/RiscVVirt/Sec/SecMain.inf

+

+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {

+   SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+     #

+     # These firmware volumes will have files placed in them uncompressed,

+     # and then both firmware volumes will be compressed in a single

+     # compression operation in order to achieve better overall compression.

+     #

+     SECTION FV_IMAGE = DXEFV

+   }

+ }

+

+[Rule.Common.SEC]

+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED{

+    PE32     PE32   Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING ="$(MODULE_NAME)" Optional

+    VERSION  STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.DXE_CORE]

+  FILE DXE_CORE = $(NAMED_GUID) {

+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.DXE_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.DXE_RUNTIME_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.UEFI_DRIVER]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex

+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.UEFI_DRIVER.BINARY]

+  FILE DRIVER = $(NAMED_GUID) {

+    DXE_DEPEX DXE_DEPEX Optional      |.depex

+    PE32      PE32   |.efi

+    UI        STRING="$(MODULE_NAME)" Optional

+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.UEFI_APPLICATION]

+  FILE APPLICATION = $(NAMED_GUID) {

+    PE32     PE32  $(INF_OUTPUT)/$(MODULE_NAME).efi

+    UI       STRING="$(MODULE_NAME)" Optional

+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.UEFI_APPLICATION.BINARY]

+  FILE APPLICATION = $(NAMED_GUID) {

+    PE32      PE32  |.efi

+    UI        STRING="$(MODULE_NAME)" Optional

+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)

+  }

+

+[Rule.Common.USER_DEFINED.ACPITABLE]

+  FILE FREEFORM = $(NAMED_GUID) {

+    RAW ACPI               |.acpi

+    RAW ASL                |.aml

+  }

+

+[Rule.Common.USER_DEFINED.DTB]

+  FILE FREEFORM = $(NAMED_GUID) {

+    RAW BIN                |.dtb

+  }

diff --git a/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc b/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc
new file mode 100644
index 000000000000..98beda0de77c
--- /dev/null
+++ b/Platform/StarFive/VisionFive2/VisionFive2.fdf.inc
@@ -0,0 +1,48 @@
+## @file

+#  Definitions of Flash definition file on StarFive VisionFive 2 platform

+#

+#  Copyright (c) 2023, StarFive Technology Co., Ltd. All rights reserved.<BR>

+#

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+#

+# OpenSBI: 0x4000_0000 ~ 0x401F_FFFF

+# EDK2   : 0x4020_0000 ~ 0x40A0_0000

+#

+DEFINE FSBL_SIZE      = 0x00100000 #100MB

+DEFINE OPENSBI_SIZE   = 0x00200000

+DEFINE FW_BASE_OFFSET = 0x40200000

+DEFINE FW_SIZE        = 0x00800000 # (BLOCK_NUM x BLOCK_SIZE)

+

+DEFINE BLOCK_NUM      = 0x800

+DEFINE BLOCK_SIZE     = 0x1000

+

+DEFINE FVMAIN_OFFSET  = 0x00000000 # Offset from FW_BASE end

+DEFINE FVMAIN_SIZE    = 0x00740000

+

+#

+# EFI Variables memory region in Flash.

+#

+DEFINE VARS_OFFSET             = 0x00740000 # Offset from FW_BASE end

+DEFINE VARS_SIZE               = 0x00040000

+DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_SIZE)

+DEFINE VARS_FTW_WORKING_SIZE   = 0x00040000

+DEFINE VARS_FTW_SPARE_OFFSET   = $(VARS_FTW_WORKING_OFFSET) + $(VARS_FTW_WORKING_SIZE)

+DEFINE VARS_FTW_SPARE_SIZE     = 0x00040000

+

+#

+# Memory map use for non-volatile variable offset in flash

+# | FSBL | OPENSBI | EDK2 | EFI VARS | ... |

+#

+SET gJH7110TokenSpaceGuid.PcdJH7110FlashVarOffset = $(FSBL_SIZE) + $(OPENSBI_SIZE) + $(VARS_OFFSET)

+

+#

+# Temporary RAM region use for sec startup before memory is discovered

+#

+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase = 0x43FF0000

+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize = 0x00010000

+

+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency = 24000000 # 24Mhz

-- 
2.34.1



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^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2023-10-27  1:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-23  8:01 [edk2-devel] [PATCH v2 1/1] StarFive/VisionFive2: Add VisionFive 2 platform John Chew
2023-10-26 13:47 ` Sunil V L
2023-10-27  1:39   ` John Chew
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2023-10-23  7:19 John Chew
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