From: "Jonathan Cameron via groups.io" <jonathan.cameron=huawei.com@groups.io>
To: Laszlo Ersek <lersek@redhat.com>
Cc: <devel@edk2.groups.io>, <kraxel@redhat.com>,
<yoshinoyatoko@163.com>, "Ni, Ray" <ray.ni@intel.com>,
Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Subject: Re: [edk2-devel] question about cxl device enumeration in pci bus driver
Date: Thu, 26 Oct 2023 14:35:38 +0100 [thread overview]
Message-ID: <20231026143538.00005d15@Huawei.com> (raw)
In-Reply-To: <5df5f698-7f1d-98f3-e6a2-7b1a4c978528@redhat.com>
On Thu, 26 Oct 2023 11:49:28 +0200
"Laszlo Ersek" <lersek@redhat.com> wrote:
> On 10/26/23 10:33, Gerd Hoffmann wrote:
> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
> >
> >> CXL Host Bridge / Root Port / Switch / Device enumeration / HDM Config, maybe could be integrated into pci drivers stack.
> >
> > Point being? Can or should the firmware do anything useful with
> > the CXL hardware? If so, what exactly and why?
> >
> > Current state of affairs is that the PCI stack does the usual PCI
> > initialization (enumerate, assign resources to PCI bars) and leaves
> > everything else to the OS.
>
> (I don't know what "HDM Config" stands for.)
>
> The only utility for driving CXL devices from the firmware could be, AFAICT:
>
> - booting off of such a device (or at least "supporting OS boot" in some
> manner)
>
> - using such a device for UEFI console purposes
There are different models for how to use CXL devices and what's possible depends on the
version of CXL. CXL 1.1 wasn't great for standards defined discovery, so
EDK2 platform logic basically has to do everything.
The one mostly expected for early CXL servers, for backwards compatibility, makes
setting up the CXL memory decoders (Host managed Device Memory - HDM) in all the
components in the path to memory + locking them down an EDK2 problem. They are then
presented in the memory map and in SRAT, HMAT etc the same as normal DDR memory.
Idea being that an old OS will be fine with that and doesn't have to be CXL aware
at all. Note this also involves walking the CDAT tables via DOE mailboxes in PCI
config space to get the magic numbers needed to compute HMAT.
The other model is to do very little in EDK2 and make entirely a problem for the OS.
The logic is necessary anyway if you want to support hotplug etc, so use it for the
cold plug paths 2. That's all we've currently supported on QEMU.
There was a presentation at Linux Plumbers last year on some out of tree support
from ARM for doing the setup on a CXL 2.0 platform (I think) in EDK2
https://lpc.events/event/16/contributions/1254/
But I guess it never went upstream.
https://github.com/SayantaP-arm/edk2-platforms/tree/cxl-type-3
+CC Sayanta
Jonathan
>
> Laszlo
>
>
>
>
>
>
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next prev parent reply other threads:[~2023-10-26 13:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 6:01 [edk2-devel] question about cxl device enumeration in pci bus driver Yoshinoya
2023-10-25 10:13 ` Ni, Ray
2023-10-26 2:36 ` Yoshinoya
2023-10-26 8:33 ` Gerd Hoffmann
2023-10-26 9:49 ` Laszlo Ersek
2023-10-26 13:35 ` Jonathan Cameron via groups.io [this message]
2023-10-27 1:26 ` Yoshinoya
[not found] ` <1791D2898E0C74CA.20272@groups.io>
2023-10-27 1:29 ` Yoshinoya
2023-10-27 5:49 ` Ni, Ray
2023-11-06 11:20 ` Yoshinoya
2023-11-07 21:54 ` Brian J. Johnson
2023-11-17 1:41 ` Yoshinoya
2023-11-07 11:31 ` [edk2-devel] Use dynamic pcd in smm mode Yoshinoya
2023-11-07 12:45 ` Laszlo Ersek
2023-11-09 6:03 ` Yoshinoya
2023-11-17 2:15 ` [edk2-devel] question about PrmPkg Yoshinoya
2023-11-17 8:42 ` Laszlo Ersek
2023-11-17 16:04 ` Michael Kubacki
2023-11-20 2:09 ` Yoshinoya
2023-11-20 13:58 ` Michael Kubacki
2024-02-27 10:06 ` [edk2-devel] Question about SMM code privilege switch Yoshinoya
2024-03-04 1:20 ` Yoshinoya
2024-05-23 2:07 ` [edk2-devel] What PTSS abbreviation means Yoshinoya
2024-02-05 9:49 ` [edk2-devel] sctpackage failed to be compile with new udk codebase Yoshinoya
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