From: "Dhaval Sharma" <dhaval@rivosinc.com>
To: devel@edk2.groups.io
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Daniel Schaefer <git@danielschaefer.me>,
Laszlo Ersek <lersek@redhat.com>
Subject: [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations
Date: Sun, 29 Oct 2023 20:16:11 +0530 [thread overview]
Message-ID: <20231029144613.150580-4-dhaval@rivosinc.com> (raw)
In-Reply-To: <20231029144613.150580-1-dhaval@rivosinc.com>
Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.
Notes:
1. CMO only supports block based Operations. Meaning cache
flush/invd/clean Operations are not available for the entire
range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
independent. binutils 2.39+ compilers support CMO instructions.
Test:
1. Ensured correct instructions are refelecting in asm
2. Not able to verify actual instruction in HW as Qemu ignores
any actual cache operations.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
Notes:
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions in Baselib
MdePkg/Library/BaseLib/BaseLib.inf | 2 +-
MdePkg/Include/Library/BaseLib.h | 33 ++++++++++++++++++++
MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++++++++++
MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 ++++++++++
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 03c7b02e828b..53389389448c 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -400,7 +400,7 @@ [Sources.RISCV64]
RiscV64/RiscVCpuBreakpoint.S | GCC
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
- RiscV64/FlushCache.S | GCC
+ RiscV64/RiscVCacheMgmt.S | GCC
RiscV64/CpuScratch.S | GCC
RiscV64/ReadTimer.S | GCC
RiscV64/RiscVMmu.S | GCC
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d4b56a9601da..c42cc165dc82 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence (
VOID
);
+/**
+ RISC-V flush cache block. Atomically perform a clean operation
+ followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushAsmCmo (
+ IN UINTN
+ );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanAsmCmo (
+ IN UINTN
+ );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalAsmCmo (
+ IN UINTN
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/RiscVasm.inc
new file mode 100644
index 000000000000..29de7358855c
--- /dev/null
+++ b/MdePkg/Include/RiscV64/RiscVasm.inc
@@ -0,0 +1,19 @@
+/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+ .word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+ .word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+ .word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
similarity index 56%
rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S
rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
index e0eea0b5fb25..3c7be3229e3b 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S
@@ -3,10 +3,12 @@
// RISC-V cache operation.
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
+.include "RiscVasm.inc"
.align 3
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheAsmFence):
ASM_PFX(RiscVInvalidateDataCacheAsmFence):
fence
ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushAsmCmo)
+ASM_PFX (RiscVCpuCacheFlushAsmCmo):
+ RISCVCMOFLUSH
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanAsmCmo)
+ASM_PFX (RiscVCpuCacheCleanAsmCmo):
+ RISCVCMOCLEAN
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalAsmCmo)
+ASM_PFX (RiscVCpuCacheInvalAsmCmo):
+ RISCVCMOINVALIDATE
+ ret
--
2.39.2
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next prev parent reply other threads:[~2023-10-29 14:46 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-29 14:46 [edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
2023-10-29 14:46 ` [edk2-devel] [PATCH v7 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
2023-10-29 14:46 ` [edk2-devel] [PATCH v7 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
2023-10-29 14:46 ` Dhaval Sharma [this message]
2023-10-29 19:12 ` [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations Pedro Falcato
2023-10-30 9:38 ` Laszlo Ersek
2023-10-30 11:33 ` Sunil V L
2023-10-30 16:37 ` Pedro Falcato
2023-10-31 9:55 ` Dhaval Sharma
2023-10-31 15:37 ` Laszlo Ersek
2023-10-31 19:19 ` Pedro Falcato
2023-11-01 8:03 ` Jingyu Li via groups.io
2023-10-30 10:55 ` Sunil V L
2023-10-31 6:45 ` Jingyu Li via groups.io
2023-10-29 14:46 ` [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
2023-10-29 19:07 ` Pedro Falcato
2023-10-30 9:40 ` Laszlo Ersek
2023-10-30 11:18 ` Sunil V L
2023-10-30 11:22 ` Sunil V L
2023-10-31 10:42 ` Laszlo Ersek
2023-10-31 6:18 ` Dhaval Sharma
2023-10-31 6:24 ` Dhaval Sharma
2023-10-31 7:36 ` Sunil V L
2023-10-31 10:41 ` Laszlo Ersek
2023-10-29 14:46 ` [edk2-devel] [PATCH v7 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
2023-10-31 4:13 ` Andrei Warkentin
2023-10-31 6:12 ` Dhaval Sharma
2023-10-31 17:01 ` Andrei Warkentin
2023-11-01 17:05 ` Dhaval Sharma
2023-11-01 20:27 ` Andrei Warkentin
2023-10-29 19:15 ` [edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V Pedro Falcato
2023-10-31 4:16 ` Andrei Warkentin
2023-10-31 5:13 ` Dhaval Sharma
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