From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 475A5D8081E for ; Sun, 29 Oct 2023 14:46:35 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=NRtdkv18HdX2vUARp3LNsexPRmDOd0BGFCcr8VuIUhQ=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1698590794; v=1; b=juFnrkyEX9okOY7xHQFj4dXJEns3kOL5l92b74IF0/MPmrryTW617Op/1NeJMnYJUP5BdqQI VCOrXIXhHI2EzfdyIo5Y2GuKmsxFKS8IFqDRDQO7yn68Wz3nzcza9pjy72LmTg56wNSllawAFMk GckbiPs25/+UT9ldySmoKWHE= X-Received: by 127.0.0.2 with SMTP id 6SRIYY7687511x2jyDUlAl22; Sun, 29 Oct 2023 07:46:34 -0700 X-Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) by mx.groups.io with SMTP id smtpd.web10.73333.1698590793498983580 for ; Sun, 29 Oct 2023 07:46:33 -0700 X-Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-577fff1cae6so2446798a12.1 for ; Sun, 29 Oct 2023 07:46:33 -0700 (PDT) X-Gm-Message-State: Qn1dAZq8yMh2zKkeg3AjhPRSx7686176AA= X-Google-Smtp-Source: AGHT+IETh1OjqiuEWfe4eAGd73cGolEV+jgqEuFN2Jg/uVzsoDG2q6OI6oz5iEtZgnuGgXDtQNYY/Q== X-Received: by 2002:a17:90b:190c:b0:280:3173:5861 with SMTP id mp12-20020a17090b190c00b0028031735861mr3652270pjb.2.1698590792784; Sun, 29 Oct 2023 07:46:32 -0700 (PDT) X-Received: from dhaval.. ([171.76.85.25]) by smtp.gmail.com with ESMTPSA id pt11-20020a17090b3d0b00b0027d15bd9fa2sm3783336pjb.35.2023.10.29.07.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Oct 2023 07:46:32 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Date: Sun, 29 Oct 2023 20:16:12 +0530 Message-Id: <20231029144613.150580-5-dhaval@rivosinc.com> In-Reply-To: <20231029144613.150580-1-dhaval@rivosinc.com> References: <20231029144613.150580-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=juFnrkyE; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none Use newly defined cache management operations for RISC-V where possible It builds up on the support added for RISC-V cache management instructions in BaseLib. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Acked-by: Laszlo Ersek --- Notes: V7: - Added PcdLib - Restructure DEBUG message based on feedback on V6 - Make naming consistent to CMO, remove all CBO references - Add ASSERT for not supported functions instead of plain debug message - Added RB tag V6: - Utilize cache management instructions if HW supports it This patch is part of restructuring on top of v5 MdePkg/MdePkg.dec | 8 + MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 168 += ++++++++++++++++--- MdePkg/MdePkg.uni | 4 + 4 files changed, 165 insertions(+), 20 deletions(-) diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index ac54338089e8..fa92673ff633 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64] # @Prompt CPU Rng algorithm's GUID.=0D gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037=0D =0D +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]=0D + #=0D + # Configurability to override RISC-V CPU Features=0D + # BIT 0 =3D Cache Management Operations. This bit is relevant only if=0D + # previous stage has feature enabled and user wants to disable it.=0D + #=0D + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT= 64|0x69=0D +=0D [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D ## This value is used to set the base address of PCI express hierarchy.= =0D # @Prompt PCI Express Base Address.=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 6fd9cbe5f6c9..601a38d6c109 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -56,3 +56,8 @@ [LibraryClasses] BaseLib=0D DebugLib=0D =0D +[LibraryClasses.RISCV64]=0D + PcdLib=0D +=0D +[Pcd.RISCV64]=0D + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index 4eb18edb9aa7..5b3104afb67e 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -2,6 +2,7 @@ RISC-V specific functionality for cache.=0D =0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -9,10 +10,115 @@ #include =0D #include =0D #include =0D +#include =0D +=0D +//=0D +// TODO: Grab cache block size and make Cache Management Operation=0D +// enabling decision based on RISC-V CPU HOB in=0D +// future when it is available.=0D +//=0D +#define RISCV_CACHE_BLOCK_SIZE 64=0D +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1=0D +=0D +typedef enum {=0D + Clean,=0D + Flush,=0D + Invld,=0D +} CACHE_OP;=0D +=0D +/**=0D +Verify CBOs are supported by this HW=0D +TODO: Use RISC-V CPU HOB once available.=0D +=0D +**/=0D +STATIC=0D +BOOLEAN=0D +RiscVIsCMOEnabled (=0D + VOID=0D + )=0D +{=0D + // If CMO is disabled in HW, skip Override check=0D + // Otherwise this PCD can override settings=0D + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITM= ASK) !=3D 0);=0D +}=0D +=0D +/**=0D + Performs required opeartion on cache lines in the cache coherency domain= =0D + of the calling CPU. If Address is not aligned on a cache line boundary,= =0D + then entire cache line containing Address is operated. If Address + Leng= th=0D + is not aligned on a cache line boundary, then the entire cache line=0D + containing Address + Length -1 is operated.=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D + @param Address The base address of the cache lines to=0D + invalidate.=0D + @param Length The number of bytes to invalidate from the instruction=0D + cache.=0D + @param Op Type of CMO operation to be performed=0D + @return Address.=0D +=0D +**/=0D +STATIC=0D +VOID=0D +CacheOpCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length,=0D + IN CACHE_OP Op=0D + )=0D +{=0D + UINTN CacheLineSize;=0D + UINTN Start;=0D + UINTN End;=0D +=0D + if (Length =3D=3D 0) {=0D + return;=0D + }=0D +=0D + if ((Op !=3D Invld) && (Op !=3D Flush) && (Op !=3D Clean)) {=0D + return;=0D + }=0D +=0D + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address));=0D +=0D + CacheLineSize =3D RISCV_CACHE_BLOCK_SIZE;=0D +=0D + Start =3D (UINTN)Address;=0D + //=0D + // Calculate the cache line alignment=0D + //=0D + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1)= ;=0D + Start &=3D ~((UINTN)CacheLineSize - 1);=0D +=0D + DEBUG (=0D + (DEBUG_INFO,=0D + "CacheOpCacheRange:\=0D + Performing Cache Management Operation %d \n", Op)=0D + );=0D +=0D + do {=0D + switch (Op) {=0D + case Invld:=0D + RiscVCpuCacheInvalAsmCmo (Start);=0D + break;=0D + case Flush:=0D + RiscVCpuCacheFlushAsmCmo (Start);=0D + break;=0D + case Clean:=0D + RiscVCpuCacheCleanAsmCmo (Start);=0D + break;=0D + default:=0D + break;=0D + }=0D +=0D + Start =3D Start + CacheLineSize;=0D + } while (Start !=3D End);=0D +}=0D =0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D - calling CPU.=0D + calling CPU. Risc-V does not have currently an CBO implementation which = can=0D + invalidate the entire I-cache. Hence using Fence instruction for now. P.= S.=0D + Fence instruction may or may not implement full I-cache invd functionali= ty=0D + on all implementations.=0D =0D **/=0D VOID=0D @@ -56,12 +162,18 @@ InvalidateInstructionCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG (=0D - (DEBUG_WARN,=0D - "%a:RISC-V unsupported function.\n"=0D - "Invalidating the whole instruction cache instead.\n", __func__)=0D - );=0D - InvalidateInstructionCache ();=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, Invld);=0D + } else {=0D + DEBUG (=0D + (DEBUG_VERBOSE,=0D + "InvalidateInstructionCacheRange:\=0D + Zicbom not supported.\n" \=0D + "Invalidating the whole instruction cache instead.\n")=0D + );=0D + InvalidateInstructionCache ();=0D + }=0D +=0D return Address;=0D }=0D =0D @@ -81,7 +193,8 @@ WriteBackInvalidateDataCache ( VOID=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + DEBUG ((DEBUG_ERROR, "WriteBackInvalidateDataCache:\=0D + RISC-V unsupported function.\n"));=0D }=0D =0D /**=0D @@ -117,7 +230,12 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, Flush);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D +=0D return Address;=0D }=0D =0D @@ -137,7 +255,7 @@ WriteBackDataCache ( VOID=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + ASSERT (FALSE);=0D }=0D =0D /**=0D @@ -156,10 +274,7 @@ WriteBackDataCache ( =0D If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D =0D - @param Address The base address of the data cache lines to write back. = If=0D - the CPU is in a physical addressing mode, then Address i= s a=0D - physical address. If the CPU is in a virtual addressing= =0D - mode, then Address is a virtual address.=0D + @param Address The base address of the data cache lines to write back.= =0D @param Length The number of bytes to write back from the data cache.=0D =0D @return Address of cache written in main memory.=0D @@ -172,7 +287,12 @@ WriteBackDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, Clean);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D +=0D return Address;=0D }=0D =0D @@ -214,10 +334,7 @@ InvalidateDataCache ( =0D If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D =0D - @param Address The base address of the data cache lines to invalidate. = If=0D - the CPU is in a physical addressing mode, then Address i= s a=0D - physical address. If the CPU is in a virtual addressing = mode,=0D - then Address is a virtual address.=0D + @param Address The base address of the data cache lines to invalidate.= =0D @param Length The number of bytes to invalidate from the data cache.=0D =0D @return Address.=0D @@ -230,6 +347,17 @@ InvalidateDataCacheRange ( IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, Invld);=0D + } else {=0D + DEBUG (=0D + (DEBUG_VERBOSE,=0D + "InvalidateDataCacheRange:\=0D + Zicbom not supported.\n" \=0D + "Invalidating the whole Data cache instead.\n")=0D + );=0D + InvalidateDataCache ();=0D + }=0D +=0D return Address;=0D }=0D diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni index 5c1fa24065c7..f49c33191054 100644 --- a/MdePkg/MdePkg.uni +++ b/MdePkg/MdePkg.uni @@ -287,6 +287,10 @@ =0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_H= ELP #language en-US "This value is used to set the available memory addres= s to store Guided Extract Handlers. The required memory space is decided by= the value of PcdMaximumGuidedExtractHandler."=0D =0D +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #lang= uage en-US "RISC-V Feature Override"=0D +=0D +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #langua= ge en-US "This value is used to Override Any RISC-V specific features suppo= rted by this PCD"=0D +=0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #lan= guage en-US "PCI Express Base Address"=0D =0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #langu= age en-US "This value is used to set the base address of PCI express hierar= chy."=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110266): https://edk2.groups.io/g/devel/message/110266 Mute This Topic: https://groups.io/mt/102256468/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-