* [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure
@ 2023-11-02 3:45 Narinder Dhillon
2023-11-02 3:45 ` [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package Narinder Dhillon
2023-11-16 17:11 ` [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure Leif Lindholm
0 siblings, 2 replies; 4+ messages in thread
From: Narinder Dhillon @ 2023-11-02 3:45 UTC (permalink / raw)
To: devel; +Cc: quic_llindhol, mw, sbalcerak, Narinder Dhillon
From: Narinder Dhillon <ndhillon@marvell.com>
Current Silicon/Marvell package structure does not allow sharing of
components that are common to different SoC's. This restructure will
increase shared code and better seperation.
Credit to Leif Lindholm for providing this new structure.
v2:
- Remove three lines for libraries that were erroneously introduced
into MarvellSiliconPkg.dec file. These libraries are present in
Armada7k8k.dsc.inc
- Removed trailing new line at the end of MarvellSiliconPkg.dec
- Squashed patches 2,3,4 into 1 as they don't build separately
v1:
- Original patch series restructuring Marvell package
Narinder Dhillon (1):
Silicon/Marvell: Retructure package
.../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 ++++-----
.../Armada70x0DbBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 ++++++-----
.../Armada80x0DbBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Cn9130DbABoardDescLib.inf | 2 +-
.../Cn9132DbABoardDescLib.inf | 2 +-
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++-----
Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 +++---
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 +++---
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++-----
.../Armada80x0McBinBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../BoardDescriptionLib.inf | 2 +-
.../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 ++--
.../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++---
.../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++---
.../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++---
.../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Applications/EepromCmd/EepromCmd.inf | 2 +-
.../Applications/FirmwareUpdate/FUpdate.inf | 6 +-
.../Applications/SpiTool/SpiFlashCmd.inf | 6 +-
.../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +-
.../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +-
.../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 +-
.../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +-
.../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +-
.../PlatformFlashAccessLib.inf | 6 +-
.../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +-
.../Armada7k8kMemoryInitPeiLib.inf | 14 +-
.../PciHostBridgeLib.inf | 2 +-
.../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +-
.../Armada7k8kSampleAtResetLib.inf | 2 +-
.../Armada7k8kSoCDescLib.inf | 4 +-
.../RealTimeClockLib/RealTimeClockLib.inf | 4 +-
.../Marvell/Documentation/PortingGuide.txt | 114 +++++-----
.../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-
.../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +-
.../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +-
.../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +-
.../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-
.../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +-
.../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +-
Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-
.../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +-
.../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +-
.../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-
.../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +-
.../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +-
.../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +-
.../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 +--
Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +-
Silicon/Marvell/Library/MppLib/MppLib.inf | 94 ++++----
.../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +-
.../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +-
Silicon/Marvell/Marvell.dec | 208 ------------------
.../Include/IndustryStandard/MvSmc.h | 0
.../Include/Library/ArmadaBoardDescLib.h | 0
.../Include/Library/ArmadaIcuLib.h | 0
.../Include/Library/ArmadaSoCDescLib.h | 0
.../Include/Library/MppLib.h | 0
.../Include/Library/MvComPhyLib.h | 0
.../Include/Library/MvGpioLib.h | 0
.../Include/Library/NonDiscoverableInitLib.h | 0
.../Include/Library/SampleAtResetLib.h | 0
.../Include/Library/UtmiPhyLib.h | 0
.../Include/Protocol/BoardDesc.h | 0
.../Include/Protocol/Eeprom.h | 0
.../Include/Protocol/Mdio.h | 0
.../Include/Protocol/MvI2c.h | 0
.../Include/Protocol/MvPhy.h | 0
.../Include/Protocol/Spi.h | 0
.../Include/Protocol/SpiFlash.h | 0
.../MarvellSiliconPkg/MarvellSiliconPkg.dec | 207 +++++++++++++++++
.../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +-
.../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +-
.../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +-
82 files changed, 848 insertions(+), 852 deletions(-)
delete mode 100644 Silicon/Marvell/Marvell.dec
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/IndustryStandard/MvSmc.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaBoardDescLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaIcuLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaSoCDescLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MppLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvComPhyLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvGpioLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/NonDiscoverableInitLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/SampleAtResetLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/UtmiPhyLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/BoardDesc.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Eeprom.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Mdio.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvI2c.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvPhy.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Spi.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/SpiFlash.h (100%)
create mode 100644 Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
base-commit: c1d04ecedf3246ec7c2e0cc12658c9c6a26f91ac
--
2.34.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package
2023-11-02 3:45 [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure Narinder Dhillon
@ 2023-11-02 3:45 ` Narinder Dhillon
2023-11-14 20:24 ` Marcin Wojtas via groups.io
2023-11-16 17:11 ` [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure Leif Lindholm
1 sibling, 1 reply; 4+ messages in thread
From: Narinder Dhillon @ 2023-11-02 3:45 UTC (permalink / raw)
To: devel; +Cc: quic_llindhol, mw, sbalcerak, Narinder Dhillon
From: Narinder Dhillon <ndhillon@marvell.com>
Current Marvell package structure makes it difficult to add new silicon
packages that reuse common elements without creating nested DEC files.
This patch creates a new MarvellSiliconPkg folder and moves the current
common elements inside it.
Also gMarvellTokenSpaceGuid has been renamed to
gMarvellSiliconTokenSpaceGuid to align with new package name.
Signed-off-by: Narinder Dhillon <ndhillon@marvell.com>
---
.../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 ++++-----
.../Armada70x0DbBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 ++++++-----
.../Armada80x0DbBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Cn9130DbABoardDescLib.inf | 2 +-
.../Cn9132DbABoardDescLib.inf | 2 +-
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++-----
Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 +++---
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 +++---
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++-----
.../Armada80x0McBinBoardDescLib.inf | 2 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../BoardDescriptionLib.inf | 2 +-
.../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 ++--
.../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++---
.../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++---
.../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++---
.../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +-
.../NonDiscoverableInitLib.inf | 2 +-
.../Applications/EepromCmd/EepromCmd.inf | 2 +-
.../Applications/FirmwareUpdate/FUpdate.inf | 6 +-
.../Applications/SpiTool/SpiFlashCmd.inf | 6 +-
.../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +-
.../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +-
.../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +-
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 +-
.../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +-
.../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +-
.../PlatformFlashAccessLib.inf | 6 +-
.../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +-
.../Armada7k8kMemoryInitPeiLib.inf | 14 +-
.../PciHostBridgeLib.inf | 2 +-
.../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +-
.../Armada7k8kSampleAtResetLib.inf | 2 +-
.../Armada7k8kSoCDescLib.inf | 4 +-
.../RealTimeClockLib/RealTimeClockLib.inf | 4 +-
.../Marvell/Documentation/PortingGuide.txt | 114 +++++-----
.../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-
.../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +-
.../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +-
.../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +-
.../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-
.../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +-
.../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +-
Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-
.../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +-
.../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +-
.../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-
.../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +-
.../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +-
.../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +-
.../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 +--
Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +-
Silicon/Marvell/Library/MppLib/MppLib.inf | 94 ++++----
.../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +-
.../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +-
Silicon/Marvell/Marvell.dec | 208 ------------------
.../Include/IndustryStandard/MvSmc.h | 0
.../Include/Library/ArmadaBoardDescLib.h | 0
.../Include/Library/ArmadaIcuLib.h | 0
.../Include/Library/ArmadaSoCDescLib.h | 0
.../Include/Library/MppLib.h | 0
.../Include/Library/MvComPhyLib.h | 0
.../Include/Library/MvGpioLib.h | 0
.../Include/Library/NonDiscoverableInitLib.h | 0
.../Include/Library/SampleAtResetLib.h | 0
.../Include/Library/UtmiPhyLib.h | 0
.../Include/Protocol/BoardDesc.h | 0
.../Include/Protocol/Eeprom.h | 0
.../Include/Protocol/Mdio.h | 0
.../Include/Protocol/MvI2c.h | 0
.../Include/Protocol/MvPhy.h | 0
.../Include/Protocol/Spi.h | 0
.../Include/Protocol/SpiFlash.h | 0
.../MarvellSiliconPkg/MarvellSiliconPkg.dec | 207 +++++++++++++++++
.../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +-
.../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +-
.../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +-
82 files changed, 848 insertions(+), 852 deletions(-)
delete mode 100644 Silicon/Marvell/Marvell.dec
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/IndustryStandard/MvSmc.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaBoardDescLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaIcuLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaSoCDescLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MppLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvComPhyLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvGpioLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/NonDiscoverableInitLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/SampleAtResetLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/UtmiPhyLib.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/BoardDesc.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Eeprom.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Mdio.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvI2c.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvPhy.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Spi.h (100%)
rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/SpiFlash.h (100%)
create mode 100644 Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 5df7498f71..362175f59e 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -48,54 +48,54 @@
################################################################################
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
#CP110 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1
#MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2
# APN806-A0 MPP SET
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
# CP110 MPP SET - Router configuration
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 }
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }
- gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
- gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2
#SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
# ComPhy0
# 0: SGMII1 1.25 Gbps
# 1: USB3_HOST0 5 Gbps
@@ -103,36 +103,36 @@
# 3: SATA1 5 Gbps
# 4: USB3_HOST1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
#UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
#MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
#PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
#NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
#PciEmulation
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
#RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
index 20294ab43b..75331ae8e4 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index 946b9fd6d0..64623e33f8 100644
--- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -29,7 +29,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
index 2698bd6573..22a0040265 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -31,9 +31,6 @@
!include MdePkg/MdeLibs.dsc.inc
-[Components.common]
- Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
-
[Components.AARCH64]
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
@@ -48,63 +45,63 @@
################################################################################
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.4"
#MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# APN806-A0 MPP SET
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
# CP110 MPP SET - master
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# CP110 MPP SET - slave
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x21, 0x25 }
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 }
- gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
- gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x21, 0x25 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 }
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2
#SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: SATA0 5 Gbps
@@ -112,8 +109,8 @@
# 3: SATA1 5 Gbps
# 4: USB_HOST1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
# ComPhy1
# 0: PCIE0 5 Gbps
# 1: SATA0 5 Gbps
@@ -121,36 +118,36 @@
# 3: SATA1 5 Gbps
# 4: PCIE1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) }
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
#UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
#MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 }
#PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
#NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SFI), $(PHY_RGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SFI), $(PHY_RGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
#PciEmulation
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
#RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.inf b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.inf
index 07ee65dfa4..302e0f832f 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.inf
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index fb303f3d89..261f2114c4 100644
--- a/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++ b/Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -30,7 +30,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
index dfbdc84448..c93b3077c7 100644
--- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
index 27a0214622..e0c84138b7 100644
--- a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
index e4d4c8e073..61bfdc8eb6 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -14,47 +14,47 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2
# APN807 MPP
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
# CP115 #0 MPP
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0xA }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0xA }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
# SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -62,39 +62,39 @@
# 3: PCIE0 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SATA1 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
# PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
# RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
# Variable store
- gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
index 7235b9f86e..8166f441b7 100644
--- a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
@@ -14,25 +14,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# CP115 #1 MPP
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7, 0x2, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7, 0x2, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy1
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -40,33 +40,33 @@
# 3: USB3_HOST1 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SATA1 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
# PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
index a0b90fac1c..909f0fbc78 100644
--- a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
@@ -14,25 +14,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|4
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4
# CP115 #2 MPP
- gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
- gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
# ComPhy1
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -40,33 +40,33 @@
# 3: USB3_HOST1 5 Gbps
# 4: SFI 10.31 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)}
- gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
# PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
index ff91d10142..dc18e94dbc 100644
--- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
@@ -69,10 +69,10 @@
[PcdsFixedAtBuild.common]
#Platform description
!if $(CN9130)
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A"
!elseif $(CN9131)
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A"
!elseif $(CN9132)
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A"
!endif
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index f7cfb3684d..e4f0cf6bd6 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -23,7 +23,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index 9196300572..469ccc7083 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -48,54 +48,54 @@
################################################################################
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
#MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# APN806-A0 MPP SET
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
# CP110 MPP SET - master
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# CP110 MPP SET - slave
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
#SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -103,8 +103,8 @@
# 3: PCIE0 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SATA1 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
# ComPhy1
# 0: SGMII1 1.25 Gbps
# 1: SATA0 5 Gbps
@@ -112,36 +112,36 @@
# 3: SATA1 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SGMII2 3.125 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
#UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
#MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
#PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
#NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
#PciEmulation
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
#RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
index 4ebe4c3883..3fbfd9f5c7 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.inf
@@ -22,7 +22,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index 469a0323ca..824e10f0b2 100644
--- a/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++ b/Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -30,7 +30,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
index ea13ff7ad7..00bf3ff550 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
@@ -23,7 +23,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
index ad0983087d..0b02740242 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
@@ -15,7 +15,7 @@
################################################################################
[PcdsFixedAtBuild.common]
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
# ComPhy0
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -23,32 +23,32 @@
# 3: PCIE0 5 Gbps
# 4: SFI 10.31 Gbps
# 5: SGMII2 3.125 Gbps
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }
# PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
index c6b0cefa8d..e9a6e34a32 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
@@ -15,25 +15,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|2
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|3
# CP115 #1 MPP
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x8, 0x8, 0x9 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x8, 0x8, 0x9 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
# ComPhy1
# 0: PCIE0 5 Gbps
# 1: PCIE0 5 Gbps
@@ -41,24 +41,24 @@
# 3: SATA1 5 Gbps
# 4: PCIE1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
index 34f9a3f2fb..74695221c4 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
@@ -15,25 +15,25 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|3
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|4
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|4
# CP115 #2 MPP
- gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
- gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0x2, 0x2, 0x8, 0x8, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
# ComPhy2
# 0: PCIE0 5 Gbps
# 1: USB3_HOST0 5 Gbps
@@ -41,24 +41,24 @@
# 3: SATA1 5 Gbps
# 4: PCIE1 5 Gbps
# 5: PCIE2 5 Gbps
- gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
- gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
# NET
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
index 17463c09c6..31e553ee41 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
@@ -15,53 +15,53 @@
################################################################################
[PcdsFixedAtBuild.common]
# CP115 count
- gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1
# MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|2
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2
# APN807 MPP
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
# CP115 #0 MPP
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0xE, 0xE, 0xE, 0xE }
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
# I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
# SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
# NonDiscoverableDevices
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
# RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
# Variable store
- gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000
[PcdsDynamicDefault.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E0000
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
index 6cb82acb13..b995ce0ef1 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
@@ -52,6 +52,6 @@
[PcdsFixedAtBuild.common]
#Platform description
- gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Board"
- gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Board"
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
index c58ba8397a..a388ecab02 100644
--- a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -24,7 +24,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf b/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf
index 1880416e42..8f71612e54 100644
--- a/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf
+++ b/Silicon/Marvell/Applications/EepromCmd/EepromCmd.inf
@@ -20,7 +20,7 @@
MdePkg/MdePkg.dec
ShellPkg/ShellPkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
UefiLib
diff --git a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf
index ee03d450d5..41e1d26140 100644
--- a/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf
+++ b/Silicon/Marvell/Applications/FirmwareUpdate/FUpdate.inf
@@ -20,7 +20,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
ShellPkg/ShellPkg.dec
[LibraryClasses]
@@ -39,8 +39,8 @@
UefiRuntimeServicesTableLib
[Pcd]
- gMarvellTokenSpaceGuid.PcdSpiFlashCs
- gMarvellTokenSpaceGuid.PcdSpiFlashMode
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode
[Protocols]
gEfiBlockIoProtocolGuid
diff --git a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf
index 3a6a2115f8..8340e43723 100644
--- a/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf
+++ b/Silicon/Marvell/Applications/SpiTool/SpiFlashCmd.inf
@@ -21,7 +21,7 @@
MdePkg/MdePkg.dec
ShellPkg/ShellPkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
UefiLib
@@ -39,8 +39,8 @@
FileHandleLib
[Pcd]
- gMarvellTokenSpaceGuid.PcdSpiFlashCs
- gMarvellTokenSpaceGuid.PcdSpiFlashMode
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode
[Protocols]
gMarvellSpiFlashProtocolGuid
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
index f3cce52e96..416b4cd63e 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf
@@ -32,7 +32,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
index 7750817e1b..f7ed7f2350 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
@@ -32,7 +32,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
index 98e5cc8b6e..c8cdea2b7d 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf
@@ -33,7 +33,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index a135cb88b8..9711a8d6a7 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -373,31 +373,31 @@
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
# ARM-TF region reservation
- gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x4000000
- gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x200000
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase|0x4000000
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize|0x200000
# Additional region reservation (e.g. for PEI stack base)
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000
# OP-TEE region reservation
- gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000
- gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000
# SMBIOS/DMI
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
- gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1"
+ gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion|"EDK2 SH 1.1"
# TRNG
- gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
+ gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
#
# Variable store - default values
#
- gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000
- gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE
- gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|TRUE
+ gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
diff --git a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf
index 4c766eeff8..7ba9ec9d26 100644
--- a/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf
+++ b/Silicon/Marvell/Armada7k8k/Drivers/Armada7k8kRngDxe/Armada7k8kRngDxe.inf
@@ -20,7 +20,7 @@
[Packages]
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseMemoryLib
@@ -29,7 +29,7 @@
UefiDriverEntryPoint
[Pcd]
- gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress
[Protocols]
gEfiRngProtocolGuid ## PRODUCES
diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
index 398baebcf5..93f1f5c822 100644
--- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
+++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf
@@ -23,7 +23,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaBoardDescLib
@@ -42,8 +42,8 @@
gEfiEventReadyToBootGuid
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdProductManufacturer
- gMarvellTokenSpaceGuid.PcdProductPlatformName
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName
[Protocols]
gMarvellPlatformInitCompleteProtocolGuid ## PRODUCES
diff --git a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/PlatformFlashAccessLib.inf b/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/PlatformFlashAccessLib.inf
index 69a7b71c51..b678a24028 100644
--- a/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/PlatformFlashAccessLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Feature/Capsule/PlatformFlashAccessLib/PlatformFlashAccessLib.inf
@@ -24,7 +24,7 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
SignedCapsulePkg/SignedCapsulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
@@ -38,8 +38,8 @@
UefiRuntimeServicesTableLib
[Pcd]
- gMarvellTokenSpaceGuid.PcdSpiFlashCs
- gMarvellTokenSpaceGuid.PcdSpiFlashMode
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode
[Protocols]
gMarvellSpiFlashProtocolGuid
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
index 8b77a07ab3..51127cfbd9 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
@@ -17,7 +17,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaBoardDescLib
@@ -45,7 +45,7 @@
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore
- gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdConfigSpaceBaseAddress
[Ppis]
gArmMpCoreInfoPpiGuid
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
index f0b469ee55..e48ab5857d 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
@@ -24,7 +24,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmPlatformLib
@@ -36,9 +36,9 @@
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdArmTFRegionBase
- gMarvellTokenSpaceGuid.PcdArmTFRegionSize
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize
- gMarvellTokenSpaceGuid.PcdOpTeeRegionBase
- gMarvellTokenSpaceGuid.PcdOpTeeRegionSize
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf
index 8fcb133e99..5877cb345e 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridgeLib.inf
@@ -27,7 +27,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
index d3876791e9..40e74be6bf 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.inf
@@ -25,7 +25,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaBoardDescLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
index 512cbf5f7e..09986828ec 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf
@@ -17,7 +17,7 @@
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.inf
index d5809c6789..15a7a505d8 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.inf
@@ -21,7 +21,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
@@ -29,4 +29,4 @@
PcdLib
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdMaxCpCount
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount
diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf
index 733827e61a..7dfa109e56 100644
--- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf
@@ -29,7 +29,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
@@ -44,7 +44,7 @@
gEfiEventVirtualAddressChangeGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress
[Depex.common.DXE_RUNTIME_DRIVER]
gEfiCpuArchProtocolGuid
diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt
index 9dee5c89fa..24cf5cff0a 100644
--- a/Silicon/Marvell/Documentation/PortingGuide.txt
+++ b/Silicon/Marvell/Documentation/PortingGuide.txt
@@ -70,7 +70,7 @@ COMPHY configuration
====================
In order to configure ComPhy library, following PCDs are available:
- - gMarvellTokenSpaceGuid.PcdComPhyDevices
+ - gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices
This array indicates, which ones of the ComPhy chips defined in
MVHW_COMPHY_DESC template will be configured.
@@ -84,7 +84,7 @@ defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h
- - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes
(Array of types - currently supported are:
CP_UNCONNECTED 0x0
@@ -112,7 +112,7 @@ defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
CP_RXAUI1 0x16
CP_SFI 0x17 )
- - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds
(Array of speeds - currently supported are:
CP_1_25G 0x1
@@ -126,7 +126,7 @@ defined numbers for SPEED/TYPE/INVERT, whose description can be found in:
CP_6_25G 0x9
CP_10_3125G 0xA )
- - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags
(Array of lane inversion types - currently supported are:
CP_NO_INVERT 0x0
@@ -138,9 +138,9 @@ Example
-------
#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
PHY Driver configuration
@@ -148,13 +148,13 @@ PHY Driver configuration
MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
Currently only 1512 and 1112 series PHYs are supported. Following PCDs are required:
- - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+ - gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg
(boolean - if true, driver waits for autonegotiation on startup)
- - gMarvellTokenSpaceGuid.PcdPhyDeviceIds
+ - gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds
(list of values corresponding to MV_PHY_DEVICE_ID enum)
- - gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+ - gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses
(addresses of PHY devices)
- - gMarvellTokenSpaceGuid.PcdPhy2MdioController
+ - gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController
(Array specifying, which Mdio controller the PHY is attached to)
@@ -169,11 +169,11 @@ It should be extended when adding support for other PHY models.
Disable autonegotiation:
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
assuming, that PHY models are 1512 and 1112 for two consecutive ports:
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x1 }
MDIO configuration
@@ -181,7 +181,7 @@ MDIO configuration
MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ and
EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required:
- - gMarvellTokenSpaceGuid.PcdMdioControllers
+ - gMarvellSiliconTokenSpaceGuid.PcdMdioControllers
(Array with used controllers
Set to 0x1 for enabled, 0x0 for disabled)
@@ -194,17 +194,17 @@ In order to enable driver on a new platform, following steps need to be taken:
- add following line to .fdf file:
INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
- add PCDs with relevant values to .dsc file:
- - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
(addresses of I2C slave devices on bus)
- - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
(buses to which accoring slaves are attached)
- - gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2
(number of SoC's I2C buses)
- - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 }
(array with used controllers)
- - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|200000000
(I2C host controller clock frequency)
- - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ - gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
(baud rate used in I2C transmission)
@@ -213,13 +213,13 @@ PciEmulation configuration
Installation of various NonDiscoverable devices via PciEmulation driver is performed
via set of PCDs. Following are available:
- - gMarvellTokenSpaceGuid.PcdPciEXhci
+ - gMarvellSiliconTokenSpaceGuid.PcdPciEXhci
(Indicates, which Xhci devices are used)
- - gMarvellTokenSpaceGuid.PcdPciEAhci
+ - gMarvellSiliconTokenSpaceGuid.PcdPciEAhci
(Indicates, which Ahci devices are used)
- - gMarvellTokenSpaceGuid.PcdPciESdhci
+ - gMarvellSiliconTokenSpaceGuid.PcdPciESdhci
(Indicates, which Sdhci devices are used)
All above PCD's correspond to hardware description in a dedicated structure:
@@ -235,15 +235,15 @@ Example
Assuming we want to enable second XHCI port and one SDHCI port on Armada
70x0 board, following needs to be declared:
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
SATA configuration
==================
There is one additional PCD for AHCI:
- - gMarvellTokenSpaceGuid.PcdSataBaseAddress
+ - gMarvellSiliconTokenSpaceGuid.PcdSataBaseAddress
(Base address of SATA controller register space - used in SATA ComPhy init
sequence)
@@ -253,14 +253,14 @@ Pp2Dxe configuration
Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
are required to operate:
- - gMarvellTokenSpaceGuid.PcdPp2Controllers
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers
(Array with used controllers
Set to 0x1 for enabled, 0x0 for disabled)
- - gMarvellTokenSpaceGuid.PcdPp2Port2Controller
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller
(Array specifying, to which controller the port belongs to)
- - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes
(Indicates speed of the network interface:
PHY_RGMII 0x0
@@ -273,22 +273,22 @@ are required to operate:
PHY_RXAUI 0x7
PHY_SFI 0x8 )
- - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes
(Array specifying, to which PHY from
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds is used. If none,
e.g. in 10G SFI in-band link detection, 0xFF value must
be specified)
- - gMarvellTokenSpaceGuid.PcdPp2PortIds
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds
(Identificators of PP2 ports)
- - gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes
(Indexes used in GOP operation)
- - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
(Set to 0x1 for always-up interface, 0x0 otherwise)
- - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+ - gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed
(Indicates speed of the network interface:
PHY_SPEED_10 0x1
@@ -302,11 +302,11 @@ UTMI PHY configuration
======================
In order to configure UTMI, following PCDs are available:
- - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
+ - gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled
(Array with used controllers
Set to 0x1 for enabled, 0x0 for disabled)
- - gMarvellTokenSpaceGuid.PcdUtmiPortType
+ - gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType
(Indicates type of the connected USB port:
UTMI_USB_HOST0 0x0
@@ -317,29 +317,29 @@ Example
-------
# UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
SPI driver configuration
========================
Following PCDs are available for configuration of spi driver:
- - gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+ - gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency
(Frequency (in Hz) of SPI clock)
- - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+ - gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency
(Max SCLK line frequency (in Hz) (max transfer frequency) )
SpiFlash configuration
======================
Folowing PCDs for spi flash driver configuration must be set properly:
- - gMarvellTokenSpaceGuid.PcdSpiFlashMode
+ - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode
(Default SCLK mode (see SPI_MODE enum in file
edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h))
- - gMarvellTokenSpaceGuid.PcdSpiFlashCs
+ - gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs
(Chip select used for communication with the Flash)
MPP configuration
@@ -350,7 +350,7 @@ In order to set desired pin multiplexing, .dsc file needs to be modified.
Documentation/Build.txt for currently supported {platftorm_name} )
Following PCDs are available:
- - gMarvellTokenSpaceGuid.PcdMppChipCount
+ - gMarvellSiliconTokenSpaceGuid.PcdMppChipCount
(Indicates how many different chips are placed on board. So far up to 4 chips
are supported)
@@ -360,37 +360,37 @@ Every MPP PCD has <Num> part where
Below is example for the first chip (Chip0).
- - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag
(Indicates that register order is reversed. (Needs to be used only for AP806-Z1) )
- - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress
(This is base address for MPP configuration register)
- - gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount
(Defines how many MPP pins are available)
- - gMarvellTokenSpaceGuid.PcdChip0MppSel0
- - gMarvellTokenSpaceGuid.PcdChip0MppSel1
- - gMarvellTokenSpaceGuid.PcdChip0MppSel2
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1
+ - gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2
(This registers defines functions of 10 pins in ascending order)
Examples
--------
# APN806-A0 MPP SET
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
- gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppRegCount|3
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
Set pin 6 and 7 to 0xa function:
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
Ramdisk configuration
=====================
There is one PCD available for Ramdisk configuration
- - gMarvellTokenSpaceGuid.PcdRamDiskSize
+ - gMarvellSiliconTokenSpaceGuid.PcdRamDiskSize
(Defines size of Ramdisk)
diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf
index 75ecae1b98..0dd17f7b56 100644
--- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf
+++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf
@@ -18,7 +18,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaBoardDescLib
@@ -32,14 +32,14 @@
gMarvellBoardDescProtocolGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdComPhyDevices
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled
- gMarvellTokenSpaceGuid.PcdPciEAhci
- gMarvellTokenSpaceGuid.PcdPciESdhci
- gMarvellTokenSpaceGuid.PcdPciEXhci
- gMarvellTokenSpaceGuid.PcdPp2Controllers
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled
- gMarvellTokenSpaceGuid.PcdUtmiPortType
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType
[Depex]
TRUE
diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
index 6f36c2db2e..db111a2c57 100644
--- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
@@ -21,7 +21,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaSoCDescLib
diff --git a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
index c202d811f2..0f00698c55 100644
--- a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+++ b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
@@ -21,7 +21,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf b/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf
index cfe9db9c1c..c5f6aa7833 100644
--- a/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf
+++ b/Silicon/Marvell/Drivers/I2c/MvEepromDxe/MvEepromDxe.inf
@@ -18,7 +18,7 @@
ArmPlatformPkg/ArmPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
@@ -36,8 +36,8 @@
gMarvellEepromProtocolGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdEepromI2cAddresses
- gMarvellTokenSpaceGuid.PcdEepromI2cBuses
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses
[Depex]
TRUE
diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
index f631fbe797..d73f2433fc 100755
--- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
@@ -19,7 +19,7 @@
MdeModulePkg/MdeModulePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPkg/ArmPkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
IoLib
@@ -38,12 +38,12 @@
gMarvellBoardDescProtocolGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency
- gMarvellTokenSpaceGuid.PcdI2cBaudRate
- gMarvellTokenSpaceGuid.PcdI2cBusCount
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount
[Guids]
gEfiEndOfDxeEventGroupGuid
diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
index f4511a9288..196d119586 100644
--- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
+++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf
@@ -21,7 +21,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf
index abf84af612..b8e5d30fc3 100644
--- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf
+++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf
@@ -19,7 +19,7 @@
ArmPlatformPkg/ArmPlatformPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
@@ -36,11 +36,11 @@
gMarvellPhyProtocolGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled
- gMarvellTokenSpaceGuid.PcdPhy2MdioController
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg
[Depex]
TRUE
diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
index 17a2a88d62..bd8b557c1a 100644
--- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -21,7 +21,7 @@
MdeModulePkg/MdeModulePkg.dec
NetworkPkg/NetworkPkg.dec
ArmPkg/ArmPkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DmaLib
@@ -47,13 +47,13 @@
gMarvellPhyProtocolGuid
[Pcd]
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller
- gMarvellTokenSpaceGuid.PcdPp2PortIds
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds
[Depex]
TRUE
diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf
index af266ee083..88fc3f17bb 100644
--- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf
+++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf
@@ -19,7 +19,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
NonDiscoverableDeviceRegistrationLib
diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf
index 18f1b164fd..4bf8718c36 100644
--- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf
+++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf
@@ -33,7 +33,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
index 582c0faf25..682de9aeec 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -22,7 +22,7 @@
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
@@ -36,12 +36,12 @@
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
- gMarvellTokenSpaceGuid.PcdProductManufacturer
- gMarvellTokenSpaceGuid.PcdProductPlatformName
- gMarvellTokenSpaceGuid.PcdProductSerial
- gMarvellTokenSpaceGuid.PcdProductVersion
- gMarvellTokenSpaceGuid.PcdFirmwareVendor
- gMarvellTokenSpaceGuid.PcdFirmwareVersion
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName
+ gMarvellSiliconTokenSpaceGuid.PcdProductSerial
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion
+ gMarvellSiliconTokenSpaceGuid.PcdFirmwareVendor
+ gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion
[Protocols]
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
diff --git a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
index b5d38da11b..902a3f4fff 100644
--- a/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
+++ b/Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf
@@ -18,7 +18,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
BaseLib
@@ -52,9 +52,9 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
- gMarvellTokenSpaceGuid.PcdSpiMemoryBase
- gMarvellTokenSpaceGuid.PcdSpiMemoryMapped
- gMarvellTokenSpaceGuid.PcdSpiVariableOffset
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped
+ gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf b/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf
index c6e93b82a1..ecaf5ad05f 100644
--- a/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf
+++ b/Silicon/Marvell/Drivers/Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf
@@ -17,7 +17,7 @@
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf b/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf
index 36697d4fa4..10142105f8 100644
--- a/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf
+++ b/Silicon/Marvell/Drivers/Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf
@@ -17,7 +17,7 @@
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
@@ -32,9 +32,9 @@
UefiRuntimeLib
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
- gMarvellTokenSpaceGuid.PcdSpiRegBase
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase
[Protocols]
gMarvellSpiMasterProtocolGuid
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
index c9a00d79d7..13944a865d 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf
@@ -17,7 +17,7 @@
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmLib
@@ -37,24 +37,24 @@
gMarvellBoardDescProtocolGuid ## CONSUMES
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdComPhyDevices
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices
#Chip0
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
- gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags
#Chip1
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds
- gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyInvFlags
#Chip2
- gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes
- gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds
- gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyInvFlags
#Chip3
- gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes
- gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds
- gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyTypes
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhySpeeds
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyInvFlags
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Library/IcuLib/IcuLib.inf
index a2adf412a7..d0817b4fb3 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.inf
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf
@@ -21,7 +21,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmadaSoCDescLib
@@ -30,4 +30,4 @@
PcdLib
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdMaxCpCount
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount
diff --git a/Silicon/Marvell/Library/MppLib/MppLib.inf b/Silicon/Marvell/Library/MppLib/MppLib.inf
index 4c1887a472..7bfbfee825 100644
--- a/Silicon/Marvell/Library/MppLib/MppLib.inf
+++ b/Silicon/Marvell/Library/MppLib/MppLib.inf
@@ -15,7 +15,7 @@
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmLib
@@ -28,57 +28,57 @@
MppLib.c
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdMppChipCount
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount
- gMarvellTokenSpaceGuid.PcdChip0MppSel0
- gMarvellTokenSpaceGuid.PcdChip0MppSel1
- gMarvellTokenSpaceGuid.PcdChip0MppSel2
- gMarvellTokenSpaceGuid.PcdChip0MppSel3
- gMarvellTokenSpaceGuid.PcdChip0MppSel4
- gMarvellTokenSpaceGuid.PcdChip0MppSel5
- gMarvellTokenSpaceGuid.PcdChip0MppSel6
- gMarvellTokenSpaceGuid.PcdChip0MppSel7
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel3
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel4
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel5
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel6
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel7
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount
- gMarvellTokenSpaceGuid.PcdChip1MppSel0
- gMarvellTokenSpaceGuid.PcdChip1MppSel1
- gMarvellTokenSpaceGuid.PcdChip1MppSel2
- gMarvellTokenSpaceGuid.PcdChip1MppSel3
- gMarvellTokenSpaceGuid.PcdChip1MppSel4
- gMarvellTokenSpaceGuid.PcdChip1MppSel5
- gMarvellTokenSpaceGuid.PcdChip1MppSel6
- gMarvellTokenSpaceGuid.PcdChip1MppSel7
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel7
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount
- gMarvellTokenSpaceGuid.PcdChip2MppSel0
- gMarvellTokenSpaceGuid.PcdChip2MppSel1
- gMarvellTokenSpaceGuid.PcdChip2MppSel2
- gMarvellTokenSpaceGuid.PcdChip2MppSel3
- gMarvellTokenSpaceGuid.PcdChip2MppSel4
- gMarvellTokenSpaceGuid.PcdChip2MppSel5
- gMarvellTokenSpaceGuid.PcdChip2MppSel6
- gMarvellTokenSpaceGuid.PcdChip2MppSel7
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel7
- gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag
- gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress
- gMarvellTokenSpaceGuid.PcdChip3MppPinCount
- gMarvellTokenSpaceGuid.PcdChip3MppSel0
- gMarvellTokenSpaceGuid.PcdChip3MppSel1
- gMarvellTokenSpaceGuid.PcdChip3MppSel2
- gMarvellTokenSpaceGuid.PcdChip3MppSel3
- gMarvellTokenSpaceGuid.PcdChip3MppSel4
- gMarvellTokenSpaceGuid.PcdChip3MppSel5
- gMarvellTokenSpaceGuid.PcdChip3MppSel6
- gMarvellTokenSpaceGuid.PcdChip3MppSel7
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel7
- gMarvellTokenSpaceGuid.PcdPciESdhci
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci
[BuildOptions]
*_*_*_CC_FLAGS = -fno-stack-protector
diff --git a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf b/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf
index 24db268bc7..0fefbc0156 100644
--- a/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf
+++ b/Silicon/Marvell/Library/MvGpioLib/MvGpioLib.inf
@@ -20,7 +20,7 @@
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
DebugLib
diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
index f0051f47e1..26fbdf4438 100644
--- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
+++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf
@@ -17,7 +17,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[LibraryClasses]
ArmLib
diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
deleted file mode 100644
index 482a90da25..0000000000
--- a/Silicon/Marvell/Marvell.dec
+++ /dev/null
@@ -1,208 +0,0 @@
-# Copyright (C) 2016 Marvell International Ltd.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-[Defines]
- DEC_SPECIFICATION = 0x00010005
- PACKAGE_NAME = OpenPlatformMarvellPkg
- PACKAGE_GUID = c372916e-83ad-4b2a-8410-bbc31bd9e68f
- PACKAGE_VERSION = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-# Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-#
-################################################################################
-
-[Includes]
- Include
-
-[Guids.common]
- gMarvellTokenSpaceGuid = { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } }
-
- gShellEepromHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } }
- gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }
- gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
-
-[LibraryClasses]
- ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h
- ArmadaIcuLib|Include/Library/ArmadaIcuLib.h
- ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h
- MvGpioLib|Include/Library/MvGpioLib.h
- NonDiscoverableInitLib|Include/Library/NonDiscoverableInitLib.h
- SampleAtResetLib|Include/Library/SampleAtResetLib.h
-
-[Protocols]
- # installed as a protocol by PlatInitDxe to force ordering between DXE drivers
- # that depend on the lowlevel platform initialization having been completed
- gMarvellPlatformInitCompleteProtocolGuid = { 0x465b8cf7, 0x016f, 0x4ba6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } }
-
-[PcdsFixedAtBuild.common]
-#Board description
- gMarvellTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072
-
-#MPP
- gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001
-
- gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x30000002
- gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003
- gMarvellTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004
- gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005
- gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006
- gMarvellTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007
- gMarvellTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008
- gMarvellTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009
- gMarvellTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010
- gMarvellTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011
- gMarvellTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012
-
- gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x30000013
- gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014
- gMarvellTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015
- gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016
- gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017
- gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0 }|VOID*|0x30000018
- gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x0 }|VOID*|0x30000019
- gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0 }|VOID*|0x30000020
- gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0 }|VOID*|0x30000021
- gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0x0 }|VOID*|0x30000022
- gMarvellTokenSpaceGuid.PcdChip1MppSel7|{ 0x0 }|VOID*|0x30000023
-
- gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x30000024
- gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025
- gMarvellTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026
- gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0 }|VOID*|0x30000027
- gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0 }|VOID*|0x30000028
- gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0 }|VOID*|0x30000029
- gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0 }|VOID*|0x30000030
- gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0 }|VOID*|0x30000031
- gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0 }|VOID*|0x30000032
- gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0 }|VOID*|0x30000033
- gMarvellTokenSpaceGuid.PcdChip2MppSel7|{ 0x0 }|VOID*|0x30000034
-
- gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x30000035
- gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036
- gMarvellTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037
- gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0 }|VOID*|0x30000038
- gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0 }|VOID*|0x30000039
- gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0 }|VOID*|0x30000040
- gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0 }|VOID*|0x30000041
- gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0 }|VOID*|0x30000042
- gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0 }|VOID*|0x30000043
- gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0x0 }|VOID*|0x30000044
- gMarvellTokenSpaceGuid.PcdChip3MppSel7|{ 0x0 }|VOID*|0x30000045
-
-#I2C
- gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x3000046
- gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184
- gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050
- gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185
- gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3000047
- gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048
- gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049
- gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183
-
-#SPI
- gMarvellTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051
- gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059
- gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|TRUE|BOOLEAN|0x3000060
- gMarvellTokenSpaceGuid.PcdSpiVariableOffset|0|UINT32|0x3000061
- gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052
- gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053
-
- gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057
- gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058
-
-#ComPhy
- gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098
-
- #Chip0
- gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068
- gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069
- gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070
-
- #Chip1
- gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105
- gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106
- gMarvellTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107
-
- #Chip2
- gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140
- gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141
- gMarvellTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142
-
- #Chip3
- gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175
- gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176
- gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177
-
-#UtmiPhy
- gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x0 }|VOID*|0x30000206
- gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207
-
-#MDIO
- gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x0 }|VOID*|0x3000043
-
-#PHY
- gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000027
- gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095
- gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
- gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070
-
-#NET
- gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028
- gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
- gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
- gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
- gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3000044
- gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045
- gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D
- gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
-
-#PciEmulation
- gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
- gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
- gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
-
-#Platform description
- gMarvellTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semihalf"|VOID*|0x50000104
- gMarvellTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105
- gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100
- gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board"|VOID*|0x50000101
- gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103
- gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*|0x50000102
-
-#RTC
- gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052
-
-#TRNG
- gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
-
-#Configuration space
- gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054
-
- #
- # The secure firmware may occupy a DRAM region that is accessible by the
- # normal world. These PCDs describe such a region, which will be converted
- # to 'reserved' memory before DXE is entered.
- #
- gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000
- gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|0x50000002
- gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|0x50000003
- gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004
- gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005
-
-[Protocols]
- gMarvellBoardDescProtocolGuid = { 0xebed8738, 0xd4a6, 0x4001, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }}
- gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
- gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
- gMarvellPhyProtocolGuid = { 0x32f48a43, 0x37e3, 0x4acf, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }}
- gMarvellSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}
- gMarvellSpiFlashProtocolGuid = { 0x9accb423, 0x5bd2, 0x4fca, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }}
-
diff --git a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h b/Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/MvSmc.h
similarity index 100%
rename from Silicon/Marvell/Include/IndustryStandard/MvSmc.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/IndustryStandard/MvSmc.h
diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaBoardDescLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaBoardDescLib.h
diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaIcuLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/ArmadaIcuLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaIcuLib.h
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaSoCDescLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/ArmadaSoCDescLib.h
diff --git a/Silicon/Marvell/Include/Library/MppLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/MppLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/MppLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MppLib.h
diff --git a/Silicon/Marvell/Include/Library/MvComPhyLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvComPhyLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/MvComPhyLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvComPhyLib.h
diff --git a/Silicon/Marvell/Include/Library/MvGpioLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvGpioLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/MvGpioLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/MvGpioLib.h
diff --git a/Silicon/Marvell/Include/Library/NonDiscoverableInitLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/NonDiscoverableInitLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/NonDiscoverableInitLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/NonDiscoverableInitLib.h
diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/SampleAtResetLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/SampleAtResetLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/SampleAtResetLib.h
diff --git a/Silicon/Marvell/Include/Library/UtmiPhyLib.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Library/UtmiPhyLib.h
similarity index 100%
rename from Silicon/Marvell/Include/Library/UtmiPhyLib.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Library/UtmiPhyLib.h
diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/BoardDesc.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/BoardDesc.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/BoardDesc.h
diff --git a/Silicon/Marvell/Include/Protocol/Eeprom.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Eeprom.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/Eeprom.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Eeprom.h
diff --git a/Silicon/Marvell/Include/Protocol/Mdio.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Mdio.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/Mdio.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Mdio.h
diff --git a/Silicon/Marvell/Include/Protocol/MvI2c.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvI2c.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/MvI2c.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvI2c.h
diff --git a/Silicon/Marvell/Include/Protocol/MvPhy.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvPhy.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/MvPhy.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/MvPhy.h
diff --git a/Silicon/Marvell/Include/Protocol/Spi.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Spi.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/Spi.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/Spi.h
diff --git a/Silicon/Marvell/Include/Protocol/SpiFlash.h b/Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/SpiFlash.h
similarity index 100%
rename from Silicon/Marvell/Include/Protocol/SpiFlash.h
rename to Silicon/Marvell/MarvellSiliconPkg/Include/Protocol/SpiFlash.h
diff --git a/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec b/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
new file mode 100644
index 0000000000..1e17152f13
--- /dev/null
+++ b/Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
@@ -0,0 +1,207 @@
+# Copyright (C) 2016 Marvell International Ltd.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = MarvellSiliconPkg
+ PACKAGE_GUID = c372916e-83ad-4b2a-8410-bbc31bd9e68f
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+
+[Includes]
+ Include
+
+[Guids.common]
+ gMarvellSiliconTokenSpaceGuid = { 0xf995c6c8, 0xbc9b, 0x4e93, { 0xbd, 0xcf, 0x49, 0x90, 0xc6, 0xe7, 0x8c, 0x7f } }
+
+ gShellEepromHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } }
+ gShellFUpdateHiiGuid = { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } }
+ gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
+
+[LibraryClasses]
+ ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h
+ ArmadaIcuLib|Include/Library/ArmadaIcuLib.h
+ ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h
+ MvGpioLib|Include/Library/MvGpioLib.h
+ NonDiscoverableInitLib|Include/Library/NonDiscoverableInitLib.h
+ SampleAtResetLib|Include/Library/SampleAtResetLib.h
+
+[Protocols]
+ # installed as a protocol by PlatInitDxe to force ordering between DXE drivers
+ # that depend on the lowlevel platform initialization having been completed
+ gMarvellPlatformInitCompleteProtocolGuid = { 0x465b8cf7, 0x016f, 0x4ba6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } }
+
+[PcdsFixedAtBuild.common]
+#Board description
+ gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072
+
+#MPP
+ gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001
+
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE|BOOLEAN|0x30000002
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0|UINT64|0x30000003
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|0|UINT32|0x30000004
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011
+ gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012
+
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE|BOOLEAN|0x30000013
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0|UINT64|0x30000014
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|0|UINT32|0x30000015
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0 }|VOID*|0x30000018
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0x0 }|VOID*|0x30000019
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0 }|VOID*|0x30000020
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x0 }|VOID*|0x30000021
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0x0 }|VOID*|0x30000022
+ gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel7|{ 0x0 }|VOID*|0x30000023
+
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE|BOOLEAN|0x30000024
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppBaseAddress|0|UINT64|0x30000025
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppPinCount|0|UINT32|0x30000026
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel0|{ 0x0 }|VOID*|0x30000027
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel1|{ 0x0 }|VOID*|0x30000028
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel2|{ 0x0 }|VOID*|0x30000029
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel3|{ 0x0 }|VOID*|0x30000030
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel4|{ 0x0 }|VOID*|0x30000031
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel5|{ 0x0 }|VOID*|0x30000032
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel6|{ 0x0 }|VOID*|0x30000033
+ gMarvellSiliconTokenSpaceGuid.PcdChip2MppSel7|{ 0x0 }|VOID*|0x30000034
+
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE|BOOLEAN|0x30000035
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppBaseAddress|0|UINT64|0x30000036
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppPinCount|0|UINT32|0x30000037
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel0|{ 0x0 }|VOID*|0x30000038
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel1|{ 0x0 }|VOID*|0x30000039
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel2|{ 0x0 }|VOID*|0x30000040
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel3|{ 0x0 }|VOID*|0x30000041
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel4|{ 0x0 }|VOID*|0x30000042
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel5|{ 0x0 }|VOID*|0x30000043
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel6|{ 0x0 }|VOID*|0x30000044
+ gMarvellSiliconTokenSpaceGuid.PcdChip3MppSel7|{ 0x0 }|VOID*|0x30000045
+
+#I2C
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x3000046
+ gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050
+ gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185
+ gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0 }|VOID*|0x3000047
+ gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049
+ gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183
+
+#SPI
+ gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0|UINT32|0x3000051
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryBase|0|UINT64|0x3000059
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMemoryMapped|TRUE|BOOLEAN|0x3000060
+ gMarvellSiliconTokenSpaceGuid.PcdSpiVariableOffset|0|UINT32|0x3000061
+ gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052
+ gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053
+
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057
+ gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058
+
+#ComPhy
+ gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098
+
+ #Chip0
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0x0 }|VOID*|0x30000068
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x0 }|VOID*|0x30000069
+ gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyInvFlags|{ 0x0 }|VOID*|0x30000070
+
+ #Chip1
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyTypes|{ 0x0 }|VOID*|0x30000105
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhySpeeds|{ 0x0 }|VOID*|0x30000106
+ gMarvellSiliconTokenSpaceGuid.PcdChip1ComPhyInvFlags|{ 0x0 }|VOID*|0x30000107
+
+ #Chip2
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyTypes|{ 0x0 }|VOID*|0x30000140
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhySpeeds|{ 0x0 }|VOID*|0x30000141
+ gMarvellSiliconTokenSpaceGuid.PcdChip2ComPhyInvFlags|{ 0x0 }|VOID*|0x30000142
+
+ #Chip3
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyTypes|{ 0x0 }|VOID*|0x30000175
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhySpeeds|{ 0x0 }|VOID*|0x30000176
+ gMarvellSiliconTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177
+
+#UtmiPhy
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x0 }|VOID*|0x30000206
+ gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207
+
+#MDIO
+ gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x0 }|VOID*|0x3000043
+
+#PHY
+ gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000027
+ gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095
+ gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
+ gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070
+
+#NET
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028
+ gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
+ gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3000044
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045
+ gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D
+ gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
+
+#PciEmulation
+ gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
+ gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
+ gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
+
+#Platform description
+ gMarvellSiliconTokenSpaceGuid.PcdFirmwareVendor|"EFI Development Kit II / Semihalf"|VOID*|0x50000104
+ gMarvellSiliconTokenSpaceGuid.PcdFirmwareVersion|"EDK II"|VOID*|0x50000105
+ gMarvellSiliconTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100
+ gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board"|VOID*|0x50000101
+ gMarvellSiliconTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103
+ gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*|0x50000102
+
+#RTC
+ gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052
+
+#TRNG
+ gMarvellSiliconTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053
+
+#Configuration space
+ gMarvellSiliconTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xF0000000|UINT64|0x50000054
+
+ #
+ # The secure firmware may occupy a DRAM region that is accessible by the
+ # normal world. These PCDs describe such a region, which will be converted
+ # to 'reserved' memory before DXE is entered.
+ #
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000
+ gMarvellSiliconTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|0x50000002
+ gMarvellSiliconTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|0x50000003
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004
+ gMarvellSiliconTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005
+
+[Protocols]
+ gMarvellBoardDescProtocolGuid = { 0xebed8738, 0xd4a6, 0x4001, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }}
+ gMarvellEepromProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }}
+ gMarvellMdioProtocolGuid = { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }}
+ gMarvellPhyProtocolGuid = { 0x32f48a43, 0x37e3, 0x4acf, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }}
+ gMarvellSpiMasterProtocolGuid = { 0x23de66a3, 0xf666, 0x4b3e, { 0xaa, 0xa2, 0x68, 0x9b, 0x18, 0xae, 0x2e, 0x19 }}
+ gMarvellSpiFlashProtocolGuid = { 0x9accb423, 0x5bd2, 0x4fca, { 0x9b, 0x4c, 0x2e, 0x65, 0xfc, 0x25, 0xdf, 0x21 }}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
index 2cd13aa2b6..d1e44beecc 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
@@ -33,7 +33,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
index 0c9fb82682..bc118b9fb3 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
@@ -34,7 +34,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
index 27e7294014..7b040ce7e8 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
@@ -37,7 +37,7 @@
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
- Silicon/Marvell/Marvell.dec
+ Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
--
2.34.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package
2023-11-02 3:45 ` [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package Narinder Dhillon
@ 2023-11-14 20:24 ` Marcin Wojtas via groups.io
0 siblings, 0 replies; 4+ messages in thread
From: Marcin Wojtas via groups.io @ 2023-11-14 20:24 UTC (permalink / raw)
To: devel, ndhillon
Hi Narinder,
Thanks for the patch.
2 comments: s/Retructure/Restructure/ from the commit title.
czw., 2 lis 2023 o 04:47 Narinder Dhillon <ndhillon@marvell.com> napisał(a):
>
> From: Narinder Dhillon <ndhillon@marvell.com>
>
> Current Marvell package structure makes it difficult to add new silicon
> packages that reuse common elements without creating nested DEC files.
>
> This patch creates a new MarvellSiliconPkg folder and moves the current
> common elements inside it.
>
> Also gMarvellTokenSpaceGuid has been renamed to
> gMarvellSiliconTokenSpaceGuid to align with new package name.
>
> Signed-off-by: Narinder Dhillon <ndhillon@marvell.com>
> ---
> .../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 ++++-----
> .../Armada70x0DbBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 ++++++-----
> .../Armada80x0DbBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Cn9130DbABoardDescLib.inf | 2 +-
> .../Cn9132DbABoardDescLib.inf | 2 +-
> Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++-----
> Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 +++---
> Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 +++---
> Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++-----
> .../Armada80x0McBinBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../BoardDescriptionLib.inf | 2 +-
> .../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 ++--
> .../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++---
> .../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++---
> .../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++---
> .../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Applications/EepromCmd/EepromCmd.inf | 2 +-
> .../Applications/FirmwareUpdate/FUpdate.inf | 6 +-
> .../Applications/SpiTool/SpiFlashCmd.inf | 6 +-
> .../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +-
> .../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +-
> .../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +-
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 +-
> .../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +-
> .../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +-
> .../PlatformFlashAccessLib.inf | 6 +-
> .../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +-
> .../Armada7k8kMemoryInitPeiLib.inf | 14 +-
> .../PciHostBridgeLib.inf | 2 +-
> .../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +-
> .../Armada7k8kSampleAtResetLib.inf | 2 +-
> .../Armada7k8kSoCDescLib.inf | 4 +-
> .../RealTimeClockLib/RealTimeClockLib.inf | 4 +-
> .../Marvell/Documentation/PortingGuide.txt | 114 +++++-----
> .../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-
> .../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +-
> .../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +-
> .../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +-
> .../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-
> .../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +-
> .../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +-
> Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-
> .../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +-
> .../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +-
> .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-
> .../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +-
> .../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +-
> .../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +-
> .../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 +--
> Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +-
> Silicon/Marvell/Library/MppLib/MppLib.inf | 94 ++++----
> .../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +-
> .../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +-
> Silicon/Marvell/Marvell.dec | 208 ------------------
> .../Include/IndustryStandard/MvSmc.h | 0
> .../Include/Library/ArmadaBoardDescLib.h | 0
> .../Include/Library/ArmadaIcuLib.h | 0
> .../Include/Library/ArmadaSoCDescLib.h | 0
> .../Include/Library/MppLib.h | 0
> .../Include/Library/MvComPhyLib.h | 0
> .../Include/Library/MvGpioLib.h | 0
> .../Include/Library/NonDiscoverableInitLib.h | 0
> .../Include/Library/SampleAtResetLib.h | 0
> .../Include/Library/UtmiPhyLib.h | 0
> .../Include/Protocol/BoardDesc.h | 0
> .../Include/Protocol/Eeprom.h | 0
> .../Include/Protocol/Mdio.h | 0
> .../Include/Protocol/MvI2c.h | 0
> .../Include/Protocol/MvPhy.h | 0
> .../Include/Protocol/Spi.h | 0
> .../Include/Protocol/SpiFlash.h | 0
> .../MarvellSiliconPkg/MarvellSiliconPkg.dec | 207 +++++++++++++++++
> .../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +-
> .../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +-
> .../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +-
> 82 files changed, 848 insertions(+), 852 deletions(-)
> delete mode 100644 Silicon/Marvell/Marvell.dec
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/IndustryStandard/MvSmc.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaBoardDescLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaIcuLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaSoCDescLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MppLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvComPhyLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvGpioLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/NonDiscoverableInitLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/SampleAtResetLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/UtmiPhyLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/BoardDesc.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Eeprom.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Mdio.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvI2c.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvPhy.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Spi.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/SpiFlash.h (100%)
> create mode 100644 Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
>
> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> index 5df7498f71..362175f59e 100644
> --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> @@ -48,54 +48,54 @@
> ################################################################################
> [PcdsFixedAtBuild.common]
> #Platform description
> - gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
> - gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
> + gMarvellSiliconTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
> + gMarvellSiliconTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
>
> #CP110 count
> - gMarvellTokenSpaceGuid.PcdMaxCpCount|1
> + gMarvellSiliconTokenSpaceGuid.PcdMaxCpCount|1
>
> #MPP
> - gMarvellTokenSpaceGuid.PcdMppChipCount|2
> + gMarvellSiliconTokenSpaceGuid.PcdMppChipCount|2
>
> # APN806-A0 MPP SET
> - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> - gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
> - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> + gMarvellSiliconTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> + gMarvellSiliconTokenSpaceGuid.PcdChip0MppPinCount|20
> + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
>
> # CP110 MPP SET - Router configuration
> - gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> - gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
> - gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
> - gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
> - gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppPinCount|64
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
> + gMarvellSiliconTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>
> # I2C
> - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 }
> - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }
> - gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
> - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
> - gMarvellTokenSpaceGuid.PcdI2cBusCount|2
> + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60, 0x21 }
> + gMarvellSiliconTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 }
> + gMarvellSiliconTokenSpaceGuid.PcdEepromI2cBuses|{ 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdI2cClockFrequency|250000000
> + gMarvellSiliconTokenSpaceGuid.PcdI2cBaudRate|100000
> + gMarvellSiliconTokenSpaceGuid.PcdI2cBusCount|2
>
> #SPI
> - gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
> - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
> - gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
> + gMarvellSiliconTokenSpaceGuid.PcdSpiRegBase|0xF2700680
> + gMarvellSiliconTokenSpaceGuid.PcdSpiMaxFrequency|10000000
> + gMarvellSiliconTokenSpaceGuid.PcdSpiClockFrequency|200000000
>
> - gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
> - gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
> + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashMode|3
> + gMarvellSiliconTokenSpaceGuid.PcdSpiFlashCs|0
>
> #ComPhy
> - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
> # ComPhy0
> # 0: SGMII1 1.25 Gbps
> # 1: USB3_HOST0 5 Gbps
> @@ -103,36 +103,36 @@
> # 3: SATA1 5 Gbps
> # 4: USB3_HOST1 5 Gbps
> # 5: PCIE2 5 Gbps
> - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
> - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
> + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
> + gMarvellSiliconTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
>
> #UtmiPhy
> - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> + gMarvellSiliconTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
>
> #MDIO
> - gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
>
> #PHY
> - gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
> - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> + gMarvellSiliconTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
>
> #NET
> - gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
> - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
> - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }
> - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
> - gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
> - gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
> - gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
> + gMarvellSiliconTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
>
> #PciEmulation
> - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
> - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
> - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
> + gMarvellSiliconTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>
> #RTC
> - gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
> + gMarvellSiliconTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
> index 20294ab43b..75331ae8e4 100644
> --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoardDescLib.inf
> @@ -22,7 +22,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdeModulePkg/MdeModulePkg.dec
> MdePkg/MdePkg.dec
> - Silicon/Marvell/Marvell.dec
> + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> index 946b9fd6d0..64623e33f8 100644
> --- a/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> +++ b/Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> @@ -29,7 +29,7 @@
> EmbeddedPkg/EmbeddedPkg.dec
> MdePkg/MdePkg.dec
> MdeModulePkg/MdeModulePkg.dec
> - Silicon/Marvell/Marvell.dec
> + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
>
> [LibraryClasses]
> DebugLib
> diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> index 2698bd6573..22a0040265 100644
> --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> @@ -31,9 +31,6 @@
>
> !include MdePkg/MdeLibs.dsc.inc
>
> -[Components.common]
> - Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
Please bring this one back.
Thanks,
Marcin
> -
> [Components.AARCH64]
> Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure
2023-11-02 3:45 [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure Narinder Dhillon
2023-11-02 3:45 ` [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package Narinder Dhillon
@ 2023-11-16 17:11 ` Leif Lindholm
1 sibling, 0 replies; 4+ messages in thread
From: Leif Lindholm @ 2023-11-16 17:11 UTC (permalink / raw)
To: ndhillon; +Cc: devel, mw, sbalcerak
Apologies, I managed to misfile this.
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Typo in subject line fixed, pushed as ec5de71d83f3.
Thanks!
/
Leif
On Thu, Nov 02, 2023 at 09:15:51 +0530, ndhillon@marvell.com wrote:
> From: Narinder Dhillon <ndhillon@marvell.com>
>
> Current Silicon/Marvell package structure does not allow sharing of
> components that are common to different SoC's. This restructure will
> increase shared code and better seperation.
>
> Credit to Leif Lindholm for providing this new structure.
>
> v2:
> - Remove three lines for libraries that were erroneously introduced
> into MarvellSiliconPkg.dec file. These libraries are present in
> Armada7k8k.dsc.inc
> - Removed trailing new line at the end of MarvellSiliconPkg.dec
> - Squashed patches 2,3,4 into 1 as they don't build separately
>
> v1:
> - Original patch series restructuring Marvell package
>
>
> Narinder Dhillon (1):
> Silicon/Marvell: Retructure package
>
> .../Marvell/Armada70x0Db/Armada70x0Db.dsc | 108 ++++-----
> .../Armada70x0DbBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Marvell/Armada80x0Db/Armada80x0Db.dsc | 133 ++++++-----
> .../Armada80x0DbBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Cn9130DbABoardDescLib.inf | 2 +-
> .../Cn9132DbABoardDescLib.inf | 2 +-
> Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 100 ++++-----
> Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 66 +++---
> Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 66 +++---
> Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 8 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Armada80x0McBin/Armada80x0McBin.dsc | 116 +++++-----
> .../Armada80x0McBinBoardDescLib.inf | 2 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../BoardDescriptionLib.inf | 2 +-
> .../Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 40 ++--
> .../Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 56 ++---
> .../Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 56 ++---
> .../Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 60 ++---
> .../Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 6 +-
> .../NonDiscoverableInitLib.inf | 2 +-
> .../Applications/EepromCmd/EepromCmd.inf | 2 +-
> .../Applications/FirmwareUpdate/FUpdate.inf | 6 +-
> .../Applications/SpiTool/SpiFlashCmd.inf | 6 +-
> .../Armada7k8k/AcpiTables/Armada70x0Db.inf | 2 +-
> .../Armada7k8k/AcpiTables/Armada80x0Db.inf | 2 +-
> .../Armada7k8k/AcpiTables/Armada80x0McBin.inf | 2 +-
> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 22 +-
> .../Armada7k8kRngDxe/Armada7k8kRngDxe.inf | 4 +-
> .../Drivers/PlatInitDxe/PlatInitDxe.inf | 6 +-
> .../PlatformFlashAccessLib.inf | 6 +-
> .../Library/Armada7k8kLib/Armada7k8kLib.inf | 4 +-
> .../Armada7k8kMemoryInitPeiLib.inf | 14 +-
> .../PciHostBridgeLib.inf | 2 +-
> .../Armada7k8kPciSegmentLib/PciSegmentLib.inf | 2 +-
> .../Armada7k8kSampleAtResetLib.inf | 2 +-
> .../Armada7k8kSoCDescLib.inf | 4 +-
> .../RealTimeClockLib/RealTimeClockLib.inf | 4 +-
> .../Marvell/Documentation/PortingGuide.txt | 114 +++++-----
> .../Drivers/BoardDesc/MvBoardDescDxe.inf | 18 +-
> .../Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf | 2 +-
> .../Gpio/MvPca95xxDxe/MvPca95xxDxe.inf | 2 +-
> .../Drivers/I2c/MvEepromDxe/MvEepromDxe.inf | 6 +-
> .../Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 14 +-
> .../Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 2 +-
> .../Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.inf | 12 +-
> Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 16 +-
> .../NonDiscoverableDxe/NonDiscoverableDxe.inf | 2 +-
> .../Drivers/SdMmc/XenonDxe/XenonDxe.inf | 2 +-
> .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 14 +-
> .../Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 8 +-
> .../Spi/MvSpiFlashDxe/MvSpiFlashDxe.inf | 2 +-
> .../Spi/MvSpiOrionDxe/MvSpiOrionDxe.inf | 8 +-
> .../Marvell/Library/ComPhyLib/ComPhyLib.inf | 28 +--
> Silicon/Marvell/Library/IcuLib/IcuLib.inf | 4 +-
> Silicon/Marvell/Library/MppLib/MppLib.inf | 94 ++++----
> .../Marvell/Library/MvGpioLib/MvGpioLib.inf | 2 +-
> .../Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 2 +-
> Silicon/Marvell/Marvell.dec | 208 ------------------
> .../Include/IndustryStandard/MvSmc.h | 0
> .../Include/Library/ArmadaBoardDescLib.h | 0
> .../Include/Library/ArmadaIcuLib.h | 0
> .../Include/Library/ArmadaSoCDescLib.h | 0
> .../Include/Library/MppLib.h | 0
> .../Include/Library/MvComPhyLib.h | 0
> .../Include/Library/MvGpioLib.h | 0
> .../Include/Library/NonDiscoverableInitLib.h | 0
> .../Include/Library/SampleAtResetLib.h | 0
> .../Include/Library/UtmiPhyLib.h | 0
> .../Include/Protocol/BoardDesc.h | 0
> .../Include/Protocol/Eeprom.h | 0
> .../Include/Protocol/Mdio.h | 0
> .../Include/Protocol/MvI2c.h | 0
> .../Include/Protocol/MvPhy.h | 0
> .../Include/Protocol/Spi.h | 0
> .../Include/Protocol/SpiFlash.h | 0
> .../MarvellSiliconPkg/MarvellSiliconPkg.dec | 207 +++++++++++++++++
> .../OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 2 +-
> .../OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 2 +-
> .../AcpiTables/T91/Cn913xCEx7Eval.inf | 2 +-
> 82 files changed, 848 insertions(+), 852 deletions(-)
> delete mode 100644 Silicon/Marvell/Marvell.dec
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/IndustryStandard/MvSmc.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaBoardDescLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaIcuLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/ArmadaSoCDescLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MppLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvComPhyLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/MvGpioLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/NonDiscoverableInitLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/SampleAtResetLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Library/UtmiPhyLib.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/BoardDesc.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Eeprom.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Mdio.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvI2c.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/MvPhy.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/Spi.h (100%)
> rename Silicon/Marvell/{ => MarvellSiliconPkg}/Include/Protocol/SpiFlash.h (100%)
> create mode 100644 Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec
>
>
> base-commit: c1d04ecedf3246ec7c2e0cc12658c9c6a26f91ac
> --
> 2.34.1
>
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2023-11-02 3:45 [edk2-devel] [edk2-platforms PATCH v2 0/1] Marvell package restructure Narinder Dhillon
2023-11-02 3:45 ` [edk2-devel] [edk2-platforms PATCH v2 1/1] Silicon/Marvell: Retructure package Narinder Dhillon
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