From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 56F2A74003E for ; Thu, 2 Nov 2023 13:54:46 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=LeTLpK4NXP7ILdP1pbZ7wZquFo03Y/vPxQg5hoH/34w=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1698933285; v=1; b=uFoBAz/lWB0HYb6b4PjRcXc3Dg5kTIwM7noaXzSzEno+c9nFCR5FyWqBeASuIHa6Dbu+P0YA a6N9eGp6Jr1rYU2YB0Muqa7pqghJ8I+pCPFKIvR88SqYns1AhyCLQYR8G3Ue4jo2oy6eHmEnNgy +fpBX6bsybzQVZLygtOr1vYY= X-Received: by 127.0.0.2 with SMTP id iIjyYY7687511xqCgBor9lOR; Thu, 02 Nov 2023 06:54:45 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.31761.1698933284160316424 for ; Thu, 02 Nov 2023 06:54:44 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1AA9A1570; Thu, 2 Nov 2023 06:55:26 -0700 (PDT) X-Received: from cam-smtp0.cambridge.arm.com (e126645.nice.arm.com [10.34.100.114]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7CDC83F738; Thu, 2 Nov 2023 06:54:42 -0700 (PDT) From: "PierreGondois" To: devel@edk2.groups.io Cc: Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v1 6/7] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks Date: Thu, 2 Nov 2023 14:54:16 +0100 Message-Id: <20231102135417.336334-7-pierre.gondois@arm.com> In-Reply-To: <20231102135417.336334-1-pierre.gondois@arm.com> References: <20231102135417.336334-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 7QM54pT2uKivsVW8ZITKV6lex7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="uFoBAz/l"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Add AARCH64 specific implementations of: - OPENSSL_cpuid_setup(), probing hardware capabilitie (presence of FEAT_AES, etc.) - OPENSSL_rdtsc(), returning non-trusted entropy by accessing system counter. Signed-off-by: Pierre Gondois --- .../Library/OpensslLib/OpensslLibAccel.inf | 5 +- .../OpensslLib/OpensslLibFullAccel.inf | 5 +- .../OpensslLib/OpensslStub/AArch64Cap.c | 107 ++++++++++++++++++ 3 files changed, 113 insertions(+), 4 deletions(-) create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/L= ibrary/OpensslLib/OpensslLibAccel.inf index 2cf985d9e5f9..a180820577aa 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf @@ -1329,6 +1329,7 @@ [Sources.X64] # Autogenerated files list ends here=0D =0D [Sources.AARCH64]=0D + OpensslStub/AArch64Cap.c=0D # Autogenerated files list starts here=0D $(OPENSSL_PATH)/crypto/aes/aes_cbc.c=0D $(OPENSSL_PATH)/crypto/aes/aes_cfb.c=0D @@ -1598,7 +1599,7 @@ [Sources.AARCH64] $(OPENSSL_PATH)/crypto/kdf/kdf_err.c=0D $(OPENSSL_PATH)/crypto/lhash/lh_stats.c=0D $(OPENSSL_PATH)/crypto/lhash/lhash.c=0D - $(OPENSSL_PATH)/crypto/armcap.c=0D +# $(OPENSSL_PATH)/crypto/armcap.c=0D $(OPENSSL_PATH)/crypto/asn1_dsa.c=0D $(OPENSSL_PATH)/crypto/bsearch.c=0D $(OPENSSL_PATH)/crypto/context.c=0D @@ -1606,7 +1607,7 @@ [Sources.AARCH64] $(OPENSSL_PATH)/crypto/core_fetch.c=0D $(OPENSSL_PATH)/crypto/core_namemap.c=0D $(OPENSSL_PATH)/crypto/cpt_err.c=0D - $(OPENSSL_PATH)/crypto/cpuid.c=0D +# $(OPENSSL_PATH)/crypto/cpuid.c=0D $(OPENSSL_PATH)/crypto/cryptlib.c=0D $(OPENSSL_PATH)/crypto/ctype.c=0D $(OPENSSL_PATH)/crypto/cversion.c=0D diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoP= kg/Library/OpensslLib/OpensslLibFullAccel.inf index 111346b31814..23917029e873 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf @@ -1432,6 +1432,7 @@ [Sources.X64] # Autogenerated files list ends here=0D =0D [Sources.AARCH64]=0D + OpensslStub/AArch64Cap.c=0D # Autogenerated files list starts here=0D $(OPENSSL_PATH)/crypto/aes/aes_cbc.c=0D $(OPENSSL_PATH)/crypto/aes/aes_cfb.c=0D @@ -1739,7 +1740,7 @@ [Sources.AARCH64] $(OPENSSL_PATH)/crypto/kdf/kdf_err.c=0D $(OPENSSL_PATH)/crypto/lhash/lh_stats.c=0D $(OPENSSL_PATH)/crypto/lhash/lhash.c=0D - $(OPENSSL_PATH)/crypto/armcap.c=0D +# $(OPENSSL_PATH)/crypto/armcap.c=0D $(OPENSSL_PATH)/crypto/asn1_dsa.c=0D $(OPENSSL_PATH)/crypto/bsearch.c=0D $(OPENSSL_PATH)/crypto/context.c=0D @@ -1747,7 +1748,7 @@ [Sources.AARCH64] $(OPENSSL_PATH)/crypto/core_fetch.c=0D $(OPENSSL_PATH)/crypto/core_namemap.c=0D $(OPENSSL_PATH)/crypto/cpt_err.c=0D - $(OPENSSL_PATH)/crypto/cpuid.c=0D +# $(OPENSSL_PATH)/crypto/cpuid.c=0D $(OPENSSL_PATH)/crypto/cryptlib.c=0D $(OPENSSL_PATH)/crypto/ctype.c=0D $(OPENSSL_PATH)/crypto/cversion.c=0D diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/Crypto= Pkg/Library/OpensslLib/OpensslStub/AArch64Cap.c new file mode 100644 index 000000000000..3a21d54462e3 --- /dev/null +++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c @@ -0,0 +1,107 @@ +/** @file=0D + Arm capabilities probing.=0D +=0D + Copyright (c) 2023, Arm Limited. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include "crypto/arm_arch.h"=0D +=0D +#include =0D +=0D +/** Get bits from a value.=0D +=0D + Shift the input value from 'shift' bits and apply 'mask'.=0D +=0D + @param value The value to get the bits from.=0D + @param shift Index of the bits to read.=0D + @param mask Mask to apply to the value once shifted.=0D +=0D + @return The desired bitfield from the value.=0D +**/=0D +#define GET_BITFIELD(value, shift, mask) \=0D + ((value >> shift) & mask)=0D +=0D +UINT32 OPENSSL_armcap_P =3D 0;=0D +=0D +void=0D +OPENSSL_cpuid_setup (=0D + void=0D + )=0D +{=0D + UINT64 Isar0;=0D +=0D + OPENSSL_armcap_P =3D 0;=0D + Isar0 =3D ArmReadIdAA64Isar0Reg ();=0D +=0D + /* Access to EL0 registers is possible from higher ELx. */=0D + OPENSSL_armcap_P |=3D ARMV8_CPUID;=0D + /* Access to Physical timer is possible. */=0D + OPENSSL_armcap_P |=3D ARMV7_TICK;=0D +=0D + /* Neon support is not guaranteed, but it is assumed to be present.=0D + Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support=0D + */=0D + OPENSSL_armcap_P |=3D ARMV7_NEON;=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_AES;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA1_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA1;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA256;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_MASK=0D + ) >=3D ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_PMULL;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_MASK=0D + ) >=3D ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA512;=0D + }=0D +}=0D +=0D +/** Read system counter value.=0D +=0D + Used to get some non-trusted entropy.=0D +=0D + @return Lower bits of the physical counter.=0D +**/=0D +uint32_t=0D +OPENSSL_rdtsc (=0D + void=0D + )=0D +{=0D + return (UINT32)ArmReadCntPctReg ();=0D +}=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110553): https://edk2.groups.io/g/devel/message/110553 Mute This Topic: https://groups.io/mt/102342402/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-