From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 17382D8108F for ; Fri, 3 Nov 2023 15:30:27 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=6+Wh4uCPj5pgxWqxxmdb6hQE2LfkLIgYyBEpbP86sKw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025426; v=1; b=PsTxCiVhrGRHhawf507dah2GlX0iLk744eXVb4qISAYGkYm3gC8SqzSWvjjdDR4s57bN+eju M9FUMWXfgpxl8OZxI1Vv+iPwRjMH3Pf94vZCCpX7Gz3BTWDMUrxVPljlRySy5uNLt43ws015r7r DRlHsL+NhB4NYPq9KEoiVwpI= X-Received: by 127.0.0.2 with SMTP id hnb5YY7687511xFvGZVYqFt0; Fri, 03 Nov 2023 08:30:26 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:26 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898902" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898902" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793181" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793181" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:23 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 3/7] UefiCpuPkg: Adds SmmCpuSyncLib library class Date: Fri, 3 Nov 2023 23:30:08 +0800 Message-Id: <20231103153012.3704-4-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: iY9GmF0VfuxdEI8x7dbzw9erx7686176AA= X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=PsTxCiVh; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) Intel is planning to provide different SMM CPU Sync implementation along with some specific registers to improve the SMI performance, hence need SmmCpuSyncLib Library for Intel. This patch is to: 1.Adds SmmCpuSyncLib Library class in UefiCpuPkg.dec. 2.Adds SmmCpuSyncLib.h function declaration header file. Change-Id: Ib7f5e317526e8b9e29b65e072bdb485dbd678817 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Include/Library/SmmCpuSyncLib.h | 191 +++++++++++++++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 3 + 2 files changed, 194 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmCpuSyncLib.h diff --git a/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h new file mode 100644 index 0000000000..b9b190c516 --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmCpuSyncLib.h @@ -0,0 +1,191 @@ +/** @file +Library that provides SMM CPU Sync related operations. + +Copyright (c) 2023, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_CPU_SYNC_LIB_H_ +#define SMM_CPU_SYNC_LIB_H_ + +#include + +/** + Creates and Init a new Smm Cpu Sync context. + + @param[in] NumberOfCpus The number of processors in the system. + + @return Pointer to an allocated Smm Cpu Sync context object. + If the creation failed, returns NULL. + +**/ +VOID * +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus + ); + +/** + Deinit an allocated Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Reset Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Get current arrived CPU count. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + + @return Current number of arrived CPU count. + -1: indicate the door has been locked. + +**/ +UINT32 +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN VOID *SmmCpuSyncCtx + ); + +/** + Performs an atomic operation to check in CPU. + Check in CPU successfully if the returned arrival CPU count value is + positive, otherwise indicate the door has been locked, the CPU can + not checkin. + + @param[in] SmmCpuSyncCtx Pointer to the Smm CPU Sync context object to be released. + @param[in] CpuIndex Pointer to the CPU Index to checkin. + + @return Positive value (>0): CPU arrival count number after check in CPU successfully. + Nonpositive value (<=0): check in CPU failure. + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckInCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation to check out CPU. + Check out CPU successfully if the returned arrival CPU count value is + nonnegative, otherwise indicate the door has been locked, the CPU can + not checkout. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + @param[in] CpuIndex Pointer to the Cpu Index to checkout. + + @return Nonnegative value (>=0): CPU arrival count number after check out CPU successfully. + Negative value (<0): Check out CPU failure. + + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + With this function, CPU can not check in via SmmCpuSyncCheckInCpu () or + check out via SmmCpuSyncCheckOutCpu (). + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + @param[in] CpuIndex Pointer to the Cpu Index to lock door. + + @return CPU arrival count number. + +**/ +UINT32 +EFIAPI +SmmCpuSyncLockDoor ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ); + +/** + Used for BSP to wait all APs. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] NumberOfAPs Number of APs need to wait. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAllAPs ( + IN VOID *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ); + +/** + Used for BSP to release one AP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP need to be released. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used for AP to wait BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP wait BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +/** + Used for AP to release BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP release BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ); + +#endif diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 0b5431dbf7..20ab079219 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,10 +62,13 @@ CpuPageTableLib|Include/Library/CpuPageTableLib.h ## @libraryclass Provides functions for manipulating smram savestate registers. MmSaveStateLib|Include/Library/MmSaveStateLib.h + ## @libraryclass Provides functions for SMM CPU Sync Operation. + SmmCpuSyncLib|Include/Library/SmmCpuSyncLib.h + [LibraryClasses.RISCV64] ## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110639): https://edk2.groups.io/g/devel/message/110639 Mute This Topic: https://groups.io/mt/102366300/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-