From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3C14DAC120C for ; Fri, 3 Nov 2023 15:30:30 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=oqp/mEMfPrRPfuqR/6LknorIaU+phLVa/84qlzGlld4=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe; s=20140610; t=1699025428; v=1; b=KZb2WN4OXW6thndDrVNGtnEQkVMLt22Sl/vz1RWvenFhoFBdQr8eiMTA36q4aqBLrQuilHGr ULzdmype8X2vfoeHTvnxOxpls6T59O2b+OA1RfO/c3FrJFyjzQe+EBujhmD7kAjdcZcUQ4Zk7aF rmO3c4tw3P4fPh7X8+GxmuAQ= X-Received: by 127.0.0.2 with SMTP id 9dbwYY7687511xcPbbwO9VD2; Fri, 03 Nov 2023 08:30:28 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web10.56401.1699025420211463760 for ; Fri, 03 Nov 2023 08:30:28 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="1898919" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="1898919" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 08:30:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="790793227" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="790793227" X-Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 03 Nov 2023 08:30:26 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [edk2-devel] [PATCH v1 4/7] UefiCpuPkg: Implements SmmCpuSyncLib library instance Date: Fri, 3 Nov 2023 23:30:09 +0800 Message-Id: <20231103153012.3704-5-jiaxin.wu@intel.com> In-Reply-To: <20231103153012.3704-1-jiaxin.wu@intel.com> References: <20231103153012.3704-1-jiaxin.wu@intel.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,jiaxin.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: CespuO2kfrwNbiW6E4wa2LGUx7686176AA= X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=KZb2WN4O; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Implements SmmCpuSyncLib Library class. The instance follows the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAllAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Change-Id: I5a004637f8b24a90594a794092548b850b187493 Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c | 481 +++++++++++++++++++++ UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf | 38 ++ UefiCpuPkg/UefiCpuLibs.dsc.inc | 15 + UefiCpuPkg/UefiCpuPkg.dsc | 1 + 4 files changed, 535 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c create mode 100644 UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf create mode 100644 UefiCpuPkg/UefiCpuLibs.dsc.inc diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c new file mode 100644 index 0000000000..3bc3ebe49a --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.c @@ -0,0 +1,481 @@ +/** @file + SMM CPU Sync lib implementation. + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + /// + /// Indicate how many CPU entered SMM. + /// + volatile UINT32 *Counter; +} SMM_CPU_SYNC_SEMAPHORE_GLOBAL; + +typedef struct { + /// + /// Used for control each CPU continue run or wait for signal + /// + volatile UINT32 *Run; +} SMM_CPU_SYNC_SEMAPHORE_CPU; + +typedef struct { + /// + /// All global semaphores' pointer in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_GLOBAL *GlobalSem; + /// + /// All semaphores for each processor in SMM CPU Sync + /// + SMM_CPU_SYNC_SEMAPHORE_CPU *CpuSem; + /// + /// The number of processors in the system. + /// This does not indicate the number of processors that entered SMM. + /// + UINTN NumberOfCpus; + /// + /// Address of global and each CPU semaphores + /// + UINTN *SemBlock; + /// + /// Size of global and each CPU semaphores + /// + UINTN SemBlockPages; +} SMM_CPU_SYNC_CTX; + +/** + Performs an atomic compare exchange operation to get semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: original integer - 1 + + @return Original integer - 1 + +**/ +UINT32 +InternalWaitForSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + for ( ; ;) { + Value = *Sem; + if ((Value != 0) && + (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value - 1 + ) == Value)) + { + break; + } + + CpuPause (); + } + + return Value - 1; +} + +/** + Performs an atomic compare exchange operation to release semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: original integer + 1 + + @return Original integer + 1 + +**/ +UINT32 +InternalReleaseSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value = *Sem; + } while (Value + 1 != 0 && + InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + Value + 1 + ) != Value); + + return Value + 1; +} + +/** + Performs an atomic compare exchange operation to lock semaphore. + The compare exchange operation must be performed using MP safe + mechanisms. + + @param Sem IN: 32-bit unsigned integer + OUT: -1 + + @return Original integer + +**/ +UINT32 +InternalLockdownSemaphore ( + IN OUT volatile UINT32 *Sem + ) +{ + UINT32 Value; + + do { + Value = *Sem; + } while (InterlockedCompareExchange32 ( + (UINT32 *)Sem, + Value, + (UINT32)-1 + ) != Value); + + return Value; +} + +/** + Creates and Init a new Smm Cpu Sync context. + + @param[in] NumberOfCpus The number of processors in the system. + + @return Pointer to an allocated Smm Cpu Sync context object. + If the creation failed, returns NULL. + +**/ +VOID * +EFIAPI +SmmCpuSyncContextInit ( + IN UINTN NumberOfCpus + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + UINTN CtxSize; + UINTN OneSemSize; + UINTN GlobalSemSize; + UINTN CpuSemSize; + UINTN TotalSemSize; + UINTN SemAddr; + UINTN CpuIndex; + + Ctx = NULL; + + // + // Allocate for the Ctx + // + CtxSize = sizeof (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL) + sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) * NumberOfCpus; + Ctx = (SMM_CPU_SYNC_CTX *)AllocatePages (EFI_SIZE_TO_PAGES (CtxSize)); + ASSERT (Ctx != NULL); + Ctx->GlobalSem = (SMM_CPU_SYNC_SEMAPHORE_GLOBAL *)((UINT8 *)Ctx + sizeof (SMM_CPU_SYNC_CTX)); + Ctx->CpuSem = (SMM_CPU_SYNC_SEMAPHORE_CPU *)((UINT8 *)Ctx + sizeof (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL)); + Ctx->NumberOfCpus = NumberOfCpus; + + // + // Allocate for Semaphores in the Ctx + // + OneSemSize = GetSpinLockProperties (); + GlobalSemSize = (sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * OneSemSize; + CpuSemSize = (sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) / sizeof (VOID *)) * OneSemSize * NumberOfCpus; + TotalSemSize = GlobalSemSize + CpuSemSize; + DEBUG ((DEBUG_INFO, "[%a] - One Semaphore Size = 0x%x\n", __FUNCTION__, OneSemSize)); + DEBUG ((DEBUG_INFO, "[%a] - Total Semaphores Size = 0x%x\n", __FUNCTION__, TotalSemSize)); + Ctx->SemBlockPages = EFI_SIZE_TO_PAGES (TotalSemSize); + Ctx->SemBlock = AllocatePages (Ctx->SemBlockPages); + ASSERT (Ctx->SemBlock != NULL); + ZeroMem (Ctx->SemBlock, TotalSemSize); + + SemAddr = (UINTN)Ctx->SemBlock; + + // + // Assign Global Semaphore pointer + // + Ctx->GlobalSem->Counter = (UINT32 *)SemAddr; + *Ctx->GlobalSem->Counter = 0; + DEBUG ((DEBUG_INFO, "[%a] - Ctx->GlobalSem->Counter Address: 0x%08x\n", __FUNCTION__, (UINTN)Ctx->GlobalSem->Counter)); + + SemAddr += GlobalSemSize; + + // + // Assign CPU Semaphore pointer + // + for (CpuIndex = 0; CpuIndex < NumberOfCpus; CpuIndex++) { + Ctx->CpuSem[CpuIndex].Run = (UINT32 *)(SemAddr + (CpuSemSize / NumberOfCpus) * CpuIndex); + *Ctx->CpuSem[CpuIndex].Run = 0; + DEBUG ((DEBUG_INFO, "[%a] - Ctx->CpuSem[%d].Run Address: 0x%08x\n", __FUNCTION__, CpuIndex, (UINTN)Ctx->CpuSem[CpuIndex].Run)); + } + + // + // Return the new created Smm Cpu Sync context + // + return (VOID *)Ctx; +} + +/** + Deinit an allocated Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextDeinit ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + UINTN CtxSize; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + CtxSize = sizeof (SMM_CPU_SYNC_CTX) + sizeof (SMM_CPU_SYNC_SEMAPHORE_GLOBAL) + sizeof (SMM_CPU_SYNC_SEMAPHORE_CPU) * (Ctx->NumberOfCpus); + + FreePages (Ctx->SemBlock, Ctx->SemBlockPages); + + FreePages (Ctx, EFI_SIZE_TO_PAGES (CtxSize)); +} + +/** + Reset Smm Cpu Sync context object. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + +**/ +VOID +EFIAPI +SmmCpuSyncContextReset ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + *Ctx->GlobalSem->Counter = 0; +} + +/** + Get current arrived CPU count. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + + @return Current number of arrived CPU count. + -1: indicate the door has been locked. + +**/ +UINT32 +EFIAPI +SmmCpuSyncGetArrivedCpuCount ( + IN VOID *SmmCpuSyncCtx + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + if (*Ctx->GlobalSem->Counter < 0) { + return (UINT32)-1; + } + + return *Ctx->GlobalSem->Counter; +} + +/** + Performs an atomic operation to check in CPU. + Check in CPU successfully if the returned arrival CPU count value is + positive, otherwise indicate the door has been locked, the CPU can + not checkin. + + @param[in] SmmCpuSyncCtx Pointer to the Smm CPU Sync context object to be released. + @param[in] CpuIndex Pointer to the CPU Index to checkin. + + @return Positive value (>0): CPU arrival count number after check in CPU successfully. + Nonpositive value (<=0): check in CPU failure. + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckInCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return (INT32)InternalReleaseSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Performs an atomic operation to check out CPU. + Check out CPU successfully if the returned arrival CPU count value is + nonnegative, otherwise indicate the door has been locked, the CPU can + not checkout. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + @param[in] CpuIndex Pointer to the Cpu Index to checkout. + + @return Nonnegative value (>=0): CPU arrival count number after check out CPU successfully. + Negative value (<0): Check out CPU failure. + + +**/ +INT32 +EFIAPI +SmmCpuSyncCheckOutCpu ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return (INT32)InternalWaitForSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Performs an atomic operation lock door for CPU checkin or checkout. + With this function, CPU can not check in via SmmCpuSyncCheckInCpu () or + check out via SmmCpuSyncCheckOutCpu (). + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object to be released. + @param[in] CpuIndex Pointer to the Cpu Index to lock door. + + @return CPU arrival count number. + +**/ +UINT32 +EFIAPI +SmmCpuSyncLockDoor ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + return InternalLockdownSemaphore (Ctx->GlobalSem->Counter); +} + +/** + Used for BSP to wait all APs. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] NumberOfAPs Number of APs need to wait. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForAllAPs ( + IN VOID *SmmCpuSyncCtx, + IN UINTN NumberOfAPs, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + while (NumberOfAPs-- > 0) { + InternalWaitForSemaphore (Ctx->CpuSem[BspIndex].Run); + } +} + +/** + Used for BSP to release one AP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP need to be released. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseOneAp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalReleaseSemaphore (Ctx->CpuSem[CpuIndex].Run); +} + +/** + Used for AP to wait BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP wait BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncWaitForBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalWaitForSemaphore (Ctx->CpuSem[CpuIndex].Run); +} + +/** + Used for AP to release BSP. + + @param[in] SmmCpuSyncCtx Pointer to the Smm Cpu Sync context object. + @param[in] CpuIndex Pointer to the Cpu Index, indicate which AP release BSP. + @param[in] BspIndex Pointer to the BSP Index. + +**/ +VOID +EFIAPI +SmmCpuSyncReleaseBsp ( + IN VOID *SmmCpuSyncCtx, + IN UINTN CpuIndex, + IN UINTN BspIndex + ) +{ + SMM_CPU_SYNC_CTX *Ctx; + + ASSERT (SmmCpuSyncCtx != NULL); + Ctx = (SMM_CPU_SYNC_CTX *)SmmCpuSyncCtx; + + InternalReleaseSemaphore (Ctx->CpuSem[BspIndex].Run); +} diff --git a/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf new file mode 100644 index 0000000000..86475ce64b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf @@ -0,0 +1,38 @@ +## @file +# SMM CPU Synchronization lib. +# +# This is SMM CPU Synchronization lib used for SMM CPU sync operations. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmCpuSyncLib + FILE_GUID = 1ca1bc1a-16a4-46ef-956a-ca500fd3381f + MODULE_TYPE = DXE_SMM_DRIVER + LIBRARY_CLASS = SmmCpuSyncLib|DXE_SMM_DRIVER + +[Sources] + SmmCpuSyncLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + PrintLib + SynchronizationLib + BaseMemoryLib + SmmServicesTableLib + MemoryAllocationLib + +[Pcd] + +[Protocols] diff --git a/UefiCpuPkg/UefiCpuLibs.dsc.inc b/UefiCpuPkg/UefiCpuLibs.dsc.inc new file mode 100644 index 0000000000..6b9b362729 --- /dev/null +++ b/UefiCpuPkg/UefiCpuLibs.dsc.inc @@ -0,0 +1,15 @@ +## @file +# UefiCpu DSC include file for [LibraryClasses*] section of all Architectures. +# +# This file can be included to the [LibraryClasses*] section(s) of a platform DSC file +# by using "!include UefiCpuPkg/UefiCpuLibs.dsc.inc" to specify the library instances +# of some EDKII basic/common library classes in UefiCpuPkg. +# +# Copyright (c) 2023, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[LibraryClasses] + SmmCpuSyncLib|UefiCpuPkg/Library/SmmCpuSyncLib/SmmCpuSyncLib.inf \ No newline at end of file diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 074fd77461..338f18eb98 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -21,10 +21,11 @@ # # External libraries to build package # !include MdePkg/MdeLibs.dsc.inc +!include UefiCpuPkg/UefiCpuLibs.dsc.inc [LibraryClasses] BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110640): https://edk2.groups.io/g/devel/message/110640 Mute This Topic: https://groups.io/mt/102366301/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-