From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 55E607803CC for ; Mon, 6 Nov 2023 02:54:09 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=CrIhFalvwnqJv18tBM/xTnZNL0JNIcANEKF+9CFb29U=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699239247; v=1; b=eAl67h5G/OHOG3hiW3qZSwZLGTY23RJlxf3XZ7k8LCmuLWfvxPTCYO5aGF2j96DQ7tRw7A2o ns4rQB4opZbd0OpgIzG5BvcJV0e5O4rS/SKy+1RvB+zgdt4uUSh1pu+gxs09o8m9br5kbRiqXWT mx80u0iH5csPsaaIg1gUZrKg= X-Received: by 127.0.0.2 with SMTP id Wtx7YY7687511x83m3b6NM6U; Sun, 05 Nov 2023 18:54:07 -0800 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.46618.1699239247225182097 for ; Sun, 05 Nov 2023 18:54:07 -0800 X-Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6b77ab73c6fso3160475b3a.1 for ; Sun, 05 Nov 2023 18:54:07 -0800 (PST) X-Gm-Message-State: 8nBNyYCI8OZotGAlBnaKCJ4Kx7686176AA= X-Google-Smtp-Source: AGHT+IGo9M7a+0mBon3DY2zuTW2aLTY3w16nqfRzwSj73rZt+YHnuT3wdqvpN4E+Cx4PVuvxOPoE6Q== X-Received: by 2002:a05:6a00:1819:b0:690:f877:aa1e with SMTP id y25-20020a056a00181900b00690f877aa1emr12353769pfa.12.1699239246304; Sun, 05 Nov 2023 18:54:06 -0800 (PST) X-Received: from dhaval.. ([171.76.87.118]) by smtp.gmail.com with ESMTPSA id fa16-20020a056a002d1000b0068fece2c190sm2679724pfb.70.2023.11.05.18.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Nov 2023 18:54:06 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v8 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Date: Mon, 6 Nov 2023 08:23:52 +0530 Message-Id: <20231106025356.167717-2-dhaval@rivosinc.com> In-Reply-To: <20231106025356.167717-1-dhaval@rivosinc.com> References: <20231106025356.167717-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=eAl67h5G; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek --- Notes: V7: - Added RB tag V6: - Move cache management function declaration in baselib where it belongs MdePkg/Include/Library/BaseLib.h | 20 +++++++++++++++++= +++ MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 -----------------= --- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 5d7067ee854e..7142bbfa42f2 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt ( VOID=0D );=0D =0D +/**=0D + RISC-V invalidate instruction cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateInstCacheAsm (=0D + VOID=0D + );=0D +=0D +/**=0D + RISC-V invalidate data cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateDataCacheAsm (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D #if defined (MDE_CPU_LOONGARCH64)=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..d5efcf49a4bf 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -10,26 +10,6 @@ #include =0D #include =0D =0D -/**=0D - RISC-V invalidate instruction cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateInstCacheAsm (=0D - VOID=0D - );=0D -=0D -/**=0D - RISC-V invalidate data cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateDataCacheAsm (=0D - VOID=0D - );=0D -=0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D calling CPU.=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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