From: "Chao Li" <lichao@loongson.cn>
To: devel@edk2.groups.io
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Bibo Mao <maobibo@loongson.cn>
Subject: [edk2-devel] [PATCH v2 07/30] MdePkg: Add CSR operation for LoongArch
Date: Mon, 6 Nov 2023 11:27:24 +0800 [thread overview]
Message-ID: <20231106032724.2274001-1-lichao@loongson.cn> (raw)
In-Reply-To: <20231106032521.2251143-1-lichao@loongson.cn>
Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them
to operate the CSR register of LoongArch architecture.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Bibo Mao <maobibo@loongson.cn>
---
MdePkg/Include/Library/BaseLib.h | 45 +++
MdePkg/Library/BaseLib/BaseLib.inf | 2 +
MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S | 422 ++++++++++++++++++++
MdePkg/Library/BaseLib/LoongArch64/Csr.c | 81 ++++
4 files changed, 550 insertions(+)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Csr.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 55d53c75a0..234f3065c2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -293,6 +293,51 @@ AsmReadStableCounter (
VOID
);
+/**
+ CSR read operation.
+
+ @param[in] Select CSR read instruction select values.
+
+ @return The return value of csrrd instruction, return -1 means no CSR instruction
+ is found.
+**/
+UINTN
+CsrRead (
+ IN UINT16 Select
+ );
+
+/**
+ CSR write operation.
+
+ @param[in] Select CSR write instruction select values.
+ @param[in] Value The csrwr will write the value.
+
+ @return The return value of csrwr instruction, that is, store the old value of
+ the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrWrite (
+ IN UINT16 Select,
+ IN UINTN Value
+ );
+
+/**
+ CSR exchange operation.
+
+ @param[in] Select CSR exchange instruction select values.
+ @param[in] Value The csrxchg will write the value.
+ @param[in] Mask The csrxchg mask value.
+
+ @return The return value of csrxchg instruction, that is, store the old value of
+ the register, return -1 means no CSR instruction is found.
+**/
+UINTN
+CsrXChg (
+ IN UINT16 Select,
+ IN UINTN Value,
+ IN UINTN Mask
+ );
+
#endif // defined (MDE_CPU_LOONGARCH64)
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index aaf221822b..74a323c798 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -409,7 +409,9 @@
[Sources.LOONGARCH64]
Math64.c
Unaligned.c
+ LoongArch64/Csr.c
LoongArch64/InternalSwitchStack.c
+ LoongArch64/AsmCsr.S | GCC
LoongArch64/GetInterruptState.S | GCC
LoongArch64/EnableInterrupts.S | GCC
LoongArch64/DisableInterrupts.S | GCC
diff --git a/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
new file mode 100644
index 0000000000..25dd060ede
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/AsmCsr.S
@@ -0,0 +1,422 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch ASM CSR operation functions
+#
+# Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <Register/LoongArch64/Csr.h>
+
+ASM_GLOBAL ASM_PFX (AsmCsrRead)
+ASM_GLOBAL ASM_PFX (AsmCsrWrite)
+ASM_GLOBAL ASM_PFX (AsmCsrXChg)
+
+.macro AsmCsrRd Sel
+ csrrd $a0, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+.macro AsmCsrWr Sel
+ csrwr $a0, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+.macro AsmCsrXChange Sel
+ csrxchg $a0, $a1, \Sel
+ jirl $zero, $ra, 0
+.endm
+
+ASM_PFX(AsmCsrRead):
+ blt $a0, $zero, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrRd
+
+BasicCsrRd:
+ la.pcrel $t0, BasicCsrRead
+ alsl.d $t0, $a0, $t0, 3
+ jirl $zero, $t0, 0
+
+TlbCsrRd:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrRd
+ la.pcrel $t0, TlbCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+CfgCsrRd:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrRd
+ la.pcrel $t0, CfgCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+KcsCsrRd:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrRd
+ la.pcrel $t0, KcsCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+StableTimerCsrRd:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrRd
+ la.pcrel $t0, StableTimerCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+TlbRefillCsrRd:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrRd
+ la.pcrel $t0, TlbRefillCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+DirMapCsrRd:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, ReadSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, ReadSelNumErr
+ la.pcrel $t0, DirMapCsrRead
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ jirl $zero, $t0, 0
+
+ReadSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrRead:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrRead:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrRead:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrRead:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrRead:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrRead:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrRead:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrRd CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+ASM_PFX(AsmCsrWrite):
+ blt $a0, $zero, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrWr
+
+BasicCsrWr:
+ la.pcrel $t0, BasicCsrWrite
+ alsl.d $t0, $a0, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+TlbCsrWr:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrWr
+ la.pcrel $t0, TlbCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+CfgCsrWr:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrWr
+ la.pcrel $t0, CfgCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+KcsCsrWr:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrWr
+ la.pcrel $t0, KcsCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+StableTimerCsrWr:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrWr
+ la.pcrel $t0, StableTimerCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+TlbRefillCsrWr:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrWr
+ la.pcrel $t0, TlbRefillCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+DirMapCsrWr:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, WriteSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, WriteSelNumErr
+ la.pcrel $t0, DirMapCsrWrite
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ jirl $zero, $t0, 0
+
+WriteSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrWrite:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrWrite:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrWrite:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrWrite:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrWrite:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrWrite:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrWrite:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrWr CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+
+ASM_PFX(AsmCsrXChg):
+ blt $a0, $zero, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_EBASE
+ bltu $t0, $a0, TlbCsrXchg
+
+BasicCsrXchg:
+ la.pcrel $t0, BasicCsrXchange
+ alsl.d $t0, $a0, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+TlbCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TLBIDX
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_RVACFG
+ bltu $t0, $a0, CfgCsrXchg
+ la.pcrel $t0, TlbCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBIDX
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+CfgCsrXchg:
+ li.w $t0, LOONGARCH_CSR_CPUNUM
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_PRCFG3
+ bltu $t0, $a0, KcsCsrXchg
+ la.pcrel $t0, CfgCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_CPUNUM
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+KcsCsrXchg:
+ li.w $t0, LOONGARCH_CSR_KS0
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_KS8
+ bltu $t0, $a0, StableTimerCsrXchg
+ la.pcrel $t0, KcsCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_KS0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+StableTimerCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TMID
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_TINTCLR
+ bltu $t0, $a0, TlbRefillCsrXchg
+ la.pcrel $t0, StableTimerCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TMID
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+TlbRefillCsrXchg:
+ li.w $t0, LOONGARCH_CSR_TLBREBASE
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_TLBREHI
+ bltu $t0, $a0, DirMapCsrXchg
+ la.pcrel $t0, TlbRefillCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_TLBREBASE
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+DirMapCsrXchg:
+ li.w $t0, LOONGARCH_CSR_DMWIN0
+ bltu $a0, $t0, XchgSelNumErr
+ li.w $t0, LOONGARCH_CSR_DMWIN3
+ bltu $t0, $a0, XchgSelNumErr
+ la.pcrel $t0, DirMapCsrXchange
+ addi.w $t1, $a0, -LOONGARCH_CSR_DMWIN0
+ alsl.d $t0, $t1, $t0, 3
+ move $a0, $a1
+ move $a1, $a2
+ jirl $zero, $t0, 0
+
+XchgSelNumErr:
+ addi.d $a0, $zero, -1
+ jirl $zero, $ra, 0
+
+BasicCsrXchange:
+ CsrSel = LOONGARCH_CSR_CRMD
+ .rept LOONGARCH_CSR_EBASE - LOONGARCH_CSR_CRMD + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbCsrXchange:
+ CsrSel = LOONGARCH_CSR_TLBIDX
+ .rept LOONGARCH_CSR_RVACFG - LOONGARCH_CSR_TLBIDX + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+CfgCsrXchange:
+ CsrSel = LOONGARCH_CSR_CPUNUM
+ .rept LOONGARCH_CSR_PRCFG3 - LOONGARCH_CSR_CPUNUM + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+KcsCsrXchange:
+ CsrSel = LOONGARCH_CSR_KS0
+ .rept LOONGARCH_CSR_KS8 - LOONGARCH_CSR_KS0 + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+StableTimerCsrXchange:
+ CsrSel = LOONGARCH_CSR_TMID
+ .rept LOONGARCH_CSR_TINTCLR - LOONGARCH_CSR_TMID + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+TlbRefillCsrXchange:
+ CsrSel = LOONGARCH_CSR_TLBREBASE
+ .rept LOONGARCH_CSR_TLBREHI - LOONGARCH_CSR_TLBREBASE + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+
+DirMapCsrXchange:
+ CsrSel = LOONGARCH_CSR_DMWIN0
+ .rept LOONGARCH_CSR_DMWIN3 - LOONGARCH_CSR_DMWIN0 + 1
+ AsmCsrXChange CsrSel
+ CsrSel = CsrSel + 1
+ .endr
+.end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/Csr.c b/MdePkg/Library/BaseLib/LoongArch64/Csr.c
new file mode 100644
index 0000000000..d51f30aacc
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Csr.c
@@ -0,0 +1,81 @@
+/** @file
+ LoongArch CSR operation functions.
+
+ Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+UINTN
+AsmCsrRead (
+ IN UINT16 Select
+ );
+
+UINTN
+AsmCsrWrite (
+ IN UINT16 Select,
+ IN UINTN Value
+ );
+
+UINTN
+AsmCsrXChg (
+ IN UINT16 Select,
+ IN UINTN Value,
+ IN UINTN Mask
+ );
+
+/**
+ CSR read operation.
+
+ @param[in] Select CSR read instruction select values.
+
+ @return The return value of csrrd instruction, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrRead (
+ IN UINT16 Select
+ )
+{
+ return AsmCsrRead (Select);
+}
+
+/**
+ CSR write operation.
+
+ @param[in] Select CSR write instruction select values.
+ @param[in, out] Value The csrwr will write the value.
+
+ @return The return value of csrwr instruction, that is, store the old value of
+ the register, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrWrite (
+ IN UINT16 Select,
+ IN OUT UINTN Value
+ )
+{
+ return AsmCsrWrite (Select, Value);
+}
+
+/**
+ CSR exchange operation.
+
+ @param[in] Select CSR exchange instruction select values.
+ @param[in, out] Value The csrxchg will write the value.
+ @param[in] Mask The csrxchg mask value.
+
+ @return The return value of csrxchg instruction, that is, store the old value of
+ the register, return -1 means Select is out of support.
+**/
+UINTN
+EFIAPI
+CsrXChg (
+ IN UINT16 Select,
+ IN OUT UINTN Value,
+ IN UINTN Mask
+ )
+{
+ return AsmCsrXChg (Select, Value, Mask);
+}
--
2.27.0
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next prev parent reply other threads:[~2023-11-06 3:27 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-06 3:25 [edk2-devel] [PATCH v2 00/30] Enable LoongArch virtual machine in edk2 Chao Li
2023-11-06 3:26 ` [edk2-devel] [PATCH v2 01/30] MdePkg: Add the header file named Csr.h for LoongArch64 Chao Li
2023-11-07 3:30 ` Michael D Kinney
2023-11-06 3:26 ` [edk2-devel] [PATCH v2 02/30] MdePkg: Add LoongArch64 FPU function set into BaseCpuLib Chao Li
2023-11-07 3:31 ` Michael D Kinney
2023-11-06 3:26 ` [edk2-devel] [PATCH v2 03/30] MdePkg: Add LoongArch64 exception function set into BaseLib Chao Li
2023-11-07 3:31 ` Michael D Kinney
2023-11-06 3:26 ` [edk2-devel] [PATCH v2 04/30] MdePkg: Add LoongArch64 local interrupt " Chao Li
2023-11-07 3:31 ` Michael D Kinney
2023-11-06 3:27 ` [edk2-devel] [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function Chao Li
2023-11-07 3:31 ` Michael D Kinney
2023-11-06 3:27 ` [edk2-devel] [PATCH v2 06/30] MdePkg: Add read stable counter operation for LoongArch Chao Li
2023-11-07 3:31 ` Michael D Kinney
2023-11-06 3:27 ` Chao Li [this message]
2023-11-07 3:31 ` [edk2-devel] [PATCH v2 07/30] MdePkg: Add CSR " Michael D Kinney
2023-11-06 3:27 ` [edk2-devel] [PATCH v2 08/30] MdePkg: Add IOCSR " Chao Li
2023-11-07 3:32 ` Michael D Kinney
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 09/30] UefiCpuPkg: Add LoongArch64 CPU Timer library Chao Li
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 10/30] UefiCpuPkg: Add CPU exception library for LoongArch Chao Li
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 11/30] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg Chao Li
2023-11-09 1:17 ` Andrei Warkentin
2023-11-14 2:00 ` Chao Li
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 12/30] UefiCpuPkg: Add LoongArch64CpuMmuLib " Chao Li
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 13/30] UefiCpuPkg: Add multiprocessor library for LoongArch64 Chao Li
2023-11-06 3:28 ` [edk2-devel] [PATCH v2 14/30] UefiCpuPkg: Add CpuDxe driver " Chao Li
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 15/30] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64 Chao Li
2023-11-15 18:55 ` Leif Lindholm
2023-11-16 8:15 ` Pedro Falcato
2023-11-16 9:17 ` Chao Li
2023-11-16 11:21 ` Leif Lindholm
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 16/30] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg Chao Li
2023-11-07 9:37 ` Gerd Hoffmann
2023-11-13 11:46 ` Sami Mujawar
2023-11-14 1:41 ` Chao Li
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 17/30] OvmfPkg/LoongArchVirt: Add PciCpuIo2Dxe module Chao Li
2023-11-07 9:42 ` Gerd Hoffmann
2023-11-07 10:03 ` Chao Li
2023-11-08 23:11 ` Sunil V L
2023-11-10 3:31 ` Chao Li
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 18/30] OvmfPkg/LoongArchVirt: Add stable timer driver Chao Li
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 19/30] OvmfPkg/LoongArchVirt: Add a NULL library named CollectApResouceLibNull Chao Li
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 20/30] OvmfPkg/LoongArchVirt: Add serial port library Chao Li
2023-11-07 9:47 ` Gerd Hoffmann
2023-11-07 10:12 ` Chao Li
2023-11-08 22:21 ` Laszlo Ersek
2023-11-10 4:51 ` Chao Li
2023-11-13 10:45 ` Laszlo Ersek
2023-11-06 3:29 ` [edk2-devel] [PATCH v2 21/30] OvmfPkg/LoongArchVirt: Add real time clock library Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 22/30] OvmfPkg/LoongArchVirt: Add NorFlashQemuLib Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 23/30] OvmfPkg/LoongArchVirt: Add PeiServiceTablePointerLib Chao Li
2023-11-08 22:22 ` Laszlo Ersek
2023-11-10 6:44 ` Chao Li
2023-11-13 11:02 ` Laszlo Ersek
2023-11-14 2:08 ` Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 24/30] OvmfPkg/LoongArchVirt: Add platform boot manager library Chao Li
2023-11-08 22:24 ` Laszlo Ersek
2023-11-10 7:09 ` Chao Li
2023-11-10 9:46 ` Gerd Hoffmann
2023-11-13 11:08 ` Laszlo Ersek
2023-11-15 3:21 ` Chao Li
2023-11-15 12:52 ` Laszlo Ersek
2023-11-16 7:09 ` Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 25/30] OvmfPkg/LoongArchVirt: Add FdtQemuFwCfgLib Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 26/30] OvmfPkg/LoongArchVirt: Add reset system library Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 27/30] OvmfPkg/LoongArchVirt: Support SEC phase Chao Li
2023-11-06 3:30 ` [edk2-devel] [PATCH v2 28/30] OvmfPkg/LoongArchVirt: Support PEI phase Chao Li
2023-11-06 3:31 ` [edk2-devel] [PATCH v2 29/30] OvmfPkg/LoongArchVirt: Add build file Chao Li
2023-11-06 3:31 ` [edk2-devel] [PATCH v2 30/30] OvmfPkg/LoongArchVirt: Add self introduction file Chao Li
[not found] ` <1794EAF40590BB23.26468@groups.io>
2023-11-07 6:41 ` [edk2-devel] [PATCH v2 09/30] UefiCpuPkg: Add LoongArch64 CPU Timer library Chao Li
[not found] ` <1794EB01154A1CFD.12603@groups.io>
2023-11-07 8:40 ` [edk2-devel] [PATCH v2 15/30] EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64 Chao Li
[not found] ` <1794EB0445E96DCB.26468@groups.io>
2023-11-07 8:41 ` [edk2-devel] [PATCH v2 16/30] ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkg Chao Li
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