From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 97CD97803CF for ; Thu, 9 Nov 2023 09:23:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=HeWZ8/2qe7yD9WBL2Ged3ha0p9NL90rSNIexpQ0qHxg=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699521836; v=1; b=EsmjQ/3ynIZgDX40wAUFDh1Wvx1/CNkg9xjQyTmV32pOhfjNeh7EJIGIr2LQOoJo2zN8e53E 847PZ2bQylIC9YB4/Jhc5a22i6RJypq59jdC32fQl0nflFP6aSttRy4zhUbTjv+B27tXOrshvSf hzRGXuDOqSu5MpJnLFq1ZjLo= X-Received: by 127.0.0.2 with SMTP id f3QyYY7687511x4TRm0rZGsg; Thu, 09 Nov 2023 01:23:56 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.117372.1699521835727914868 for ; Thu, 09 Nov 2023 01:23:55 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BCECE15BF; Thu, 9 Nov 2023 01:24:39 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com (e126645.nice.arm.com [10.34.100.114]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A7EC63F703; Thu, 9 Nov 2023 01:23:53 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io Cc: Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann , Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v2 2/7] MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg() Date: Thu, 9 Nov 2023 10:23:02 +0100 Message-Id: <20231109092307.1770332-3-pierre.gondois@arm.com> In-Reply-To: <20231109092307.1770332-1-pierre.gondois@arm.com> References: <20231109092307.1770332-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: tgrxV9XYk3DwNdZFNyO6yREGx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="EsmjQ/3y"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io To enable AARCH64 native instruction support for Openssl, some interfaces must be implemented. OPENSSL_cpuid_setup() allows to probe the supported features of the platform. Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing Arm64 instruction capabilities. A similar ArmReadIdAA64Isar0() function is available in the ArmPkg, but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely on the ArmPkg. Signed-off-by: Pierre Gondois --- MdePkg/Include/Library/BaseLib.h | 72 +++++++++++++++++++ .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S | 30 ++++++++ .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm | 30 ++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 2 + 4 files changed, 134 insertions(+) create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index b81c9dd83508..365d50cfb1b8 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -140,6 +140,78 @@ ArmReadCntPctReg ( VOID=0D );=0D =0D +//=0D +// Bit shifts for the ID_AA64ISAR0_EL1 register.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)=0D +=0D +//=0D +// Bit masks for the ID_AA64ISAR0_EL1 fields.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)=0D +=0D +//=0D +// Bit masks for the ID_AA64ISAR0_EL1 field values.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)=0D +=0D +/**=0D + Reads the current value of ID_AA64ISAR0_EL1 register.=0D +=0D + Reads and returns the current value of ID_AA64ISAR0_EL1.=0D + This function is only available on AARCH64.=0D +=0D + @return The current value of ID_AA64ISAR0_EL1=0D +**/=0D +UINT64=0D +EFIAPI=0D +ArmReadIdAA64Isar0Reg (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_AARCH64)=0D =0D #if defined (MDE_CPU_RISCV64)=0D diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S b/MdePk= g/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S new file mode 100644 index 000000000000..4e61b869a401 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S @@ -0,0 +1,30 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# ArmReadIdAA64Isar0Reg() for AArch64=0D +#=0D +# Copyright (c) 2021, NUVIA Inc. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +.text=0D +.p2align 2=0D +GCC_ASM_EXPORT(ArmReadIdAA64Isar0Reg)=0D +=0D +#/**=0D +# Reads the ID_AA64ISAR0 Register.=0D +#=0D +# @return The contents of the ID_AA64ISAR0 register.=0D +#=0D +#**/=0D +#UINT64=0D +#EFIAPI=0D +#ArmReadIdAA64Isar0Reg (=0D +# VOID=0D +# );=0D +#=0D +ASM_PFX(ArmReadIdAA64Isar0Reg):=0D + AARCH64_BTI(c)=0D + mrs x0, id_aa64isar0_el1=0D + ret=0D diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm b/Mde= Pkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm new file mode 100644 index 000000000000..790fb905d001 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm @@ -0,0 +1,30 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; ArmReadIdAA64Isar0Reg() for AArch64=0D +;=0D +; Copyright (c) 2021, NUVIA Inc. All rights reserved.
=0D +;=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D + EXPORT ArmReadIdAA64Isar0Reg=0D + AREA BaseLib_LowLevel, CODE, READONLY=0D +=0D +;/**=0D +; Reads the ID_AA64ISAR0 Register.=0D +;=0D +; @return The contents of the ID_AA64ISAR0 register.=0D +;=0D +;**/=0D +;UINT64=0D +;EFIAPI=0D +;ArmReadIdAA64Isar0Reg (=0D +; VOID=0D +; );=0D +;=0D +ArmReadIdAA64Isar0Reg=0D + mrs x0, id_aa64isar0_el1=0D + ret=0D +=0D + END=0D diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 24e5e6c3ecb5..299bcaa56d39 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -377,6 +377,7 @@ [Sources.AARCH64] AArch64/CpuBreakpoint.S | GCC=0D AArch64/SpeculationBarrier.S | GCC=0D AArch64/ArmReadCntPctReg.S | GCC=0D + AArch64/ArmReadIdAA64Isar0Reg.S | GCC=0D =0D AArch64/MemoryFence.asm | MSFT=0D AArch64/SwitchStack.asm | MSFT=0D @@ -387,6 +388,7 @@ [Sources.AARCH64] AArch64/CpuBreakpoint.asm | MSFT=0D AArch64/SpeculationBarrier.asm | MSFT=0D AArch64/ArmReadCntPctReg.asm | MSFT=0D + AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT=0D =0D [Sources.RISCV64]=0D Math64.c=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110955): https://edk2.groups.io/g/devel/message/110955 Mute This Topic: https://groups.io/mt/102482400/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-