From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 05A13740062 for ; Fri, 10 Nov 2023 10:48:40 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=MOyTz19vDnUqONVWlWfCVLg9TCML9mSA0FIPgReRWbg=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699613319; v=1; b=i9CnovgTUhnpamAe2bJIaD6LO2asye99dmsO9kuPSAKWfEB0pLpyyeeuUg0Rv0uQe7FCzw1/ PNdkk6hEXCYhtDDdT18++a6+agqD+UxMSV0BMyEiAySo8VtVMdzC7zdicwh8OavSXMgFFOWSH8U wYQvy9SWiGMVQWsUOnHFJq/I= X-Received: by 127.0.0.2 with SMTP id B8bQYY7687511x1sKhVAwNMn; Fri, 10 Nov 2023 02:48:39 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.24748.1699613318916146090 for ; Fri, 10 Nov 2023 02:48:39 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3174612FC; Fri, 10 Nov 2023 02:49:23 -0800 (PST) X-Received: from e126645.arm.com (unknown [10.57.82.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 36FBB3F7C5; Fri, 10 Nov 2023 02:48:36 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io Cc: Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v3 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks Date: Fri, 10 Nov 2023 11:48:09 +0100 Message-Id: <20231110104810.2038376-6-pierre.gondois@arm.com> In-Reply-To: <20231110104810.2038376-1-pierre.gondois@arm.com> References: <20231110104810.2038376-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: BeuRTRF5db1Obwg9zoZickfPx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=i9CnovgT; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Add AARCH64 specific implementations of: - OPENSSL_cpuid_setup(), probing hardware capabilitie (presence of FEAT_AES, etc.) - OPENSSL_rdtsc(), returning non-trusted entropy by accessing system counter. Signed-off-by: Pierre Gondois --- .../Library/OpensslLib/OpensslLibAccel.inf | 7 ++ .../OpensslLib/OpensslLibFullAccel.inf | 7 ++ .../OpensslLib/OpensslStub/AArch64Cap.c | 107 ++++++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/L= ibrary/OpensslLib/OpensslLibAccel.inf index 3d1a9638b1c1..08e8be6ea9e1 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf @@ -1329,6 +1329,7 @@ [Sources.X64] # Autogenerated files list ends here=0D =0D [Sources.AARCH64]=0D + OpensslStub/AArch64Cap.c=0D # Autogenerated files list starts here=0D $(OPENSSL_PATH)/crypto/aes/aes_cbc.c=0D $(OPENSSL_PATH)/crypto/aes/aes_cfb.c=0D @@ -1955,11 +1956,17 @@ [Packages] MdePkg/MdePkg.dec=0D CryptoPkg/CryptoPkg.dec=0D =0D +[Packages.AARCH64]=0D + ArmPkg/ArmPkg.dec=0D +=0D [LibraryClasses]=0D BaseLib=0D DebugLib=0D RngLib=0D =0D +[LibraryClasses.AARCH64]=0D + ArmLib=0D +=0D [BuildOptions]=0D #=0D # Disables the following Visual Studio compiler warnings brought by open= ssl source,=0D diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoP= kg/Library/OpensslLib/OpensslLibFullAccel.inf index e7e83d419f4b..2a01ffe06bd7 100644 --- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf +++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf @@ -1432,6 +1432,7 @@ [Sources.X64] # Autogenerated files list ends here=0D =0D [Sources.AARCH64]=0D + OpensslStub/AArch64Cap.c=0D # Autogenerated files list starts here=0D $(OPENSSL_PATH)/crypto/aes/aes_cbc.c=0D $(OPENSSL_PATH)/crypto/aes/aes_cfb.c=0D @@ -2107,11 +2108,17 @@ [Packages] MdePkg/MdePkg.dec=0D CryptoPkg/CryptoPkg.dec=0D =0D +[Packages.AARCH64]=0D + ArmPkg/ArmPkg.dec=0D +=0D [LibraryClasses]=0D BaseLib=0D DebugLib=0D RngLib=0D =0D +[LibraryClasses.AARCH64]=0D + ArmLib=0D +=0D [BuildOptions]=0D #=0D # Disables the following Visual Studio compiler warnings brought by open= ssl source,=0D diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/Crypto= Pkg/Library/OpensslLib/OpensslStub/AArch64Cap.c new file mode 100644 index 000000000000..4c57334316ca --- /dev/null +++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c @@ -0,0 +1,107 @@ +/** @file=0D + Arm capabilities probing.=0D +=0D + Copyright (c) 2023, Arm Limited. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include "crypto/arm_arch.h"=0D +=0D +#include =0D +=0D +/** Get bits from a value.=0D +=0D + Shift the input value from 'shift' bits and apply 'mask'.=0D +=0D + @param value The value to get the bits from.=0D + @param shift Index of the bits to read.=0D + @param mask Mask to apply to the value once shifted.=0D +=0D + @return The desired bitfield from the value.=0D +**/=0D +#define GET_BITFIELD(value, shift, mask) \=0D + ((value >> shift) & mask)=0D +=0D +UINT32 OPENSSL_armcap_P =3D 0;=0D +=0D +void=0D +OPENSSL_cpuid_setup (=0D + void=0D + )=0D +{=0D + UINT64 Isar0;=0D +=0D + OPENSSL_armcap_P =3D 0;=0D + Isar0 =3D ArmReadIdAA64Isar0 ();=0D +=0D + /* Access to EL0 registers is possible from higher ELx. */=0D + OPENSSL_armcap_P |=3D ARMV8_CPUID;=0D + /* Access to Physical timer is possible. */=0D + OPENSSL_armcap_P |=3D ARMV7_TICK;=0D +=0D + /* Neon support is not guaranteed, but it is assumed to be present.=0D + Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support=0D + */=0D + OPENSSL_armcap_P |=3D ARMV7_NEON;=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_AES;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA1_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA1;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_MASK=0D + ) !=3D 0)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA256;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_MASK=0D + ) >=3D ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_PMULL;=0D + }=0D +=0D + if (GET_BITFIELD (=0D + Isar0,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_MASK=0D + ) >=3D ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK)=0D + {=0D + OPENSSL_armcap_P |=3D ARMV8_SHA512;=0D + }=0D +}=0D +=0D +/** Read system counter value.=0D +=0D + Used to get some non-trusted entropy.=0D +=0D + @return Lower bits of the physical counter.=0D +**/=0D +uint32_t=0D +OPENSSL_rdtsc (=0D + void=0D + )=0D +{=0D + return (UINT32)ArmReadCntPct ();=0D +}=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111033): https://edk2.groups.io/g/devel/message/111033 Mute This Topic: https://groups.io/mt/102504424/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-