From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D02C6941269 for ; Mon, 13 Nov 2023 05:59:58 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=x7/FMifQCFWF8VOHhkwF59QjEk9+QQ7z3yHlGW85VHc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1699855197; v=1; b=ceDychmfUh1lbnVU949AD2k13feZVcSKBQc+7p0dpgGpfjXNPdczIm5Zn9n6slEyrwmZoujW mjH1v3Fehi9w0NblzQEFrR3EIFTPA8mpifvMG/dcdfckmqRuj6oHUQZBHmP8qUip/C0hyvfm9PF 82pe/3ERLX7UvXFd6lTlEF5Y= X-Received: by 127.0.0.2 with SMTP id SEPOYY7687511xvuBkttAChO; Sun, 12 Nov 2023 21:59:57 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.31633.1699855196531823285 for ; Sun, 12 Nov 2023 21:59:56 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10892"; a="476603916" X-IronPort-AV: E=Sophos;i="6.03,298,1694761200"; d="scan'208";a="476603916" X-Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2023 21:59:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,298,1694761200"; d="scan'208";a="12004934" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by orviesa001.jf.intel.com with ESMTP; 12 Nov 2023 21:59:53 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Yuanhao Xie , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4] UefiCpuPkg/MpInitLib: Enable execute disable bit. Date: Mon, 13 Nov 2023 13:59:48 +0800 Message-Id: <20231113055948.1773-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 8XKzHKnIyz0XyBLHiz4l2woXx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ceDychmf; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Yuanhao Xie This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation. The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters . Based on SDM: If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved. Signed-off-by: Yuanhao Xie Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 14 +++++++++++--- UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 9a6ec5db5c..f29e66a14f 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -910,9 +910,16 @@ DxeApEntryPoint ( CPU_MP_DATA *CpuMpData ) { - UINTN ProcessorNumber; + UINTN ProcessorNumber; + MSR_IA32_EFER_REGISTER EferMsr; GetProcessorNumber (CpuMpData, &ProcessorNumber); + if (CpuMpData->EnableExecuteDisableForSwitchContext) { + EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); + EferMsr.Bits.NXE = 1; + AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); + } + RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); PlaceAPInMwaitLoopOrRunLoop ( @@ -2188,8 +2195,9 @@ MpInitLibInitialize ( if (MpHandOff->WaitLoopExecutionMode == sizeof (VOID *)) { ASSERT (CpuMpData->ApLoopMode != ApInHltLoop); - CpuMpData->FinishedCount = 0; - CpuMpData->InitFlag = ApInitDone; + CpuMpData->FinishedCount = 0; + CpuMpData->InitFlag = ApInitDone; + CpuMpData->EnableExecuteDisableForSwitchContext = IsBspExecuteDisableEnabled (); SaveCpuMpData (CpuMpData); // // In scenarios where both the PEI and DXE phases run in the same diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 763db4963d..af296f6ac0 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -270,6 +270,7 @@ struct _CPU_MP_DATA { UINT64 TotalTime; EFI_EVENT WaitEvent; UINTN **FailedCpuList; + BOOLEAN EnableExecuteDisableForSwitchContext; AP_INIT_STATE InitFlag; BOOLEAN SwitchBspFlag; -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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