From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 535379410A0 for ; Mon, 20 Nov 2023 04:21:25 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=HNIpjPsaxc+n2p7CsRQTwqVHTLjE8OcoOIDlD60blr8=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1700454084; v=1; b=JZZ16Mj+8x/Rm/NZB7a2r7mHzv65kzCqlnqlVXgN401My/2jjlL7qaRLPeSNWKqv/i3SD2rR 6v3etyU5dgywxNIPuVLDBg8OUoi+k26WXeHZEYdy3suncSyUQe5CdpGMPSL8LZIVELzmpeEr0RW fCVDMboAZPBHDUfZ5arXngEE= X-Received: by 127.0.0.2 with SMTP id BIkdYY7687511xMi0mVbbIMu; Sun, 19 Nov 2023 20:21:24 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.43973.1700454081395369065 for ; Sun, 19 Nov 2023 20:21:22 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10899"; a="455871831" X-IronPort-AV: E=Sophos;i="6.04,212,1695711600"; d="scan'208";a="455871831" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2023 20:19:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10899"; a="939678718" X-IronPort-AV: E=Sophos;i="6.04,212,1695711600"; d="scan'208";a="939678718" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by orsmga005.jf.intel.com with ESMTP; 19 Nov 2023 20:18:59 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Yuanhao Xie , Laszlo Ersek , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V5 1/2] UefiCpuPkg/MpInitLib: Enable execute disable bit. Date: Mon, 20 Nov 2023 12:18:45 +0800 Message-Id: <20231120041846.2221-2-yuanhao.xie@intel.com> In-Reply-To: <20231120041846.2221-1-yuanhao.xie@intel.com> References: <20231120041846.2221-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: aZfdaJjzLXs37UQJ08DJ5L7Yx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=JZZ16Mj+; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Yuanhao Xie This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation. The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters . Based on SDM: If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved. Signed-off-by: Yuanhao Xie Reviewed-by: Laszlo Ersek Cc: Laszlo Ersek lersek@redhat.com Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 14 +++++++++++--- UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 9a6ec5db5c..f29e66a14f 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -910,9 +910,16 @@ DxeApEntryPoint ( CPU_MP_DATA *CpuMpData ) { - UINTN ProcessorNumber; + UINTN ProcessorNumber; + MSR_IA32_EFER_REGISTER EferMsr; GetProcessorNumber (CpuMpData, &ProcessorNumber); + if (CpuMpData->EnableExecuteDisableForSwitchContext) { + EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); + EferMsr.Bits.NXE = 1; + AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); + } + RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); PlaceAPInMwaitLoopOrRunLoop ( @@ -2188,8 +2195,9 @@ MpInitLibInitialize ( if (MpHandOff->WaitLoopExecutionMode == sizeof (VOID *)) { ASSERT (CpuMpData->ApLoopMode != ApInHltLoop); - CpuMpData->FinishedCount = 0; - CpuMpData->InitFlag = ApInitDone; + CpuMpData->FinishedCount = 0; + CpuMpData->InitFlag = ApInitDone; + CpuMpData->EnableExecuteDisableForSwitchContext = IsBspExecuteDisableEnabled (); SaveCpuMpData (CpuMpData); // // In scenarios where both the PEI and DXE phases run in the same diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 763db4963d..0afac7c78c 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -270,6 +270,7 @@ struct _CPU_MP_DATA { UINT64 TotalTime; EFI_EVENT WaitEvent; UINTN **FailedCpuList; + BOOLEAN EnableExecuteDisableForSwitchContext AP_INIT_STATE InitFlag; BOOLEAN SwitchBspFlag; -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111447): https://edk2.groups.io/g/devel/message/111447 Mute This Topic: https://groups.io/mt/102702056/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-