From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 4B98A740034 for ; Mon, 20 Nov 2023 13:48:51 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=JlHuVgT05Pcnt/7cBBohl4uNlniJaJ+d3ShnFsiQhHw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1700488129; v=1; b=gG30eiVDjK+4r9E7mN/jF5/6juc/5qN/dKm6d2c0O2wXWkESg4DUmH40fsiBx3U1novNizHL yDPje06WzCA7fzsQU+r48YObZAfQOSjhKOEZdxQIJv25O3GvAHw2CMmJ+1rlX25dNTNZbAJ2mD2 wM6oi99TZyLEgjXfHa7b0p2Q= X-Received: by 127.0.0.2 with SMTP id WS8yYY7687511xeZuJiWZX56; Mon, 20 Nov 2023 05:48:49 -0800 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.50553.1700488129368249490 for ; Mon, 20 Nov 2023 05:48:49 -0800 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D18B1042; Mon, 20 Nov 2023 05:49:35 -0800 (PST) X-Received: from cam-smtp0.cambridge.arm.com (e126645.nice.arm.com [10.34.100.114]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 945E23F6C4; Mon, 20 Nov 2023 05:48:47 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io Cc: Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register Date: Mon, 20 Nov 2023 14:48:21 +0100 Message-Id: <20231120134826.1288260-2-pierre.gondois@arm.com> In-Reply-To: <20231120134826.1288260-1-pierre.gondois@arm.com> References: <20231120134826.1288260-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: bz42UAj1VORL1mATzg1pTf04x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=gG30eiVD; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Add macro definitions and helper functions to access AArch64 capabilities described in the AA64Isar0 register. Signed-off-by: Pierre Gondois --- ArmPkg/Include/Chipset/AArch64.h | 60 +++- ArmPkg/Include/Library/ArmLib.h | 228 ++++++++++++- ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 367 +++++++++++++++++++++ 3 files changed, 653 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArc= h64.h index 5390bf0a2774..97c20e71a811 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -1,7 +1,7 @@ /** @file=0D =0D Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=0D - Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
=0D + Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -127,6 +127,64 @@ // build for ARMv8.0, we need to define the register here.=0D #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2=0D =0D +//=0D +// Bit shifts for the ID_AA64ISAR0_EL1 register.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)=0D +=0D +//=0D +// Bit masks for the ID_AA64ISAR0_EL1 fields.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)=0D +=0D +//=0D +// Bit masks for the ID_AA64ISAR0_EL1 field values.=0D +//=0D +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)=0D +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)=0D +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)=0D +=0D #define VECTOR_BASE(tbl) \=0D .section .text.##tbl##,"ax"; \=0D .align 11; \=0D diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLi= b.h index 6aa8a48f07f3..a176fcd7bf0a 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -1,7 +1,7 @@ /** @file=0D =0D Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=0D - Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
=0D + Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.
=0D Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -805,6 +805,232 @@ ArmHasEte ( VOID=0D );=0D =0D +/** Read AA64Isar0 register.=0D +=0D + @return AA64Isar0's register value.=0D +**/=0D +UINTN=0D +EFIAPI=0D +ArmReadIdAA64Isar0 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_AES.=0D +=0D + @retval TRUE FEAT_AES is implemented.=0D + @retval FALSE FEAT_AES is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasAes (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_PMULL.=0D +=0D + @retval TRUE FEAT_PMULL is implemented.=0D + @retval FALSE FEAT_PMULL is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasPmull (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA1.=0D +=0D + @retval TRUE FEAT_SHA1 is implemented.=0D + @retval FALSE FEAT_SHA1 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha1 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA256.=0D +=0D + @retval TRUE FEAT_SHA256 is implemented.=0D + @retval FALSE FEAT_SHA256 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha256 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA512.=0D +=0D + @retval TRUE FEAT_SHA512 is implemented.=0D + @retval FALSE FEAT_SHA512 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha512 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements CRC32 instruction.=0D +=0D + @retval TRUE CRC32 instruction is implemented.=0D + @retval FALSE CRC32 instruction is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasCrc32 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_LSE.=0D +=0D + @retval TRUE FEAT_LSE is implemented.=0D + @retval FALSE FEAT_LSE is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasLse (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_RDM.=0D +=0D + @retval TRUE FEAT_RDM is implemented.=0D + @retval FALSE FEAT_RDM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasRdm (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA3.=0D +=0D + @retval TRUE FEAT_SHA3 is implemented.=0D + @retval FALSE FEAT_SHA3 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha3 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SM3.=0D +=0D + @retval TRUE FEAT_SM3 is implemented.=0D + @retval FALSE FEAT_SM3 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSm3 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SM4.=0D +=0D + @retval TRUE FEAT_SM4 is implemented.=0D + @retval FALSE FEAT_SM4 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSm4 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_DotProd.=0D +=0D + @retval TRUE FEAT_DotProd is implemented.=0D + @retval FALSE FEAT_DotProd is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasDp (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FHM.=0D +=0D + @retval TRUE FEAT_FHM is implemented.=0D + @retval FALSE FEAT_FHM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFhm (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FlagM.=0D +=0D + @retval TRUE FEAT_FlagM is implemented.=0D + @retval FALSE FEAT_FlagM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFlagm (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FlagM2.=0D +=0D + @retval TRUE FEAT_FlagM2 is implemented.=0D + @retval FALSE FEAT_FlagM2 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFlagm2 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_TLBIOS.=0D +=0D + @retval TRUE FEAT_TLBIOS is implemented.=0D + @retval FALSE FEAT_TLBIOS is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasTlbios (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_TLBIRANGE.=0D +=0D + @retval TRUE FEAT_TLBIRANGE is implemented.=0D + @retval FALSE FEAT_TLBIRANGE is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasTlbirange (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_RNG.=0D +=0D + @retval TRUE FEAT_RNG is implemented.=0D + @retval FALSE FEAT_RNG is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasRndr (=0D + VOID=0D + );=0D +=0D #endif // MDE_CPU_AARCH64=0D =0D #ifdef MDE_CPU_ARM=0D diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/Ar= mLib/AArch64/AArch64Lib.c index 87285465871d..c64c015844a6 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -18,6 +18,19 @@ #include "AArch64Lib.h"=0D #include "ArmLibPrivate.h"=0D =0D +/** Get bits from a value.=0D +=0D + Shift the input value from 'shift' bits and apply 'mask'.=0D +=0D + @param value The value to get the bits from.=0D + @param shift Index of the bits to read.=0D + @param mask Mask to apply to the value once shifted.=0D +=0D + @return The desired bitfield from the value.=0D +**/=0D +#define GET_BITFIELD(value, shift, mask) \=0D + ((value >> shift) & mask)=0D +=0D VOID=0D AArch64DataCacheOperation (=0D IN AARCH64_CACHE_OPERATION DataCacheOperation=0D @@ -150,3 +163,357 @@ ArmHasEte ( // The ID_AA64DFR0_EL1.TraceVer field identifies the presence of FEAT_ET= E.=0D return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRACEVER) !=3D 0);=0D }=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_AES.=0D +=0D + @retval TRUE FEAT_AES is implemented.=0D + @retval FALSE FEAT_AES is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasAes (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_PMULL.=0D +=0D + @retval TRUE FEAT_PMULL is implemented.=0D + @retval FALSE FEAT_PMULL is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasPmull (=0D + VOID=0D + )=0D +{=0D + //=0D + // Only check BIT1 of AES field, bits [7:4]=0D + //=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA1.=0D +=0D + @retval TRUE FEAT_SHA1 is implemented.=0D + @retval FALSE FEAT_SHA1 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha1 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA1_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA256.=0D +=0D + @retval TRUE FEAT_SHA256 is implemented.=0D + @retval FALSE FEAT_SHA256 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha256 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA512.=0D +=0D + @retval TRUE FEAT_SHA512 is implemented.=0D + @retval FALSE FEAT_SHA512 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha512 (=0D + VOID=0D + )=0D +{=0D + //=0D + // Only check BIT1 of SHA2 field, bits [15:12]=0D + //=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements CRC32 instruction.=0D +=0D + @retval TRUE CRC32 instruction is implemented.=0D + @retval FALSE CRC32 instruction is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasCrc32 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_CRC32_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_LSE.=0D +=0D + @retval TRUE FEAT_LSE is implemented.=0D + @retval FALSE FEAT_LSE is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasLse (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_RDM.=0D +=0D + @retval TRUE FEAT_RDM is implemented.=0D + @retval FALSE FEAT_RDM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasRdm (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_RDM_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_RDM_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SHA3.=0D +=0D + @retval TRUE FEAT_SHA3 is implemented.=0D + @retval FALSE FEAT_SHA3 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSha3 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SHA3_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SM3.=0D +=0D + @retval TRUE FEAT_SM3 is implemented.=0D + @retval FALSE FEAT_SM3 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSm3 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SM3_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SM3_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_SM4.=0D +=0D + @retval TRUE FEAT_SM4 is implemented.=0D + @retval FALSE FEAT_SM4 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasSm4 (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_SM4_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_SM4_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_DotProd.=0D +=0D + @retval TRUE FEAT_DotProd is implemented.=0D + @retval FALSE FEAT_DotProd is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasDp (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_DP_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_DP_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FHM.=0D +=0D + @retval TRUE FEAT_FHM is implemented.=0D + @retval FALSE FEAT_FHM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFhm (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_FHM_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_FHM_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FlagM.=0D +=0D + @retval TRUE FEAT_FlagM is implemented.=0D + @retval FALSE FEAT_FlagM is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFlagm (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_TS_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_TS_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_FlagM2.=0D +=0D + @retval TRUE FEAT_FlagM2 is implemented.=0D + @retval FALSE FEAT_FlagM2 is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasFlagm2 (=0D + VOID=0D + )=0D +{=0D + //=0D + // Only check BIT1 of TS field, bits [55:52]=0D + //=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_TS_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_TLBIOS.=0D +=0D + @retval TRUE FEAT_TLBIOS is implemented.=0D + @retval FALSE FEAT_TLBIOS is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasTlbios (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_TLB_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_TLBIRANGE.=0D +=0D + @retval TRUE FEAT_TLBIRANGE is implemented.=0D + @retval FALSE FEAT_TLBIRANGE is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasTlbirange (=0D + VOID=0D + )=0D +{=0D + //=0D + // Only check BIT1 of TLB field, bits [59:56]=0D + //=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK=0D + ) !=3D 0;=0D +}=0D +=0D +/**=0D + Checks whether the CPU implements FEAT_RNG.=0D +=0D + @retval TRUE FEAT_RNG is implemented.=0D + @retval FALSE FEAT_RNG is not implemented.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +ArmHasRndr (=0D + VOID=0D + )=0D +{=0D + return GET_BITFIELD (=0D + ArmReadIdAA64Isar0 (),=0D + ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT,=0D + ARM_ID_AA64ISAR0_EL1_RNDR_MASK=0D + ) !=3D 0;=0D +}=0D --=20 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111474): https://edk2.groups.io/g/devel/message/111474 Mute This Topic: https://groups.io/mt/102707262/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-