From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 116157803D2 for ; Wed, 22 Nov 2023 06:09:01 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=uIA4pYmgiBMC3OP27N0MG0bVhd6tjUtieG62Fs2q15Y=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1700633340; v=1; b=B0HO5tWAI0OPUecMzPdss/11+SjZsF5Qw9iqXufATk1G11QhO0Pn7T/CS9h10LqOlH8lRQD+ 1oDYzBYdLy3UHnYuLXIIXLmi8BRlPBW9YGwTZ00voHKjAm3AGKJ5DjfmtE+J4feB51LSeqADlcp GEPPAMxu1CCGEhVLmyxnyiDE= X-Received: by 127.0.0.2 with SMTP id hYb2YY7687511x2DDAvOgrP1; Tue, 21 Nov 2023 22:09:00 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.13638.1700633335895148945 for ; Tue, 21 Nov 2023 22:09:00 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="372166246" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="372166246" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 22:08:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="15129539" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by fmviesa001.fm.intel.com with ESMTP; 21 Nov 2023 22:08:57 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: xieyuanh , Ray Ni , Eric Dong , Rahul Kumar , Tom Lendacky , Laszlo Ersek Subject: [edk2-devel] [Patch V3 1/3] UefiCpuPkg/MpInitLib: Eliminate redundant microcode loading in DXE. Date: Wed, 22 Nov 2023 14:08:32 +0800 Message-Id: <20231122060834.3467-2-yuanhao.xie@intel.com> In-Reply-To: <20231122060834.3467-1-yuanhao.xie@intel.com> References: <20231122060834.3467-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: aM2gZBpPjfKVa6ev5dnYNPB2x7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=B0HO5tWA; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io The DXE stage's Microcode loading process has been elimincated by: 1. Let ShadowMicrocodeUpdatePatch and MicrocodeDetect for BSP performed only during the PEI phase. DXE skip those actions. 2. BSP in DXE WakeUpAp only for synchronizing MTRR settings, not loading microcode. Synchronizing the MTRR table to the AP is always essential. During the DXE phase, it cannot be omitted like loading microcode, as the PEI and DXE may be in different bit modes. Cc: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Tom Lendacky Cc: Laszlo Ersek Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 9a6ec5db5c..c26a17e1db 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -451,12 +451,19 @@ ApInitializeSync ( CpuMpData = (CPU_MP_DATA *)Buffer; Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); ASSERT_EFI_ERROR (Status); + ASSERT (CpuMpData->InitFlag == ApInitReconfig || CpuMpData->InitFlag == ApInitDone); + if (CpuMpData->InitFlag != ApInitReconfig) { + // + // Load microcode on AP for PEI phase. + // During the DXE phase, it cannot omitted. + // + MicrocodeDetect (CpuMpData, ProcessorNumber); + } + // - // Load microcode on AP - // - MicrocodeDetect (CpuMpData, ProcessorNumber); - // - // Sync BSP's MTRR table to AP + // Synchronizing the MTRR table to the AP is always essential. + // During the DXE phase, it cannot be omitted like loading microcode, + // as the PEI and DXE may be in different bit modes. // MtrrSetAllMtrrs (&CpuMpData->MtrrTable); } @@ -2224,29 +2231,25 @@ MpInitLibInitialize ( } } - if (!GetMicrocodePatchInfoFromHob ( - &CpuMpData->MicrocodePatchAddress, - &CpuMpData->MicrocodePatchRegionSize - )) - { + if (MpHandOff == NULL) { // // The microcode patch information cache HOB does not exist, which means // the microcode patches data has not been loaded into memory yet // ShadowMicrocodeUpdatePatch (CpuMpData); + // + // Detect and apply Microcode on BSP + // + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); } - // - // Detect and apply Microcode on BSP - // - MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); // // Store BSP's MTRR setting // MtrrGetAllMtrrs (&CpuMpData->MtrrTable); // - // Wakeup APs to do some AP initialize sync (Microcode & MTRR) + // Wakeup APs to do some AP initialize sync (MTRR and/or Microcode). // if (CpuMpData->CpuCount > 1) { if (MpHandOff != NULL) { @@ -2258,6 +2261,11 @@ MpInitLibInitialize ( CpuMpData->InitFlag = ApInitReconfig; } + // + // Wake up the AP to perform some AP initialization synchronization. + // 1. For PEI stage, load microcode and synchronize MTRR, + // 2. For the DXE phase, only synchronize MTRR. + // WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); // // Wait for all APs finished initialization -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111595): https://edk2.groups.io/g/devel/message/111595 Mute This Topic: https://groups.io/mt/102744598/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-