From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 16973AC0C04 for ; Wed, 22 Nov 2023 06:09:12 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=k8lNoiff7VvFqLK1hXaqOJsIZxIgIFzS3DR58Zp5b0E=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1700633351; v=1; b=YorudtQEkG+9C5WsUR6iKh3grglsxDupgr7TEPF9wqvbRrsPBV6gnS3k0ynabFXWJrBX1GDa aZNCDXv1CH411mlsiBKrXj4V12cagm7d8O10VU/CMyYXIAF6peDc4X9id+8LCjSr7hiyw2oLQNA 74nbc6iKwPpsasRHUy/XY8Cg= X-Received: by 127.0.0.2 with SMTP id N5ZvYY7687511xYgVpuM99nH; Tue, 21 Nov 2023 22:09:11 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.13638.1700633335895148945 for ; Tue, 21 Nov 2023 22:09:06 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="372166281" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="372166281" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 22:09:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="15129583" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by fmviesa001.fm.intel.com with ESMTP; 21 Nov 2023 22:09:04 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: xieyuanh , Ray Ni , Eric Dong , Rahul Kumar , Tom Lendacky , Laszlo Ersek Subject: [edk2-devel] [Patch V3 3/3] UefiCpuPkg/MpInitLib: Extract Dump Microcode Revision as function. Date: Wed, 22 Nov 2023 14:08:34 +0800 Message-Id: <20231122060834.3467-4-yuanhao.xie@intel.com> In-Reply-To: <20231122060834.3467-1-yuanhao.xie@intel.com> References: <20231122060834.3467-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 26MumWcYSZ8CPDYqiDkagODHx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=YorudtQE; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io There is no functional changes, only extract DumpMicrocodeRevision since only in PEI BSP will detect, apply microcode, and APs will sync microcode. Cc: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Tom Lendacky Cc: Laszlo Ersek Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/Microcode.c | 91 +++++++++++++++++++++++++++++++++++++++++++++---------------------------------------------- UefiCpuPkg/Library/MpInitLib/MpLib.c | 31 ++----------------------------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 31 ++++++++++--------------------- 3 files changed, 57 insertions(+), 96 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c index 11720560af..c0ca85543a 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -322,65 +322,64 @@ OnExit: } /** - Shadow the required microcode patches data into memory. + Dump the microcode revision for each core. - @param[in, out] CpuMpData The pointer to CPU MP Data structure. -**/ + @param[in] CpuMpData Pointer to CPU MP Data + **/ VOID -ShadowMicrocodeUpdatePatch ( - IN OUT CPU_MP_DATA *CpuMpData +DumpMicrocodeRevision ( + IN CPU_MP_DATA *CpuMpData ) { - EFI_STATUS Status; + UINT32 ThreadId; + UINT32 ExpectedMicrocodeRevision; + CPU_INFO_IN_HOB *CpuInfoInHob; + UINTN Index; - Status = PlatformShadowMicrocode (CpuMpData); - if (EFI_ERROR (Status)) { - ShadowMicrocodePatchByPcd (CpuMpData); + // + // Dump the microcode revision for each core. + // + DEBUG_CODE_BEGIN (); + CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; + for (Index = 0; Index < CpuMpData->CpuCount; Index++) { + GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId); + if (ThreadId == 0) { + // + // MicrocodeDetect() loads microcode in first thread of each core, so, + // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core. + // + ExpectedMicrocodeRevision = 0; + if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) { + ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision; + } + + DEBUG (( + DEBUG_INFO, + "CPU[%04d]: Microcode revision = %08x, expected = %08x\n", + Index, + CpuMpData->CpuData[Index].MicrocodeRevision, + ExpectedMicrocodeRevision + )); + } } + + DEBUG_CODE_END (); } /** - Get the cached microcode patch base address and size from the microcode patch - information cache HOB. - - @param[out] Address Base address of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - @param[out] RegionSize Size of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - - @retval TRUE The microcode patch information cache HOB is found. - @retval FALSE The microcode patch information cache HOB is not found. + Shadow the required microcode patches data into memory. + @param[in, out] CpuMpData The pointer to CPU MP Data structure. **/ -BOOLEAN -GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize +VOID +ShadowMicrocodeUpdatePatch ( + IN OUT CPU_MP_DATA *CpuMpData ) { - EFI_HOB_GUID_TYPE *GuidHob; - EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob; + EFI_STATUS Status; - GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid); - if (GuidHob == NULL) { - DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __func__)); - return FALSE; + Status = PlatformShadowMicrocode (CpuMpData); + if (EFI_ERROR (Status)) { + ShadowMicrocodePatchByPcd (CpuMpData); } - - MicrocodePathHob = GET_GUID_HOB_DATA (GuidHob); - - *Address = MicrocodePathHob->MicrocodePatchAddress; - *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize; - - DEBUG (( - DEBUG_INFO, - "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", - __func__, - *Address, - *RegionSize - )); - - return TRUE; } diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 538095d3bb..2fd96bf0bc 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -2282,37 +2282,10 @@ MpInitLibInitialize ( } } - // - // Dump the microcode revision for each core. - // - DEBUG_CODE_BEGIN (); - UINT32 ThreadId; - UINT32 ExpectedMicrocodeRevision; - - CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; - for (Index = 0; Index < CpuMpData->CpuCount; Index++) { - GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId); - if (ThreadId == 0) { - // - // MicrocodeDetect() loads microcode in first thread of each core, so, - // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core. - // - ExpectedMicrocodeRevision = 0; - if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) { - ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision; - } - - DEBUG (( - DEBUG_INFO, - "CPU[%04d]: Microcode revision = %08x, expected = %08x\n", - Index, - CpuMpData->CpuData[Index].MicrocodeRevision, - ExpectedMicrocodeRevision - )); - } + if (MpHandOff == NULL) { + DumpMicrocodeRevision (CpuMpData); } - DEBUG_CODE_END (); // // Initialize global data for MP support // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 763db4963d..fd302e6845 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -735,34 +735,23 @@ MicrocodeDetect ( ); /** - Shadow the required microcode patches data into memory. + Dump the microcode revision for each core. - @param[in, out] CpuMpData The pointer to CPU MP Data structure. -**/ + @param[in] CpuMpData Pointer to CPU MP Data + **/ VOID -ShadowMicrocodeUpdatePatch ( - IN OUT CPU_MP_DATA *CpuMpData +DumpMicrocodeRevision ( + IN CPU_MP_DATA *CpuMpData ); /** - Get the cached microcode patch base address and size from the microcode patch - information cache HOB. - - @param[out] Address Base address of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - @param[out] RegionSize Size of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - - @retval TRUE The microcode patch information cache HOB is found. - @retval FALSE The microcode patch information cache HOB is not found. + Shadow the required microcode patches data into memory. + @param[in, out] CpuMpData The pointer to CPU MP Data structure. **/ -BOOLEAN -GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize +VOID +ShadowMicrocodeUpdatePatch ( + IN OUT CPU_MP_DATA *CpuMpData ); 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