From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id EF3CA940FE3 for ; Fri, 24 Nov 2023 02:56:44 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=LnWpF5hh2wkid+/XiuhsSlQFncjbAAlvjoHKsnRxD+k=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1700794603; v=1; b=j8vOnJBWvgrFgaTEHu7I2a0AWbxYi7EdOIaqqw7ifSL2DYVf7iQfyLGNvkg7eTRVEkUC5jz2 SoDxiv0RAj11qvYstQtZRjp02TsCrCXUOiyf5+b/XPGx7Xjnk/6oKGW9YdKJ+H3FdyRZtUwQaLi OsZrfFQrXEhP2I77zIbrt51Q= X-Received: by 127.0.0.2 with SMTP id 0pAfYY7687511xRAlD4uBSEL; Thu, 23 Nov 2023 18:56:43 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.128508.1700794600506959702 for ; Thu, 23 Nov 2023 18:56:43 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="377386849" X-IronPort-AV: E=Sophos;i="6.04,223,1695711600"; d="scan'208";a="377386849" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2023 18:56:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="802087268" X-IronPort-AV: E=Sophos;i="6.04,223,1695711600"; d="scan'208";a="802087268" X-Received: from shwdeopenlab813.ccr.corp.intel.com ([10.239.55.230]) by orsmga001.jf.intel.com with ESMTP; 23 Nov 2023 18:56:40 -0800 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: xieyuanh , Ray Ni , Eric Dong , Rahul Kumar , Tom Lendacky , Laszlo Ersek Subject: [edk2-devel] [Patch V4 1/3] UefiCpuPkg/MpInitLib: Eliminate redundant microcode loading in DXE. Date: Fri, 24 Nov 2023 10:56:33 +0800 Message-Id: <20231124025635.3629-2-yuanhao.xie@intel.com> In-Reply-To: <20231124025635.3629-1-yuanhao.xie@intel.com> References: <20231124025635.3629-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: zoVq0NBmKVFhpPY3n1nIdE5Rx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=j8vOnJBW; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io The DXE stage's Microcode loading process has been elimincated by: 1. Let ShadowMicrocodeUpdatePatch and MicrocodeDetect for BSP performed only during the PEI phase. DXE skip those actions. 2. BSP in DXE WakeUpAp only for synchronizing MTRR settings, not loading microcode. Synchronizing the MTRRs setting to the APs is always essential. The modification of the MTRRs on the BSP may happens during timing in the early DXE phase, while the CpuMp PPI service and the CpuMp Protocol both not available. Cc: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Tom Lendacky Cc: Laszlo Ersek Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Library/MpInitLib/Microcode.c | 46 ---------------------------------------------- UefiCpuPkg/Library/MpInitLib/MpLib.c | 39 ++++++++++++++++++++++++--------------- UefiCpuPkg/Library/MpInitLib/MpLib.h | 21 --------------------- 3 files changed, 24 insertions(+), 82 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c index 11720560af..8faa93024d 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -338,49 +338,3 @@ ShadowMicrocodeUpdatePatch ( ShadowMicrocodePatchByPcd (CpuMpData); } } - -/** - Get the cached microcode patch base address and size from the microcode patch - information cache HOB. - - @param[out] Address Base address of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - @param[out] RegionSize Size of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - - @retval TRUE The microcode patch information cache HOB is found. - @retval FALSE The microcode patch information cache HOB is not found. - -**/ -BOOLEAN -GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize - ) -{ - EFI_HOB_GUID_TYPE *GuidHob; - EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob; - - GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid); - if (GuidHob == NULL) { - DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __func__)); - return FALSE; - } - - MicrocodePathHob = GET_GUID_HOB_DATA (GuidHob); - - *Address = MicrocodePathHob->MicrocodePatchAddress; - *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize; - - DEBUG (( - DEBUG_INFO, - "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", - __func__, - *Address, - *RegionSize - )); - - return TRUE; -} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 9a6ec5db5c..1fd6440a53 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -451,12 +451,20 @@ ApInitializeSync ( CpuMpData = (CPU_MP_DATA *)Buffer; Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); ASSERT_EFI_ERROR (Status); + ASSERT (CpuMpData->InitFlag == ApInitReconfig || CpuMpData->InitFlag == ApInitDone); + if (CpuMpData->InitFlag != ApInitReconfig) { + // + // Load microcode on AP for PEI phase. + // During the DXE phase, it cannot omitted. + // + MicrocodeDetect (CpuMpData, ProcessorNumber); + } + // - // Load microcode on AP - // - MicrocodeDetect (CpuMpData, ProcessorNumber); - // - // Sync BSP's MTRR table to AP + // Synchronizing the MTRRs setting to the APs is always essential. + // The modification of the MTRRs on the BSP may happens during + // timing in the early DXE phase, while the CpuMp PPI service and + // the CpuMp Protocol are both not available. // MtrrSetAllMtrrs (&CpuMpData->MtrrTable); } @@ -2224,29 +2232,25 @@ MpInitLibInitialize ( } } - if (!GetMicrocodePatchInfoFromHob ( - &CpuMpData->MicrocodePatchAddress, - &CpuMpData->MicrocodePatchRegionSize - )) - { + if (MpHandOff == NULL) { // // The microcode patch information cache HOB does not exist, which means // the microcode patches data has not been loaded into memory yet // ShadowMicrocodeUpdatePatch (CpuMpData); + // + // Detect and apply Microcode on BSP + // + MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); } - // - // Detect and apply Microcode on BSP - // - MicrocodeDetect (CpuMpData, CpuMpData->BspNumber); // // Store BSP's MTRR setting // MtrrGetAllMtrrs (&CpuMpData->MtrrTable); // - // Wakeup APs to do some AP initialize sync (Microcode & MTRR) + // Wakeup APs to do some AP initialize sync (MTRR and/or Microcode). // if (CpuMpData->CpuCount > 1) { if (MpHandOff != NULL) { @@ -2258,6 +2262,11 @@ MpInitLibInitialize ( CpuMpData->InitFlag = ApInitReconfig; } + // + // Wake up APs to perform AP initialization synchronization. + // 1. For the PEI stage, load microcode and synchronize MTRRs, + // 2. For the DXE phase, only synchronize MTRRs. + // WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); // // Wait for all APs finished initialization diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 763db4963d..01b5b9c113 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -744,27 +744,6 @@ ShadowMicrocodeUpdatePatch ( IN OUT CPU_MP_DATA *CpuMpData ); -/** - Get the cached microcode patch base address and size from the microcode patch - information cache HOB. - - @param[out] Address Base address of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - @param[out] RegionSize Size of the microcode patches data. - It will be updated if the microcode patch - information cache HOB is found. - - @retval TRUE The microcode patch information cache HOB is found. - @retval FALSE The microcode patch information cache HOB is not found. - -**/ -BOOLEAN -GetMicrocodePatchInfoFromHob ( - UINT64 *Address, - UINT64 *RegionSize - ); - /** Detect whether Mwait-monitor feature is supported. -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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