From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3CDEC7803D0 for ; Wed, 29 Nov 2023 20:33:44 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=lvlsun/HMTng/F2OWQ/lpOHPGKIx7Js6UVUVg4vke58=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1701290022; v=1; b=mH+9sBqgR9+tuOeEElO4TOlm1s/mFW+m57L7aqq8aFFoAfba0aPJMM0+HrE9WzGDE6lwscSl Uid9UtSBm2vL8vvIWmjQjzwFXYylq0GYXAGu0g9Z7bBiCNTwlyqm3IloUlRK0pa3CkX7Oz4qizw 21P26JJzl89Gf3xN6ilV5k04= X-Received: by 127.0.0.2 with SMTP id MwUxYY7687511xxh39O2qAOw; Wed, 29 Nov 2023 12:33:42 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.26036.1701241072761157060 for ; Tue, 28 Nov 2023 22:57:52 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="395928544" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="395928544" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 22:57:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10908"; a="886733245" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="886733245" X-Received: from shwdeopenlab108.ccr.corp.intel.com ([10.239.55.64]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 22:57:48 -0800 From: Foster Nong To: devel@edk2.groups.io Cc: Foster Nong , Michael D Kinney , Liming Gao , Ray Ni , Chris Li Subject: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h into IndustryStandard Date: Wed, 29 Nov 2023 14:57:29 +0800 Message-Id: <20231129065729.8259-1-foster.nong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,foster.nong@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: vVZkdqrIt8yhYo6151yes6D4x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=mH+9sBqg; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4516 1) Add CXL 3.0 header file to comply with CXL 3.0 specification 2) CXL 3.0 header will embed Cxl20.h 3) Updated Cxl.h to point to 3.0 header file Signed-off-by: Foster Nong Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Chris Li --- MdePkg/Include/IndustryStandard/Cxl.h | 2 +- MdePkg/Include/IndustryStandard/Cxl30.h | 315 ++++++++++++++++++++ 2 files changed, 316 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/Industr= yStandard/Cxl.h index 9ad3242e25..cb623a355d 100755 --- a/MdePkg/Include/IndustryStandard/Cxl.h +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _CXL_MAIN_H_=0D #define _CXL_MAIN_H_=0D =0D -#include =0D +#include =0D //=0D // CXL assigned new Vendor ID=0D //=0D diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/Indus= tryStandard/Cxl30.h new file mode 100644 index 0000000000..feb6b9c52f --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -0,0 +1,315 @@ +/** @file=0D + CXL 3.0 Register definitions=0D +=0D + This file contains the register definitions based on the Compute Express= Link=0D + (CXL) Specification Revision 3.0.=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef CXL30_H_=0D +#define CXL30_H_=0D +=0D +#include =0D +=0D +//=0D +// CXL Cache Memory Capability IDs=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4 Table 8= -22=0D +//=0D +#define CXL_CACHE_MEM_CAPABILITY_ID_TIMEOUT_AND_ISOLATION 0x0009= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED 0x000A= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_BI_ROUTE_TABLE 0x000B= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_BI_DECODER 0x000C= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_ROUTE_TABLE 0x000D= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_DECODER 0x000E= =0D +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_HDM_DECODER 0x000F= =0D +=0D +//=0D +// CXL_Capability_Version=0D +// Compute Express ink Specification Revision 3.0 - Chapter 8.2.4.5=0D +//=0D +#define CXL_HDM_DECODER_VERSION_30 0x3=0D +=0D +//=0D +// CXL CXL HDM Decoder n Control=0D +// Compute Express Link Specification Revision 3.0 - 8.2.4.19.7=0D +//=0D +//=0D +// Bit4..7: Interleave Ways (IW)=0D +//=0D +#define CXL_HDM_16_WAY_INTERLEAVING 0x4=0D +#define CXL_HDM_3_WAY_INTERLEAVING 0x8=0D +#define CXL_HDM_6_WAY_INTERLEAVING 0x9=0D +#define CXL_HDM_12_WAY_INTERLEAVING 0xA=0D +=0D +//=0D +// Ensure proper structure formats=0D +//=0D +#pragma pack(1)=0D +=0D +//=0D +// CXL.cachemem Extended Register Capability=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.24=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 ExtendedRangesBitmap : 16; // Bit 0..15=0D + UINT32 Reserved : 16; // Bit 16..31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CM_EXTENTED_REGISTER_CAPABILITY;=0D +=0D +#define CXL_CM_EXTENTED_RANGES_BITMAP (BIT2 | BIT3 | BIT4 | BIT5 | BIT6= | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT15)=0D +=0D +//=0D +// CXL BI Route Table Capability=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.25=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 ExplicitBiRtCommitRequired :1; // bit 0=0D + UINT32 Reserved :31; // bit 1..3= 1=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_RT_CAPABILITY;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 BiRtCommit :1; // bit 0=0D + UINT32 Reserved :31; // bit 1..= 31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_RT_CONTROL;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 BiRtCommitted :1; // bit 0=0D + UINT32 BiRtErrorNotCommitted :1; // bit 1=0D + UINT32 Reserved1 :6; // bit 2..7= =0D + UINT32 BiRtCommitTimeoutScale :4; // bit 8..1= 1=0D + UINT32 BiRtCommitTimeoutBase :4; // bit 12..= 15=0D + UINT32 Reserved2 :16; // bit 16..= 31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_RT_STATUS;=0D +=0D +typedef struct {=0D + CXL_BI_RT_CAPABILITY BiRtCap; /= / offset 0x00=0D + CXL_BI_RT_CONTROL BiRtControl; /= / offset 0x04=0D + CXL_BI_RT_STATUS BiRtStatus; /= / offset 0x08=0D +} CXL_BI_ROUTE_TABLE_CAPABILITY;=0D +=0D +//=0D +// CXL BI Decoder Capability=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.26=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 HdmDCapable :1; // bit 0=0D + UINT32 ExplicitBiDecoderCommitRequired :1; // bit 1=0D + UINT32 Reserved :30; // bit 2..3= 1=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_DECODER_CAP;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 BiForward :1; // bit 0=0D + UINT32 BiEnable :1; // bit 1=0D + UINT32 BiDecoderCommit :1; // bit 2=0D + UINT32 Reserved :29; // bit 3..3= 1=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_DECODER_CONTROL;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 BiDecoderCommitted :1; // bit 0=0D + UINT32 BiDecoderErrorNotCommitted :1; // bit 1=0D + UINT32 Reserved1 :6; // bit 2..7= =0D + UINT32 BiDecoderCommitTimeoutScale :4; // bit 8..1= 1=0D + UINT32 BiDecoderCommitTimeoutBase :4; // bit 12..= 15=0D + UINT32 Reserved2 :16; // bit 16..= 31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_BI_DECODER_STATUS;=0D +=0D +typedef struct {=0D + CXL_BI_DECODER_CAP BiDecoderCap; = // offset 0x00=0D + CXL_BI_DECODER_CONTROL BiDecoderControl; = // offset 0x04=0D + CXL_BI_DECODER_STATUS BiDecoderStatus; = // offset 0x08=0D +} CXL_BI_DECODER_CAPABILITY;=0D +=0D +//=0D +// CXL Cache ID Route Table Capability=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.27=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 CacheIdTargetCount : 5; // Bit 0..4= =0D + UINT32 Reserved1 : 3; // Bit 5..7= =0D + UINT32 HdmDType2DeviceMaxCount : 4; // Bit 8..11= =0D + UINT32 Reserved2 : 4; // Bit 12..1= 5=0D + UINT32 ExplicitCacheIdRtCommitRequired : 1; // Bit 16=0D + UINT32 Reserved3 : 15; // Bit 17:31= =0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_RT_CAPABILITY;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 CacheIdRtCommit : 1; // Bit 0=0D + UINT32 Reserved : 31; // Bit 1..31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_RT_CONTROL;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 CacheIdRtCommitted : 1; // Bit 0=0D + UINT32 CacheIdRtErrNotCommitted : 1; // Bit 1=0D + UINT32 Reserved1 : 6; // Bit 2..7=0D + UINT32 CacheIdRtCommitTimeoutScale : 4; // Bit 8..11=0D + UINT32 CacheIdRtCommitTimeoutBase : 4; // Bit 12..15=0D + UINT32 Reserved2 : 16; // Bit 16..31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_RT_STATUS;=0D +=0D +typedef union {=0D + struct {=0D + UINT16 Valid : 1; // Bit 0=0D + UINT16 Reserved : 7; // Bit 1..7=0D + UINT16 PortNumber : 8; // Bit 8..15=0D + } Bits;=0D + UINT16 Uint16;=0D +} CXL_CACHE_ID_RT_TARGET;=0D +=0D +typedef struct {=0D + CXL_CACHE_ID_RT_CAPABILITY CacheIdRtCap; // offset 0x00= =0D + CXL_CACHE_ID_RT_CONTROL CacheIdRtControl; // offset 0x04= =0D + CXL_CACHE_ID_RT_STATUS CacheIdRtStatus; // offset 0x08= =0D + UINT32 Reserved; // offset 0x0C= =0D + CXL_CACHE_ID_RT_TARGET CacheIdRtTarget[]; // offset 0x10= =0D +} CXL_CACHE_ID_ROUTE_TABLE_CAPABILITY;=0D +=0D +//=0D +// CXL Cache ID Decoder Capability=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.28=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 ExplicitCacheIdDecoderCommitRequired : 1; // Bit = 0=0D + UINT32 Reserved : 31; // Bit = 1..31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_DECODER_CAP;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 ForwardCacheId : 1; // Bit 0=0D + UINT32 AssignCacheId : 1; // Bit 1=0D + UINT32 HdmDType2DevicePresent : 1; // Bit 2=0D + UINT32 CacheIdDecoderCommit : 1; // Bit 3=0D + UINT32 Reserved1 : 4; // Bit 4..7=0D + UINT32 HdmDType2DeviceCacheId : 4; // Bit 8..11=0D + UINT32 Reserved2 : 4; // Bit 12..15=0D + UINT32 LocalCacheId : 4; // Bit 16..19=0D + UINT32 Reserved3 : 4; // Bit 20..23=0D + UINT32 TrustLevel : 2; // Bit 24..25=0D + UINT32 Reserved4 : 6; // Bit 26..31=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_DECODER_CONTROL;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 CacheIdDecoderCommitted : 1; // Bit 0=0D + UINT32 CacheIdDecoderErrorNotCommitted : 1; // Bit 1=0D + UINT32 Reserved1 : 6; // Bit 2..7= =0D + UINT32 CacheIdDecoderCommitTimeoutScale : 4; // Bit 8..11= =0D + UINT32 CacheIdDecoderCommitTimeoutBase : 4; // Bit 12..1= 5=0D + UINT32 Reserved2 : 16; // Bit 16..3= 1=0D + } Bits;=0D + UINT32 Uint32;=0D +} CXL_CACHE_ID_DECODER_STATUS;=0D +=0D +typedef struct {=0D + CXL_CACHE_ID_DECODER_CAP CacheIdDecoderCap; // offset 0= x00=0D + CXL_CACHE_ID_DECODER_CONTROL CacheIdDecoderControl; // offset 0= x04=0D + CXL_CACHE_ID_DECODER_STATUS CacheIdDecoderStatus; // offset 0= x08=0D +} CXL_CACHE_ID_DECODER_CAPABILITY;=0D +=0D +//=0D +// CXL Timeout and Isolation Capability Structure=0D +// Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.23=0D +//=0D +typedef union {=0D + struct {=0D + UINT32 CxlmemTransactionTimeoutRangesSupported : 4; // Bits 3:0=0D + UINT32 CxlmemTransactionTimeoutSupported : 1; // Bits 4=0D + UINT32 Reserved1 : 3; // Bits 7:5=0D + UINT32 CxlcacheTransactionTimeoutRangesSupported : 4; // Bits 11:8=0D + UINT32 CxlcacheTransactionTimeoutSupported : 1; // Bits 12=0D + UINT32 Reserved2 : 3; // Bits 15:13=0D + UINT32 CxlmemIsolationSupported : 1; // Bits 16=0D + UINT32 CxlmemIsolationLinkdownSupported : 1; // Bits 17=0D + UINT32 CxlcacheIsolationSupported : 1; // Bits 18=0D + UINT32 CxlcacheIsolationLinkdownSupported : 1; // Bits 19=0D + UINT32 Reserved3 : 5; // Bits 24:20=0D + UINT32 IsolationErrCorSignalingSupported : 1; // Bits 25=0D + UINT32 IsolationInterruptSupported : 1; // Bits 26=0D + UINT32 IsolationInterruptMessageNumber : 5; // Bits 31:27=0D + } Bits;=0D + UINT32 Data32;=0D +} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 CxlmemTransactionTimeoutValue : 4; // Bits 3:0=0D + UINT32 CxlmemTransactionTimeoutEnable : 1; // Bits 4=0D + UINT32 Reserved1 : 3; // Bits 7:5=0D + UINT32 CxlcacheTransactionTimeoutValue : 4; // Bits 11:8=0D + UINT32 CxlcacheTransactionTimeoutEnable : 1; // Bits 12=0D + UINT32 Reserved2 : 3; // Bits 15:13=0D + UINT32 CxlmemIsolationEnable : 1; // Bits 16=0D + UINT32 CxlmemIsolationLinkdownEnable : 1; // Bits 17=0D + UINT32 CxlcacheIsolationEnable : 1; // Bits 18=0D + UINT32 CxlcacheIsolationLinkdownEnable : 1; // Bits 19=0D + UINT32 Reserved3 : 5; // Bits 24:20=0D + UINT32 IsolationErrCorSignalingEnable : 1; // Bits 25=0D + UINT32 IsolationInterruptEnable : 1; // Bits 26=0D + UINT32 Reserved4 : 5; // Bits 31:27=0D + } Bits;=0D + UINT32 Data32;=0D +} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 CxlmemTransactionTimeout : 1; // Bits 0=0D + UINT32 Reserved1 : 3; // Bits 3:1=0D + UINT32 CxlcacheTransactionTimeout : 1; // Bits 4=0D + UINT32 Reserved2 : 3; // Bits 7:5=0D + UINT32 CxlmemIsolationStatus : 1; // Bits 8=0D + UINT32 CxlmemIsolationLinkdownStatus : 1; // Bits 9=0D + UINT32 Reserved3 : 2; // Bits 11:10=0D + UINT32 CxlcacheIsolationStatus : 1; // Bits 12=0D + UINT32 CxlcacheIsolationLinkdownStatus : 1; // Bits 13=0D + UINT32 CxlRpBusy : 1; // Bits 14=0D + UINT32 Reserved4 : 17; // Bits 31:15=0D + } Bits;=0D + UINT32 Data32;=0D +} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS;=0D +=0D +typedef struct {=0D + CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY TimeoutAndIsolationCap;= =0D + UINT32 Reserved;=0D + CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL TimeoutAndIsolationContr= ol;=0D + CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatu= s;=0D +} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;=0D +=0D +#pragma pack()=0D +=0D +#endif=0D --=20 2.37.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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