From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 5641EAC1169 for ; Mon, 4 Dec 2023 08:30:02 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=8Cj1sKeZjZkhQMskIGLHHxsmQrQ2mO1qB+RddYD9OBQ=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1701678601; v=1; b=hRCxJwXgCJyVDsSwdPv+ljshSWtxG/mIJVKdqujNGDQ054BdBzgVX2QPLDRaID83s16p/uJi CmdFXPvuEMnbfl7gKeSO+D8EMA3irCh3vuvxW/eNf/RHWyeg8LZFttTNtttVTWgZoITYNOVfsyx ZqTTnlIcZw7oaiZievuHc9+M= X-Received: by 127.0.0.2 with SMTP id MgkJYY7687511x6TYjInQ3Ra; Mon, 04 Dec 2023 00:30:01 -0800 X-Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web11.64431.1701678600568534746 for ; Mon, 04 Dec 2023 00:30:00 -0800 X-Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-285d1101868so2617095a91.0 for ; Mon, 04 Dec 2023 00:30:00 -0800 (PST) X-Gm-Message-State: TBu9vziYLiBA6DzGzkb6sveAx7686176AA= X-Google-Smtp-Source: AGHT+IGfVW10N/qWPJQqsAuOsNdL6qfnE3iwE2W04IkhN6G1BhUE1XrwR76hmqdpfbhB/f7Y/20wSA== X-Received: by 2002:a17:90b:c15:b0:286:6cc1:28b with SMTP id bp21-20020a17090b0c1500b002866cc1028bmr960149pjb.86.1701678599617; Mon, 04 Dec 2023 00:29:59 -0800 (PST) X-Received: from dhaval.blr.rivosinc.com ([49.249.129.34]) by smtp.gmail.com with ESMTPSA id h21-20020a170902f7d500b001d058ad8770sm5754211plw.306.2023.12.04.00.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 00:29:59 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: [edk2-devel] [PATCH v9 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Date: Mon, 4 Dec 2023 13:59:46 +0530 Message-Id: <20231204082950.96914-2-dhaval@rivosinc.com> In-Reply-To: <20231204082950.96914-1-dhaval@rivosinc.com> References: <20231204082950.96914-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=hRCxJwXg; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io The declarations for cache Management functions belong to BaseLib instead of instance source file. This helps with further restructuring of cache management code for RISC-V. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek --- Notes: V7: - Added RB tag V6: - Move cache management function declaration in baselib where it belongs MdePkg/Include/Library/BaseLib.h | 20 +++++++++++++++++= +++ MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 -----------------= --- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 5d7067ee854e..7142bbfa42f2 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt ( VOID=0D );=0D =0D +/**=0D + RISC-V invalidate instruction cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateInstCacheAsm (=0D + VOID=0D + );=0D +=0D +/**=0D + RISC-V invalidate data cache.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVInvalidateDataCacheAsm (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D #if defined (MDE_CPU_LOONGARCH64)=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193ca..d5efcf49a4bf 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -10,26 +10,6 @@ #include =0D #include =0D =0D -/**=0D - RISC-V invalidate instruction cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateInstCacheAsm (=0D - VOID=0D - );=0D -=0D -/**=0D - RISC-V invalidate data cache.=0D -=0D -**/=0D -VOID=0D -EFIAPI=0D -RiscVInvalidateDataCacheAsm (=0D - VOID=0D - );=0D -=0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D calling CPU.=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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