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From: "Dhaval Sharma" <dhaval@rivosinc.com>
To: devel@edk2.groups.io
Cc: Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Daniel Schaefer <git@danielschaefer.me>,
Laszlo Ersek <lersek@redhat.com>
Subject: [edk2-devel] [PATCH v9 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op
Date: Mon, 4 Dec 2023 13:59:47 +0530
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There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
Notes:
V8:
- Update function name to udpate *asm* in the end
V7:
- Add RB tag
V6:
- As part of restructuring, adding cache instruction differentiation
in function naming
MdePkg/Include/Library/BaseLib.h | 4 ++--
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 ++++----
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base=
Lib.h
index 7142bbfa42f2..d80e27285424 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
**/=0D
VOID=0D
EFIAPI=0D
-RiscVInvalidateInstCacheAsm (=0D
+RiscVInvalidateInstCacheFenceAsm (=0D
VOID=0D
);=0D
=0D
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
**/=0D
VOID=0D
EFIAPI=0D
-RiscVInvalidateDataCacheAsm (=0D
+RiscVInvalidateDataCacheFenceAsm (=0D
VOID=0D
);=0D
=0D
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L=
ibrary/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..ac2a3c23a249 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
VOID=0D
)=0D
{=0D
- RiscVInvalidateInstCacheAsm ();=0D
+ RiscVInvalidateInstCacheFenceAsm ();=0D
}=0D
=0D
/**=0D
@@ -193,7 +193,7 @@ InvalidateDataCache (
VOID=0D
)=0D
{=0D
- RiscVInvalidateDataCacheAsm ();=0D
+ RiscVInvalidateDataCacheFenceAsm ();=0D
}=0D
=0D
/**=0D
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B=
aseLib/RiscV64/FlushCache.S
index 7c10fdd268af..8cfb85097996 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
//------------------------------------------------------------------------=
------=0D
=0D
.align 3=0D
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)=0D
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)=0D
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)=0D
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)=0D
=0D
-ASM_PFX(RiscVInvalidateInstCacheAsm):=0D
+ASM_PFX(RiscVInvalidateInstCacheFenceAsm):=0D
fence.i=0D
ret=0D
=0D
-ASM_PFX(RiscVInvalidateDataCacheAsm):=0D
+ASM_PFX(RiscVInvalidateDataCacheFenceAsm):=0D
fence=0D
ret=0D
--=20
2.39.2
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