From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 9A6219414F4 for ; Wed, 6 Dec 2023 08:16:30 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=KL0CvNpxUaudZ+DjpLLY7LCiWFNjLemOmN3KEduynsk=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1701850589; v=1; b=XwuX1XgFCQCwc90pFF+/0x5pKHOjw6L2VVmeLpy6qBcGE68/Q+J3+KE4PII2E6gX6bqOCAb6 gVVSjwRDRk7dCZBEFQoo/F821a7g6LxArVO3Umq108qgr0IZUaK7sXoMSHmDUg9aZvJSPxDldVo 4Fc1+eicgOBS7o3uYbaaQPaI= X-Received: by 127.0.0.2 with SMTP id dOkMYY7687511xH51MaV08lV; Wed, 06 Dec 2023 00:16:29 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.26660.1701850587670127710 for ; Wed, 06 Dec 2023 00:16:28 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="1118489" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="1118489" X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2023 00:16:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="837240753" X-IronPort-AV: E=Sophos;i="6.04,254,1695711600"; d="scan'208";a="837240753" X-Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.28]) by fmsmga008.fm.intel.com with ESMTP; 06 Dec 2023 00:16:26 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Wu Jiaxin , Tan Dun Subject: [edk2-devel] [PATCH v7 1/5] UefiCpuPkg: Add macro definitions for CET feature for NASM files. Date: Wed, 6 Dec 2023 16:16:20 +0800 Message-Id: <20231206081624.1370-2-w.sheng@intel.com> In-Reply-To: <20231206081624.1370-1-w.sheng@intel.com> References: <20231206081624.1370-1-w.sheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,w.sheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Uj7k9CcA05OOXhFmVtVfEsCjx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=XwuX1XgF; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Wu Jiaxin Cc: Tan Dun --- UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/= Cet.inc new file mode 100644 index 0000000000..41c99988c9 --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Cet.inc @@ -0,0 +1,26 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +; Abstract:=0D +;=0D +; This file provides macro definitions for CET feature for NASM files.=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +%define MSR_IA32_U_CET 0x6A0=0D +%define MSR_IA32_S_CET 0x6A2=0D +%define MSR_IA32_CET_SH_STK_EN (1<<0)=0D +%define MSR_IA32_CET_WR_SHSTK_EN (1<<1)=0D +%define MSR_IA32_CET_ENDBR_EN (1<<2)=0D +%define MSR_IA32_CET_LEG_IW_EN (1<<3)=0D +%define MSR_IA32_CET_NO_TRACK_EN (1<<4)=0D +%define MSR_IA32_CET_SUPPRESS_DIS (1<<5)=0D +%define MSR_IA32_CET_SUPPRESS (1<<10)=0D +%define MSR_IA32_CET_TRACKER (1<<11)=0D +%define MSR_IA32_PL0_SSP 0x6A4=0D +%define MSR_IA32_INTERRUPT_SSP_TABLE_ADDR 0x6A8=0D +=0D +%define CR4_CET_BIT 23=0D +%define CR4_CET (1<