From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id E3436AC10B6 for ; Tue, 12 Dec 2023 13:13:02 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=HY/IyK20JzRDbkU+Dv+KaPhkcLhFKEJVICxZt6yvPBE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1702386781; v=1; b=h9bdNws3bl+ojZysaC1tOwyDnq7aLdxIxvpAjPBukWxHBqIV0n2OQhbBn5p3pOdlXktFUJOP /GiIkwVWmtORvHeMPYSTofpjPNk1VefS/Djsj8AdEv2evuHMAWk33VVfZ1fWR3KMEaOiS5uNuLY ADhhN/O/Y661cY/OA169cL8I= X-Received: by 127.0.0.2 with SMTP id 4oY9YY7687511xaud7EPFkm7; Tue, 12 Dec 2023 05:13:01 -0800 X-Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web11.1231.1702386780457448712 for ; Tue, 12 Dec 2023 05:13:01 -0800 X-Received: from loongson.cn (unknown [10.2.9.245]) by gateway (Coremail) with SMTP id _____8DxS+lYXHhlw1kAAA--.2172S3; Tue, 12 Dec 2023 21:12:56 +0800 (CST) X-Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx3+FXXHhlL6QAAA--.4711S2; Tue, 12 Dec 2023 21:12:56 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Ray Ni , Rahul Kumar , Gerd Hoffmann , Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v4 19/37] UefiCpuPkg: Add MMIO method in CpuIo2Dxe Date: Tue, 12 Dec 2023 21:12:54 +0800 Message-Id: <20231212131254.2471233-1-lichao@loongson.cn> In-Reply-To: <20231212130932.2467028-1-lichao@loongson.cn> References: <20231212130932.2467028-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cx3+FXXHhlL6QAAA--.4711S2 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQADCGV3wy0H6gAesF X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lichao@loongson.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: iIaJ0z0vFmtRzftk2tsCuzvax7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=h9bdNws3; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io CpuIo2Dxe only supports IO to access PCI IO. Some ARCH requires MMIO to access PCI IO, add the MMIO access method in CpuIo2Dxe. The MMIO methods depend on PcdPciIoTranslationIsEnabled and PcdPciIoTransLation. The code is referenced from ArmPkg. Build-tested only (with "OvmfPkgX64.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Sami Mujawar Signed-off-by: Chao Li --- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c | 149 +++++++++++++++++++---------- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h | 2 + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf | 8 +- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni | 2 + 4 files changed, 111 insertions(+), 50 deletions(-) diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c index 87f4f805ca..cd31977af2 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c @@ -3,6 +3,8 @@ Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -149,7 +151,7 @@ CpuIoCheckParameter ( // // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count // can also be the maximum integer value supported by the CPU, this range - // check must be adjusted to avoid all oveflow conditions. + // check must be adjusted to avoid all overflow conditions. // // The following form of the range check is equivalent but assumes that // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). @@ -398,6 +400,18 @@ CpuIoServiceRead ( EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; UINT8 *Uint8Buffer; + UINT8 EFIAPI (*CpuIoRead8) ( + UINTN + ); + + UINT16 EFIAPI (*CpuIoRead16) ( + UINTN + ); + + UINT32 EFIAPI (*CpuIoRead32) ( + UINTN + ); + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); if (EFI_ERROR (Status)) { return Status; @@ -410,37 +424,48 @@ CpuIoServiceRead ( OutStride = mOutStride[Width]; OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - // - // Fifo operations supported for (mInStride[Width] == 0) - // - if (InStride == 0) { - switch (OperationWidth) { - case EfiCpuIoWidthUint8: - IoReadFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint16: - IoReadFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint32: - IoReadFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + if (FeaturePcdGet (PcdPciIoTranslationIsEnabled) == FALSE) { + // + // Fifo operations supported for (mInStride[Width] == 0) + // + if (InStride == 0) { + switch (OperationWidth) { + case EfiCpuIoWidthUint8: + IoReadFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint16: + IoReadFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint32: + IoReadFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } } + + CpuIoRead8 = IoRead8; + CpuIoRead16 = IoRead16; + CpuIoRead32 = IoRead32; + } else { + Address += PcdGet64 (PcdPciIoTranslation); + CpuIoRead8 = MmioRead8; + CpuIoRead16 = MmioRead16; + CpuIoRead32 = MmioRead32; } for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiCpuIoWidthUint8) { - *Uint8Buffer = IoRead8 ((UINTN)Address); + *Uint8Buffer = CpuIoRead8 ((UINTN)Address); } else if (OperationWidth == EfiCpuIoWidthUint16) { - *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address); + *((UINT16 *)Uint8Buffer) = CpuIoRead16 ((UINTN)Address); } else if (OperationWidth == EfiCpuIoWidthUint32) { - *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address); + *((UINT32 *)Uint8Buffer) = CpuIoRead32 ((UINTN)Address); } } @@ -502,6 +527,21 @@ CpuIoServiceWrite ( EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; UINT8 *Uint8Buffer; + UINT8 EFIAPI (*CpuIoWrite8) ( + UINTN, + UINT8 + ); + + UINT16 EFIAPI (*CpuIoWrite16) ( + UINTN, + UINT16 + ); + + UINT32 EFIAPI (*CpuIoWrite32) ( + UINTN, + UINT32 + ); + // // Make sure the parameters are valid // @@ -517,37 +557,48 @@ CpuIoServiceWrite ( OutStride = mOutStride[Width]; OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); - // - // Fifo operations supported for (mInStride[Width] == 0) - // - if (InStride == 0) { - switch (OperationWidth) { - case EfiCpuIoWidthUint8: - IoWriteFifo8 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint16: - IoWriteFifo16 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - case EfiCpuIoWidthUint32: - IoWriteFifo32 ((UINTN)Address, Count, Buffer); - return EFI_SUCCESS; - default: - // - // The CpuIoCheckParameter call above will ensure that this - // path is not taken. - // - ASSERT (FALSE); - break; + if (FeaturePcdGet (PcdPciIoTranslationIsEnabled) == FALSE) { + // + // Fifo operations supported for (mInStride[Width] == 0) + // + if (InStride == 0) { + switch (OperationWidth) { + case EfiCpuIoWidthUint8: + IoWriteFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint16: + IoWriteFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiCpuIoWidthUint32: + IoWriteFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } } + + CpuIoWrite8 = IoWrite8; + CpuIoWrite16 = IoWrite16; + CpuIoWrite32 = IoWrite32; + } else { + Address += PcdGet64 (PcdPciIoTranslation); + CpuIoWrite8 = MmioWrite8; + CpuIoWrite16 = MmioWrite16; + CpuIoWrite32 = MmioWrite32; } for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { if (OperationWidth == EfiCpuIoWidthUint8) { - IoWrite8 ((UINTN)Address, *Uint8Buffer); + CpuIoWrite8 ((UINTN)Address, *Uint8Buffer); } else if (OperationWidth == EfiCpuIoWidthUint16) { - IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + CpuIoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); } else if (OperationWidth == EfiCpuIoWidthUint32) { - IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + CpuIoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); } } diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h index 7ebde0759b..5256a583e1 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h @@ -2,6 +2,8 @@ Internal include file for the CPU I/O 2 Protocol. Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2016, Linaro Ltd. All rights reserved.
+Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf index 499258491f..271c47371b 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf @@ -3,6 +3,8 @@ # # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.
+# Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,7 +22,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 X64 EBC +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 LOONGARCH64 # [Sources] @@ -37,6 +39,10 @@ IoLib UefiBootServicesTableLib +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslationIsEnabled + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation + [Protocols] gEfiCpuIo2ProtocolGuid ## PRODUCES diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni index 8d4e5dd6b4..14a36ff888 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni @@ -4,6 +4,8 @@ // Produces the CPU I/O 2 Protocol by using the services of the I/O Library. // // Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+// Copyright (c) 2016, Linaro Ltd. All rights reserved.
+// Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // -- 2.27.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112410): https://edk2.groups.io/g/devel/message/112410 Mute This Topic: https://groups.io/mt/103129115/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-