From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id AD38CAC1215 for ; Wed, 13 Dec 2023 15:00:53 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=8MrgiaUJAqcwZLP5A/1rkZUO0AMKGqgG9UYwA0CCt9s=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1702479652; v=1; b=nwgW0cLAmgee8qz1ETJ1uNU7Ke7MB1ey6voHsdOTA7fbp1ZMaONBaz5CGHJrsYL7Z9vT6GNv 5flva14Z+99Vdbmc5Q6OfEb7qyxBr3jW+nl89TliJxSpWCrwTeccEiEu2Pvpj9Z2T5OlmtAsZIS eJPUo+OdjIsuZ5dumJLhx034= X-Received: by 127.0.0.2 with SMTP id CnykYY7687511xhFslZufIBS; Wed, 13 Dec 2023 07:00:52 -0800 X-Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mx.groups.io with SMTP id smtpd.web11.37831.1702479651876310875 for ; Wed, 13 Dec 2023 07:00:51 -0800 X-Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-6ceba6c4b8dso5751632b3a.1 for ; Wed, 13 Dec 2023 07:00:51 -0800 (PST) X-Gm-Message-State: dP1EpiI0IPhogbpwxQVp6ZUSx7686176AA= X-Google-Smtp-Source: AGHT+IFHL9M5fTE53ktz8nsmx21byJJe88uARgE29wu2CYMpulVdFszWx2BoQx/yfbUm3L+kx9w1xg== X-Received: by 2002:a05:6a00:990:b0:6cd:d53c:f5ea with SMTP id u16-20020a056a00099000b006cdd53cf5eamr9967646pfg.6.1702479650852; Wed, 13 Dec 2023 07:00:50 -0800 (PST) X-Received: from dhaval.. ([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.07.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 07:00:50 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek , Pedro Falcato , jingyulee98@gmail.com Subject: [edk2-devel] [PATCH v10 3/5] MdePkg: Implement RISC-V Cache Management Operations Date: Wed, 13 Dec 2023 20:29:29 +0530 Message-Id: <20231213145931.28307-4-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=nwgW0cLA; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Sunil V L Cc: Daniel Schaefer Cc: Laszlo Ersek Cc: Pedro Falcato Signed-off-by: Dhaval Sharma Reviewed-by: Laszlo Ersek Reviewed-by: Sunil V L Reviewed-by: Jingyu Li --- Notes: v8: - Add *asm* postfix to cmo functions - Add reviewed by tags V7: - Modify instruction names as per feedback from V6 - Added RB V6: - Implement Cache management instructions in Baselib MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Library/BaseLib.h | 33 +++= +++++++++++++++++ MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++= ++++++++ MdePkg/Library/BaseLib/RiscV64/{FlushCache.S =3D> RiscVCacheMgmt.S} | 17 += +++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 03c7b02e828b..53389389448c 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuBreakpoint.S | GCC=0D RiscV64/RiscVCpuPause.S | GCC=0D RiscV64/RiscVInterrupt.S | GCC=0D - RiscV64/FlushCache.S | GCC=0D + RiscV64/RiscVCacheMgmt.S | GCC=0D RiscV64/CpuScratch.S | GCC=0D RiscV64/ReadTimer.S | GCC=0D RiscV64/RiscVMmu.S | GCC=0D diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index c5e7f6dff0bc..b71e47f41b7f 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm ( VOID=0D );=0D =0D +/**=0D + RISC-V flush cache block. Atomically perform a clean operation=0D + followed by an invalidate operation=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheFlushCmoAsm (=0D + IN UINTN=0D + );=0D +=0D +/**=0D +Perform a write transfer to another cache or to memory if the=0D +data in the copy of the cache block have been modified by a store=0D +operation=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheCleanCmoAsm (=0D + IN UINTN=0D + );=0D +=0D +/**=0D +Deallocate the copy of the cache block=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +RiscVCpuCacheInvalCmoAsm (=0D + IN UINTN=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D #if defined (MDE_CPU_LOONGARCH64)=0D diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/R= iscVasm.inc new file mode 100644 index 000000000000..29de7358855c --- /dev/null +++ b/MdePkg/Include/RiscV64/RiscVasm.inc @@ -0,0 +1,19 @@ +/*=0D + *=0D + * RISC-V cache operation encoding.=0D + * Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D + * SPDX-License-Identifier: BSD-2-Clause-Patent=0D + *=0D + */=0D +=0D +.macro RISCVCMOFLUSH=0D + .word 0x25200f=0D +.endm=0D +=0D +.macro RISCVCMOINVALIDATE=0D + .word 0x05200f=0D +.endm=0D +=0D +.macro RISCVCMOCLEAN=0D + .word 0x15200f=0D +.endm=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/B= aseLib/RiscV64/RiscVCacheMgmt.S similarity index 56% rename from MdePkg/Library/BaseLib/RiscV64/FlushCache.S rename to MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S index 8cfb85097996..4752aa72d95e 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -3,10 +3,12 @@ // RISC-V cache operation.=0D //=0D // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D //------------------------------------------------------------------------= ------=0D +.include "RiscVasm.inc"=0D =0D .align 3=0D ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)=0D @@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm): ASM_PFX(RiscVInvalidateDataCacheFenceAsm):=0D fence=0D ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm)=0D +ASM_PFX (RiscVCpuCacheFlushCmoAsm):=0D + RISCVCMOFLUSH=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm)=0D +ASM_PFX (RiscVCpuCacheCleanCmoAsm):=0D + RISCVCMOCLEAN=0D + ret=0D +=0D +ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm)=0D +ASM_PFX (RiscVCpuCacheInvalCmoAsm):=0D + RISCVCMOINVALIDATE=0D + ret=0D --=20 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112481): https://edk2.groups.io/g/devel/message/112481 Mute This Topic: https://groups.io/mt/103150433/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-