From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 819297803E0 for ; Wed, 13 Dec 2023 15:00:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=4CozGfhjd6JYysX6wnpXoW74dFdjrdp6QfL8ob5LZAQ=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1702479656; v=1; b=umkP4LVoIFKfPbWqjedzb//vu5CCS+Ko5EaH7tzgjEbROfXkffVqfLnbECvaNdt3xjOAhINA ReseP0p45QdIbSwSgrR4Yqa7V8D6O7ZWwlWQ9LXLMQluTG3QZfiin+bH267DSyKSNGkojmbfHlb mFeTLUMMeHv7qeD5KYT7r+fE= X-Received: by 127.0.0.2 with SMTP id dWAVYY7687511xRYa7aMPNIM; Wed, 13 Dec 2023 07:00:56 -0800 X-Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by mx.groups.io with SMTP id smtpd.web10.38253.1702479655652049202 for ; Wed, 13 Dec 2023 07:00:55 -0800 X-Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-6ce72730548so6231988b3a.1 for ; Wed, 13 Dec 2023 07:00:55 -0800 (PST) X-Gm-Message-State: mt0vjMYF9TrSLo3cBjl0DYabx7686176AA= X-Google-Smtp-Source: AGHT+IE71d4QYcobScUGuf3hf/YS28Fl3W3lI+DOHtS4p2ERK7gJYb/yI/6G6PQTFx5dNZrIcElOHg== X-Received: by 2002:a05:6a00:98e:b0:6ce:10ed:7754 with SMTP id u14-20020a056a00098e00b006ce10ed7754mr9428675pfg.31.1702479653357; Wed, 13 Dec 2023 07:00:53 -0800 (PST) X-Received: from dhaval.. ([171.76.83.136]) by smtp.gmail.com with ESMTPSA id s16-20020a62e710000000b006ce3bf7acc7sm9985388pfh.113.2023.12.13.07.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 07:00:53 -0800 (PST) From: "Dhaval Sharma" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek , Pedro Falcato Subject: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Date: Wed, 13 Dec 2023 20:29:30 +0530 Message-Id: <20231213145931.28307-5-dhaval@rivosinc.com> In-Reply-To: <20231213145931.28307-1-dhaval@rivosinc.com> References: <20231213145931.28307-1-dhaval@rivosinc.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dhaval@rivosinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=umkP4LVo; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Use newly defined cache management operations for RISC-V where possible=0D It builds up on the support added for RISC-V cache management=0D instructions in BaseLib.=0D Cc: Michael D Kinney =0D Cc: Liming Gao =0D Cc: Zhiguang Liu =0D Cc: Laszlo Ersek =0D Cc: Pedro Falcato =0D =0D Signed-off-by: Dhaval Sharma =0D Acked-by: Laszlo Ersek =0D Reviewed-by: Pedro Falcato =0D ---=0D =0D Notes:=0D V10:=0D - Fix formatting to keep comments within 80=0D - Replace RV with RISC-V=0D - Fix an issue with multi line comments=0D - Added assert to an unsupported function=0D - Minor case modification in str in .uni=0D =0D V9:=0D - Fixed an issue with Instruction cache invalidation. Use fence.i=0D instruction as CMO does not support i-cache operations.=0D V8:=0D - Added note to convert PCD into RISC-V feature bitmap pointer=0D - Modified function names to be more explicit about cache ops=0D - Added RB tag=0D V7:=0D - Added PcdLib=0D - Restructure DEBUG message based on feedback on V6=0D - Make naming consistent to CMO, remove all CBO references=0D - Add ASSERT for not supported functions instead of plain debug message= =0D - Added RB tag=0D V6:=0D - Utilize cache management instructions if HW supports it=0D This patch is part of restructuring on top of v5=0D =0D MdePkg/MdePkg.dec | 8 += =0D MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 += =0D MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 177 += +++++++++++++++----=0D MdePkg/MdePkg.uni | 4 += =0D 4 files changed, 166 insertions(+), 28 deletions(-)=0D =0D diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec=0D index ac54338089e8..fa92673ff633 100644=0D --- a/MdePkg/MdePkg.dec=0D +++ b/MdePkg/MdePkg.dec=0D @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AAR= CH64]=0D # @Prompt CPU Rng algorithm's GUID.=0D gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x0= 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x0000= 0037=0D =0D +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64]=0D + #=0D + # Configurability to override RISC-V CPU Features=0D + # BIT 0 =3D Cache Management Operations. This bit is relevant only if=0D + # previous stage has feature enabled and user wants to disable it.=0D + #=0D + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT= 64|0x69=0D +=0D [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D ## This value is used to set the base address of PCI express hierarchy.= =0D # @Prompt PCI Express Base Address.=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf=0D index 6fd9cbe5f6c9..601a38d6c109 100644=0D --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf=0D +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf=0D @@ -56,3 +56,8 @@ [LibraryClasses]=0D BaseLib=0D DebugLib=0D =0D +[LibraryClasses.RISCV64]=0D + PcdLib=0D +=0D +[Pcd.RISCV64]=0D + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES=0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/RiscVCache.c=0D index ac2a3c23a249..7c53a17abbb5 100644=0D --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c=0D +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c=0D @@ -2,6 +2,7 @@=0D RISC-V specific functionality for cache.=0D =0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2023, Rivos Inc. All rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D @@ -9,10 +10,116 @@=0D #include =0D #include =0D #include =0D +#include =0D +=0D +//=0D +// TODO: Grab cache block size and make Cache Management Operation=0D +// enabling decision based on RISC-V CPU HOB in=0D +// future when it is available and convert PcdRiscVFeatureOverride=0D +// PCD to a pointer that contains pointer to bitmap structure=0D +// which can be operated more elegantly.=0D +//=0D +#define RISCV_CACHE_BLOCK_SIZE 64=0D +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1=0D +=0D +typedef enum {=0D + CacheOpClean,=0D + CacheOpFlush,=0D + CacheOpInvld,=0D +} CACHE_OP;=0D +=0D +/**=0D +Verify CBOs are supported by this HW=0D +TODO: Use RISC-V CPU HOB once available.=0D +=0D +**/=0D +STATIC=0D +BOOLEAN=0D +RiscVIsCMOEnabled (=0D + VOID=0D + )=0D +{=0D + // If CMO is disabled in HW, skip Override check=0D + // Otherwise this PCD can override settings=0D + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_CMO_BITM= ASK) !=3D 0);=0D +}=0D +=0D +/**=0D + Performs required opeartion on cache lines in the cache coherency domain= =0D + of the calling CPU. If Address is not aligned on a cache line boundary,= =0D + then entire cache line containing Address is operated. If Address + Leng= th=0D + is not aligned on a cache line boundary, then the entire cache line=0D + containing Address + Length -1 is operated.=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D + @param Address The base address of the cache lines to=0D + invalidate.=0D + @param Length The number of bytes to invalidate from the instruction=0D + cache.=0D + @param Op Type of CMO operation to be performed=0D + @return Address.=0D +=0D +**/=0D +STATIC=0D +VOID=0D +CacheOpCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length,=0D + IN CACHE_OP Op=0D + )=0D +{=0D + UINTN CacheLineSize;=0D + UINTN Start;=0D + UINTN End;=0D +=0D + if (Length =3D=3D 0) {=0D + return;=0D + }=0D +=0D + if ((Op !=3D CacheOpInvld) && (Op !=3D CacheOpFlush) && (Op !=3D CacheOp= Clean)) {=0D + return;=0D + }=0D +=0D + ASSERT ((Length - 1) <=3D (MAX_ADDRESS - (UINTN)Address));=0D +=0D + CacheLineSize =3D RISCV_CACHE_BLOCK_SIZE;=0D +=0D + Start =3D (UINTN)Address;=0D + //=0D + // Calculate the cache line alignment=0D + //=0D + End =3D (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1)= ;=0D + Start &=3D ~((UINTN)CacheLineSize - 1);=0D +=0D + DEBUG (=0D + (DEBUG_VERBOSE,=0D + "CacheOpCacheRange: Performing Cache Management Operation %d \n", Op)= =0D + );=0D +=0D + do {=0D + switch (Op) {=0D + case CacheOpInvld:=0D + RiscVCpuCacheInvalCmoAsm (Start);=0D + break;=0D + case CacheOpFlush:=0D + RiscVCpuCacheFlushCmoAsm (Start);=0D + break;=0D + case CacheOpClean:=0D + RiscVCpuCacheCleanCmoAsm (Start);=0D + break;=0D + default:=0D + break;=0D + }=0D +=0D + Start =3D Start + CacheLineSize;=0D + } while (Start !=3D End);=0D +}=0D =0D /**=0D Invalidates the entire instruction cache in cache coherency domain of th= e=0D - calling CPU.=0D + calling CPU. Risc-V does not have currently an CBO implementation which = can=0D + invalidate the entire I-cache. Hence using Fence instruction for now. P.= S.=0D + Fence instruction may or may not implement full I-cache invd functionali= ty=0D + on all implementations.=0D =0D **/=0D VOID=0D @@ -28,17 +135,11 @@ InvalidateInstructionCache (=0D Invalidates a range of instruction cache lines in the cache coherency do= main=0D of the calling CPU.=0D =0D - Invalidates the instruction cache lines specified by Address and Length.= If=0D - Address is not aligned on a cache line boundary, then entire instruction= =0D - cache line containing Address is invalidated. If Address + Length is not= =0D - aligned on a cache line boundary, then the entire instruction cache line= =0D - containing Address + Length -1 is invalidated. This function may choose = to=0D - invalidate the entire instruction cache if that is more efficient than=0D - invalidating the specified range. If Length is 0, then no instruction ca= che=0D - lines are invalidated. Address is returned.=0D -=0D - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D -=0D + An operation from a CMO instruction is defined to operate only on the co= pies=0D + of a cache block that are cached in the caches accessible by the explici= t=0D + memory accesses performed by the set of coherent agents.In other words C= MO=0D + operations are not applicable to instruction cache. Use fence.i instruct= ion=0D + instead to achieve the same purpose.=0D @param Address The base address of the instruction cache lines to=0D invalidate. If the CPU is in a physical addressing mode,= then=0D Address is a physical address. If the CPU is in a virtua= l=0D @@ -57,9 +158,10 @@ InvalidateInstructionCacheRange (=0D )=0D {=0D DEBUG (=0D - (DEBUG_WARN,=0D - "%a:RISC-V unsupported function.\n"=0D - "Invalidating the whole instruction cache instead.\n", __func__)=0D + (DEBUG_VERBOSE,=0D + "InvalidateInstructionCacheRange: RISC-V unsupported function.\n"=0D + "Invalidating the whole instruction cache instead.\n"=0D + )=0D );=0D InvalidateInstructionCache ();=0D return Address;=0D @@ -81,7 +183,12 @@ WriteBackInvalidateDataCache (=0D VOID=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + ASSERT (FALSE);=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "WriteBackInvalidateDataCache:" \=0D + "RISC-V unsupported function.\n"=0D + ));=0D }=0D =0D /**=0D @@ -117,7 +224,12 @@ WriteBackInvalidateDataCacheRange (=0D IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, CacheOpFlush);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D +=0D return Address;=0D }=0D =0D @@ -137,7 +249,7 @@ WriteBackDataCache (=0D VOID=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + ASSERT (FALSE);=0D }=0D =0D /**=0D @@ -156,10 +268,7 @@ WriteBackDataCache (=0D =0D If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D =0D - @param Address The base address of the data cache lines to write back. = If=0D - the CPU is in a physical addressing mode, then Address i= s a=0D - physical address. If the CPU is in a virtual addressing= =0D - mode, then Address is a virtual address.=0D + @param Address The base address of the data cache lines to write back.= =0D @param Length The number of bytes to write back from the data cache.=0D =0D @return Address of cache written in main memory.=0D @@ -172,7 +281,12 @@ WriteBackDataCacheRange (=0D IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, CacheOpClean);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D +=0D return Address;=0D }=0D =0D @@ -214,10 +328,7 @@ InvalidateDataCache (=0D =0D If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D =0D - @param Address The base address of the data cache lines to invalidate. = If=0D - the CPU is in a physical addressing mode, then Address i= s a=0D - physical address. If the CPU is in a virtual addressing = mode,=0D - then Address is a virtual address.=0D + @param Address The base address of the data cache lines to invalidate.= =0D @param Length The number of bytes to invalidate from the data cache.=0D =0D @return Address.=0D @@ -230,6 +341,16 @@ InvalidateDataCacheRange (=0D IN UINTN Length=0D )=0D {=0D - DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __func__));=0D + if (RiscVIsCMOEnabled ()) {=0D + CacheOpCacheRange (Address, Length, CacheOpInvld);=0D + } else {=0D + DEBUG (=0D + (DEBUG_VERBOSE,=0D + "InvalidateDataCacheRange: Zicbom not supported.\n" \=0D + "Invalidating the whole Data cache instead.\n") \=0D + );=0D + InvalidateDataCache ();=0D + }=0D +=0D return Address;=0D }=0D diff --git a/MdePkg/MdePkg.uni b/MdePkg/MdePkg.uni=0D index 5c1fa24065c7..73b5dd8f32cc 100644=0D --- a/MdePkg/MdePkg.uni=0D +++ b/MdePkg/MdePkg.uni=0D @@ -287,6 +287,10 @@=0D =0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdGuidedExtractHandlerTableAddress_H= ELP #language en-US "This value is used to set the available memory addres= s to store Guided Extract Handlers. The required memory space is decided by= the value of PcdMaximumGuidedExtractHandler."=0D =0D +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_PROMPT #lang= uage en-US "RISC-V Feature Override"=0D +=0D +#string STR_gEfiMdePkgTokenSpaceGuid_PcdRiscVFeatureOverride_HELP #langua= ge en-US "This value is used to override any RISC-V specific features suppo= rted by this PCD"=0D +=0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_PROMPT #lan= guage en-US "PCI Express Base Address"=0D =0D #string STR_gEfiMdePkgTokenSpaceGuid_PcdPciExpressBaseAddress_HELP #langu= age en-US "This value is used to set the base address of PCI express hierar= chy."=0D -- =0D 2.39.2=0D =0D -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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