[edk2-devel] [edk2-platforms PATCH v2 1/8] Silicon/Marvell: New Marvell Odyssey processor

["Narinder Dhillon" <ndhillon@marvell.com>]

From: Narinder Dhillon <ndhillon@marvell.com>

This patch creates ArmPlatformPkg for Odyssey SoC by overriding some of
the files in original ArmPlatformPkg. Differences from standard
ArmPlatformPkg are marked with "--- MRVL Override" comment.

Signed-off-by: Narinder Dhillon <ndhillon@marvell.com>
---
 .../PrePi/AArch64/ModuleEntryPoint.S          | 136 ++++++++++
 .../ArmPlatformPkg/PrePi/PeiMPCore.inf        | 110 ++++++++
 .../Override/ArmPlatformPkg/PrePi/PrePi.c     | 238 ++++++++++++++++++
 3 files changed, 484 insertions(+)
 create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S
 create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf
 create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c

diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S
new file mode 100644
index 0000000000..481d794154
--- /dev/null
+++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S
@@ -0,0 +1,136 @@
+//
+//  Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+GCC_ASM_IMPORT(mDeviceTreeBaseAddress)  // --- MRVL Override: defined in PrePi.c
+GCC_ASM_IMPORT(mSystemMemoryEnd)        // --- MRVL Override
+ASM_FUNC(_ModuleEntryPoint)
+
+  // --- MRVL Override start
+  // Save the boot parameter to a global variable
+  adr   x10, mDeviceTreeBaseAddress
+  str   x1, [x10]
+  // --- MRVL Override end
+
+  // Do early platform specific actions
+  bl    ASM_PFX(ArmPlatformPeiBootAction)
+
+  // Get ID of this CPU in multi-core system
+  bl    ASM_PFX(ArmReadMpidr)
+  // Keep a copy of the MpId register value
+  mov   x10, x0
+
+_SetSVCMode:
+// Check if we can install the stack at the top of the System Memory or if we need
+// to install the stacks at the bottom of the Firmware Device (case the FD is located
+// at the top of the DRAM)
+_SystemMemoryEndInit:
+  ldr   x1, mSystemMemoryEnd
+
+  // --- MRVL Override start
+  // mSystemMemoryEnd shall be set by SMC call within ArmPlatformPeiBootAction
+  cmp   x1, #0xffffffffffffffff
+  bne   _SetupStackPosition
+  // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs
+  MOV64 (x1, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSystemMemorySize) - 1)
+
+  // Update the global variable
+  adr   x2, mSystemMemoryEnd
+  str   x1, [x2]
+  // --- MRVL Override end
+
+_SetupStackPosition:
+  // x1 = SystemMemoryTop
+
+  // Calculate Top of the Firmware Device
+  MOV64 (x2, FixedPcdGet64(PcdFdBaseAddress))
+  MOV32 (x3, FixedPcdGet32(PcdFdSize) - 1)
+  sub   x3, x3, #1
+  add   x3, x3, x2      // x3 = FdTop = PcdFdBaseAddress + PcdFdSize
+
+  // UEFI Memory Size (stacks are allocated in this region)
+  MOV32 (x4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize))
+
+  //
+  // Reserve the memory for the UEFI region (contain stacks on its top)
+  //
+
+  // Calculate how much space there is between the top of the Firmware and the Top of the System Memory
+  subs  x0, x1, x3   // x0 = SystemMemoryTop - FdTop
+  b.mi  _SetupStack  // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM
+  cmp   x0, x4
+  b.ge  _SetupStack
+
+  // Case the top of stacks is the FdBaseAddress
+  mov   x1, x2
+
+_SetupStack:
+  // x1 contains the top of the stack (and the UEFI Memory)
+
+  // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
+  // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
+  // top of the memory space)
+  adds  x11, x1, #1
+  b.cs  _SetupOverflowStack
+
+_SetupAlignedStack:
+  mov   x1, x11
+  b     _GetBaseUefiMemory
+
+_SetupOverflowStack:
+  // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
+  // aligned (4KB)
+  and   x1, x1, ~EFI_PAGE_MASK
+
+_GetBaseUefiMemory:
+  // Calculate the Base of the UEFI Memory
+  sub   x11, x1, x4
+
+_GetStackBase:
+  // r1 = The top of the Mpcore Stacks
+  // Stack for the primary core = PrimaryCoreStack
+  MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+  sub   x12, x1, x2
+
+  // Stack for the secondary core = Number of Cores - 1
+  MOV32 (x1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
+  sub   x12, x12, x1
+
+  // x12 = The base of the MpCore Stacks (primary stack & secondary stacks)
+  mov   x0, x12
+  mov   x1, x10
+  //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
+  MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+  MOV32 (x3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
+  bl    ASM_PFX(ArmPlatformStackSet)
+
+  // Is it the Primary Core ?
+  mov   x0, x10
+  bl    ASM_PFX(ArmPlatformIsPrimaryCore)
+  cmp   x0, #1
+  bne   _PrepareArguments
+
+_PrepareArguments:
+  mov   x0, x10
+  mov   x1, x11
+  mov   x2, x12
+
+  // Move sec startup address into a data register
+  // Ensure we're jumping to FV version of the code (not boot remapped alias)
+  ldr   x4, =ASM_PFX(CEntryPoint)
+
+  // Set the frame pointer to NULL so any backtraces terminate here
+  mov   x29, xzr
+
+  // Jump to PrePiCore C code
+  //    x0 = MpId
+  //    x1 = UefiMemoryBase
+  //    x2 = StacksBase
+  blr   x4
+
+_NeverReturn:
+  b _NeverReturn
diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf
new file mode 100644
index 0000000000..49d9e406d7
--- /dev/null
+++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf
@@ -0,0 +1,110 @@
+#/** @file
+#
+#  (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
+#  Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmPlatformPrePiMPCore
+  FILE_GUID                      = d959e387-7b91-452c-90e0-a1dbac90ddb8
+  MODULE_TYPE                    = SEC
+  VERSION_STRING                 = 1.0
+  DEFINE ORG_SOURCES_PATH        = ArmPlatformPkg/PrePi # --- MRVL Override
+
+[Sources]
+  $(ORG_SOURCES_PATH)/PrePi.h       # --- MRVL Override
+  PrePi.c
+  $(ORG_SOURCES_PATH)/MainMPCore.c  # --- MRVL Override
+
+[Sources.ARM]
+  $(ORG_SOURCES_PATH)/Arm/ArchPrePi.c                   # --- MRVL Override
+  $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.S   | GCC    # --- MRVL Override
+  $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.asm | RVCT   # --- MRVL Override
+
+[Sources.AArch64]
+  $(ORG_SOURCES_PATH)/AArch64/ArchPrePi.c               # --- MRVL Override
+  AArch64/ModuleEntryPoint.S
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  CacheMaintenanceLib
+  DebugLib
+  DebugAgentLib
+  ArmLib
+  ArmGicLib
+  IoLib
+  TimerLib
+  SerialPortLib
+  ExtractGuidedSectionLib
+  LzmaDecompressLib
+  DebugAgentLib
+  PrePiLib
+  ArmPlatformLib
+  ArmPlatformStackLib
+  MemoryAllocationLib
+  HobLib
+  PrePiHobListPointerLib
+  PlatformPeiLib
+  MemoryInitPeiLib
+  FdtLib  # --- MRVL Override
+
+[Ppis]
+  gArmMpCoreInfoPpiGuid
+
+[Guids]
+  gArmMpCoreInfoGuid
+  gEfiFirmwarePerformanceGuid
+  gFdtHobGuid  # --- MRVL Override
+
+[FeaturePcd]
+  gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdVFPEnabled
+
+  gArmTokenSpaceGuid.PcdFdBaseAddress
+  gArmTokenSpaceGuid.PcdFdSize
+
+  gArmTokenSpaceGuid.PcdFvBaseAddress
+  gArmTokenSpaceGuid.PcdFvSize
+
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicSgiIntId
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
+
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
+  gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
+
diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c
new file mode 100644
index 0000000000..5168881b18
--- /dev/null
+++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c
@@ -0,0 +1,238 @@
+/** @file
+
+  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/PrePiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PrePiHobListPointerLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PerformanceLib.h>
+
+#include <Ppi/GuidedSectionExtraction.h>
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/SecPerformance.h>
+
+#include "PrePi.h"
+#include <libfdt.h> // fdt_totalsize // --- MRVL Override
+
+#define IS_XIP()  (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\
+                  ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
+
+UINT64  mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
+                           FixedPcdGet64 (PcdSystemMemorySize) - 1;
+
+UINT64 mDeviceTreeBaseAddress = 0; // --- MRVL Override
+int fdt_check_header(const void *fdt);
+
+EFI_STATUS
+GetPlatformPpi (
+  IN  EFI_GUID  *PpiGuid,
+  OUT VOID      **Ppi
+  )
+{
+  UINTN                   PpiListSize;
+  UINTN                   PpiListCount;
+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;
+  UINTN                   Index;
+
+  PpiListSize = 0;
+  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
+  PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
+  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
+    if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
+      *Ppi = PpiList->Ppi;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+VOID
+PrePiMain (
+  IN  UINTN   UefiMemoryBase,
+  IN  UINTN   StacksBase,
+  IN  UINT64  StartTimeStamp
+  )
+{
+  EFI_HOB_HANDOFF_INFO_TABLE  *HobList;
+  ARM_MP_CORE_INFO_PPI        *ArmMpCoreInfoPpi;
+  UINTN                       ArmCoreCount;
+  ARM_CORE_INFO               *ArmCoreInfoTable;
+  EFI_STATUS                  Status;
+  CHAR8                       Buffer[500];  // --- MRVL Override
+  UINTN                       CharCount;
+  UINTN                       StacksSize;
+  FIRMWARE_SEC_PERFORMANCE    Performance;
+
+  // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
+  ASSERT (
+    IS_XIP () ||
+    ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
+     ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))
+    );
+
+  // Initialize the architecture specific bits
+  ArchInitialize ();
+
+  // Initialize the Serial Port
+  SerialPortInitialize ();
+  CharCount = AsciiSPrint (
+                Buffer,
+                sizeof (Buffer),
+                "UEFI firmware (version %s built at %a on %a)\n\r",
+                (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+                __TIME__,
+                __DATE__
+                );
+  SerialPortWrite ((UINT8 *)Buffer, CharCount);
+
+  // Initialize the Debug Agent for Source Level Debugging
+  InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+  SaveAndSetDebugTimerInterrupt (TRUE);
+
+  // Declare the PI/UEFI memory region
+  HobList = HobConstructor (
+              (VOID *)UefiMemoryBase,
+              FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
+              (VOID *)UefiMemoryBase,
+              (VOID *)StacksBase // The top of the UEFI Memory is reserved for the stacks
+              );
+  PrePeiSetHobList (HobList);
+
+  // --- MRVL Override start
+  // Build the FDT HOB
+  ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) == 0);
+  DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n",
+          mDeviceTreeBaseAddress,
+          fdt_totalsize((VOID *)mDeviceTreeBaseAddress)));
+
+  BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDeviceTreeBaseAddress));
+  // --- MRVL Override end
+
+  // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
+  Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
+  ASSERT_EFI_ERROR (Status);
+
+  // Create the Stacks HOB (reserve the memory for all stacks)
+  if (ArmIsMpCore ()) {
+    StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
+                 ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
+  } else {
+    StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
+  }
+
+  BuildStackHob (StacksBase, StacksSize);
+
+  // TODO: Call CpuPei as a library
+  BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
+
+  if (ArmIsMpCore ()) {
+    // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
+    Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
+
+    // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
+    ASSERT_EFI_ERROR (Status);
+
+    // Build the MP Core Info Table
+    ArmCoreCount = 0;
+    Status       = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+    if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
+      // Build MPCore Info HOB
+      BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
+    }
+  }
+
+  // Store timer value logged at the beginning of firmware image execution
+  Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
+
+  // Build SEC Performance Data Hob
+  BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
+
+  // Set the Boot Mode
+  SetBootMode (ArmPlatformGetBootMode ());
+
+  // Initialize Platform HOBs (CpuHob and FvHob)
+  Status = PlatformPeim ();
+  ASSERT_EFI_ERROR (Status);
+
+  // Now, the HOB List has been initialized, we can register performance information
+  PERF_START (NULL, "PEI", NULL, StartTimeStamp);
+
+  // SEC phase needs to run library constructors by hand.
+  ProcessLibraryConstructorList ();
+
+  // Assume the FV that contains the SEC (our code) also contains a compressed FV.
+  Status = DecompressFirstFv ();
+  ASSERT_EFI_ERROR (Status);
+
+  // Load the DXE Core and transfer control to it
+  Status = LoadDxeCoreFromFv (NULL, 0);
+  ASSERT_EFI_ERROR (Status);
+}
+
+VOID
+CEntryPoint (
+  IN  UINTN  MpId,
+  IN  UINTN  UefiMemoryBase,
+  IN  UINTN  StacksBase
+  )
+{
+  UINT64  StartTimeStamp;
+
+  // Initialize the platform specific controllers
+  ArmPlatformInitialize (MpId);
+
+  if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
+    // Initialize the Timer Library to setup the Timer HW controller
+    TimerConstructor ();
+    // We cannot call yet the PerformanceLib because the HOB List has not been initialized
+    StartTimeStamp = GetPerformanceCounter ();
+  } else {
+    StartTimeStamp = 0;
+  }
+
+  // Data Cache enabled on Primary core when MMU is enabled.
+  ArmDisableDataCache ();
+  // Invalidate instruction cache
+  ArmInvalidateInstructionCache ();
+  // Enable Instruction Caches on all cores.
+  ArmEnableInstructionCache ();
+
+  // Define the Global Variable region when we are not running in XIP
+  if (!IS_XIP ()) {
+    if (ArmPlatformIsPrimaryCore (MpId)) {
+      if (ArmIsMpCore ()) {
+        // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
+        ArmCallSEV ();
+      }
+    } else {
+      // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
+      ArmCallWFE ();
+    }
+  }
+
+  // If not primary Jump to Secondary Main
+  if (ArmPlatformIsPrimaryCore (MpId)) {
+    InvalidateDataCacheRange (
+      (VOID *)UefiMemoryBase,
+      FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
+      );
+
+    // Goto primary Main.
+    PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
+  } else {
+    SecondaryMain (MpId);
+  }
+
+  // DXE Core should always load and never return
+  ASSERT (FALSE);
+}
-- 
2.34.1



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