From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 061DB941A83 for ; Wed, 3 Jan 2024 13:59:14 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=ya3H4KWy6MRImq6QtAfn0QoCchztw4FU+H26/KmVq5M=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1704290353; v=1; b=So+zc1nN6hV+ne3j78O3P0qj9IjtvtbjNoz14f/1gJjOLvkh/oxJJTgnhWXHiIUhfpuCRbTi NH0OmH9J44jkhOUD8XoymAFZxIt6dghisxmOrVr9ZcIOz6d+rm7uNCJ6pste0YWsdYjyZQPGsWt A6dgdGoKtoSEtYUjf+uPp7T4= X-Received: by 127.0.0.2 with SMTP id bKNpYY7687511xaihJTnjJAJ; Wed, 03 Jan 2024 05:59:13 -0800 X-Received: from mail-il1-f170.google.com (mail-il1-f170.google.com [209.85.166.170]) by mx.groups.io with SMTP id smtpd.web10.17862.1704290353152579750 for ; Wed, 03 Jan 2024 05:59:13 -0800 X-Received: by mail-il1-f170.google.com with SMTP id e9e14a558f8ab-35fe456b94cso51210165ab.3 for ; Wed, 03 Jan 2024 05:59:13 -0800 (PST) X-Gm-Message-State: ANjoHmdUU2BeHZJrIfP7bd1zx7686176AA= X-Google-Smtp-Source: AGHT+IHFtANIJMge4DngBARt97RKbcR5e4kbGrEdT28qDTgJIqWKcvJQEKardppEGx/l+rQUDJB5+A== X-Received: by 2002:a5d:9c4b:0:b0:7ba:9b64:88fe with SMTP id 11-20020a5d9c4b000000b007ba9b6488femr26638610iof.17.1704290351599; Wed, 03 Jan 2024 05:59:11 -0800 (PST) X-Received: from sunil-laptop.dc1.ventanamicro.com ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id w6-20020a056638378600b0046dcaba1adesm1213393jal.62.2024.01.03.05.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:59:11 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Gerd Hoffmann , Rahul Kumar , Laszlo Ersek , Ray Ni , Andrei Warkentin Subject: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc Date: Wed, 3 Jan 2024 19:28:48 +0530 Message-Id: <20240103135849.127251-4-sunilvl@ventanamicro.com> In-Reply-To: <20240103135849.127251-1-sunilvl@ventanamicro.com> References: <20240103135849.127251-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=So+zc1nN; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Sstc extension allows to program the timer and receive the interrupt without using an SBI call. This reduces the latency to generate the timer interrupt. So, detect whether Sstc extension is supported and use the stimecmp register directly to program the timer interrupt. Cc: Gerd Hoffmann Cc: Rahul Kumar Cc: Laszlo Ersek Cc: Ray Ni Cc: Andrei Warkentin Signed-off-by: Sunil V L --- .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 ++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +++++++++++++++++-- 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf index aba660186dc0..f2a2cf12caef 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf @@ -41,6 +41,7 @@ [Sources.RISCV64] Timer.c [Pcd] + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES [Protocols] diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h index 9b3542230cb5..5e5071b3f0b2 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h @@ -26,6 +26,8 @@ // #define DEFAULT_TIMER_TICK_DURATION 100000 +#define RISCV_CPU_FEATURE_SSTC_BITMASK 0x2 + extern VOID RiscvSetTimerPeriod ( UINT32 TimerPeriod diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c index 30e48061cd06..4babfb4bfc60 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c @@ -44,6 +44,19 @@ STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; STATIC UINT64 mTimerPeriod = 0; STATIC UINT64 mLastPeriodStart = 0; +/** + Check whether Sstc is enabled in PCD. + +**/ +STATIC +BOOLEAN +RiscVIsSstcEnabled ( + VOID + ) +{ + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_SSTC_BITMASK) != 0); +} + /** Timer Interrupt Handler. @@ -94,7 +107,12 @@ TimerInterruptHandler ( ), 1000000u ); // convert to tick - SbiSetTimer (PeriodStart); + if (RiscVIsSstcEnabled ()) { + RiscVSetSupervisorTimeCompareRegister (PeriodStart); + } else { + SbiSetTimer (PeriodStart); + } + RiscVEnableTimerInterrupt (); // enable SMode timer int gBS->RestoreTPL (OriginalTPL); } @@ -197,7 +215,11 @@ TimerDriverSetTimerPeriod ( ), 1000000u ); // convert to tick - SbiSetTimer (PeriodStart); + if (RiscVIsSstcEnabled ()) { + RiscVSetSupervisorTimeCompareRegister (PeriodStart); + } else { + SbiSetTimer (PeriodStart); + } mCpu->EnableInterrupt (mCpu); RiscVEnableTimerInterrupt (); // enable SMode timer int @@ -282,6 +304,10 @@ TimerDriverInitialize ( // mTimerNotifyFunction = NULL; + if (RiscVIsSstcEnabled ()) { + DEBUG ((DEBUG_INFO, "%a: Timer interrupt is via Sstc extension\n", __func__)); + } + // // Make sure the Timer Architectural Protocol is not already installed in the system // -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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