From: "Zhi Jin" <zhi.jin@intel.com>
To: devel@edk2.groups.io
Cc: Zhi Jin <zhi.jin@intel.com>, Ray Ni <ray.ni@intel.com>,
Laszlo Ersek <lersek@redhat.com>,
Rahul Kumar <rahul1.kumar@intel.com>,
Gerd Hoffmann <kraxel@redhat.com>,
Jiaxin Wu <jiaxin.wu@intel.com>
Subject: [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll
Date: Fri, 5 Jan 2024 10:04:09 +0800 [thread overview]
Message-ID: <20240105020409.902684-1-zhi.jin@intel.com> (raw)
PatchSmmSaveStateMap patches the SMM entry (code) and SmmSaveState
region (data) for each core, which can be improved to flush TLB once
after all the memory entries have been patched.
FlushTlbForAll flushes TLB for each core in serial, which can be
improved to flush TLB in parrallel.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Signed-off-by: Zhi Jin <zhi.jin@intel.com>
---
.../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 95 ++++++++++++-------
1 file changed, 63 insertions(+), 32 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 15f998e501..d4066436f5 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -547,17 +547,14 @@ FlushTlbForAll (
VOID
)
{
- UINTN Index;
-
FlushTlbOnCurrentProcessor (NULL);
-
- for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- if (Index != gSmst->CurrentlyExecutingCpu) {
- // Force to start up AP in blocking mode,
- SmmBlockingStartupThisAp (FlushTlbOnCurrentProcessor, Index, NULL);
- // Do not check return status, because AP might not be present in some corner cases.
- }
- }
+ InternalSmmStartupAllAPs (
+ (EFI_AP_PROCEDURE2)FlushTlbOnCurrentProcessor,
+ 0,
+ NULL,
+ NULL,
+ NULL
+ );
}
/**
@@ -799,71 +796,105 @@ PatchSmmSaveStateMap (
UINTN TileCodeSize;
UINTN TileDataSize;
UINTN TileSize;
+ UINTN PageTableBase;
- TileCodeSize = GetSmiHandlerSize ();
- TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
- TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
- TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
- TileSize = TileDataSize + TileCodeSize - 1;
- TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
+ TileCodeSize = GetSmiHandlerSize ();
+ TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
+ TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
+ TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
+ TileSize = TileDataSize + TileCodeSize - 1;
+ TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
+ PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n"));
for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) {
//
// Code
//
- SmmSetMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
TileCodeSize,
- EFI_MEMORY_RO
+ EFI_MEMORY_RO,
+ TRUE,
+ NULL
);
- SmmClearMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET,
TileCodeSize,
- EFI_MEMORY_XP
+ EFI_MEMORY_XP,
+ FALSE,
+ NULL
);
//
// Data
//
- SmmClearMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + TileCodeSize,
TileSize - TileCodeSize,
- EFI_MEMORY_RO
+ EFI_MEMORY_RO,
+ FALSE,
+ NULL
);
- SmmSetMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[Index] + SMM_HANDLER_OFFSET + TileCodeSize,
TileSize - TileCodeSize,
- EFI_MEMORY_XP
+ EFI_MEMORY_XP,
+ TRUE,
+ NULL
);
}
//
// Code
//
- SmmSetMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET,
TileCodeSize,
- EFI_MEMORY_RO
+ EFI_MEMORY_RO,
+ TRUE,
+ NULL
);
- SmmClearMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET,
TileCodeSize,
- EFI_MEMORY_XP
+ EFI_MEMORY_XP,
+ FALSE,
+ NULL
);
//
// Data
//
- SmmClearMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET + TileCodeSize,
SIZE_32KB - TileCodeSize,
- EFI_MEMORY_RO
+ EFI_MEMORY_RO,
+ FALSE,
+ NULL
);
- SmmSetMemoryAttributes (
+ ConvertMemoryPageAttributes (
+ PageTableBase,
+ mPagingMode,
mCpuHotPlugData.SmBase[mMaxNumberOfCpus - 1] + SMM_HANDLER_OFFSET + TileCodeSize,
SIZE_32KB - TileCodeSize,
- EFI_MEMORY_XP
+ EFI_MEMORY_XP,
+ TRUE,
+ NULL
);
}
--
2.39.2
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next reply other threads:[~2024-01-05 2:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-05 2:04 Zhi Jin [this message]
[not found] <17A7512BA8BD522D.25044@groups.io>
2024-01-05 2:20 ` [edk2-devel] [PATCH 1/1] UefiCpuPkg/PiSmmCpuDxeSmm: Optimize PatchSmmSaveStateMap and FlushTlbForAll Ni, Ray
2024-01-05 2:37 ` Zhi Jin
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