From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 94B51740070 for ; Thu, 11 Jan 2024 09:00:09 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=iekwO9H8oIUKbQAMSReFpbugT6yoNkpTthhI9uAjklU=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1704963606; v=1; b=uTtpgpKPTiScpKg6+NQgAsBg1gK7EaNYQcA/NT6q4/nfeaja91hqd/u24dY0Q0r9ZHgOLutt urQH6D2HAB/iZmV1wTisxESQUBRD3kYq5HzxuarRBVmc+Oo3ccKwA+HROXdVa7U8k4laohApPzK GpXLS1Y/rswVNex8ujIx0YR8= X-Received: by 127.0.0.2 with SMTP id QfxFYY7687511x1jcH1uVDmP; Thu, 11 Jan 2024 01:00:06 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.7619.1704963605950076673 for ; Thu, 11 Jan 2024 01:00:06 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="6145502" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="6145502" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 01:00:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10949"; a="1029473239" X-IronPort-AV: E=Sophos;i="6.04,185,1695711600"; d="scan'208";a="1029473239" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2024 00:59:59 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V3] UefiCpuPkg:Limit PhysicalAddressBits in special case Date: Thu, 11 Jan 2024 16:59:47 +0800 Message-Id: <20240111085947.1105-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: XmYA28RxkeL6WVbNH0C6v02cx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=uTtpgpKP; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io When creating smm page table, limit maximum supported physical address bits returned by CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled. When 5-Level Paging is disabled and the PhysicalAddressBits retrived from CPU HOB or CpuId is bigger than 47, and since virtual addresses are sign-extended, only [0, 2^47-1] range in 52-bit physical address is mapped in page table. Signed-off-by: Dun Tan Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index ddd9be66b5..35c282a771 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -137,11 +137,13 @@ GetSubEntriesNum ( /** Calculate the maximum support address. + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed. + @return the maximum support address. **/ UINT8 CalculateMaximumSupportAddress ( - VOID + BOOLEAN Is5LevelPagingNeeded ) { UINT32 RegEax; @@ -164,6 +166,15 @@ CalculateMaximumSupportAddress ( } } + // + // Only [0, 2^47 -1] in 52-bit physical addresses is mapped in page table + // when 5-Level Paging is disabled. + // + ASSERT (PhysicalAddressBits <= 52); + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) { + PhysicalAddressBits = 47; + } + return PhysicalAddressBits; } @@ -197,7 +208,7 @@ SmmInitPageTable ( mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess); m1GPageTableSupport = Is1GPageSupport (); m5LevelPagingNeeded = Is5LevelPagingNeeded (); - mPhysicalAddressBits = CalculateMaximumSupportAddress (); + mPhysicalAddressBits = CalculateMaximumSupportAddress (m5LevelPagingNeeded); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); if (m5LevelPagingNeeded) { mPagingMode = m1GPageTableSupport ? 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