From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 49DA374003B for ; Fri, 12 Jan 2024 08:31:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=hogJxZD4ydPUjLItITFlBj9zmx8ybpAvvAX4jBR8v84=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1705048316; v=1; b=m8DA2QDvKurScxQsD9pYwXe39E1L1bjA4dP0k8g/xeYgtvQ29CSMmhJbggWQoyVU5RAddsKg Fc/jvdWN60Y3/iDqsMm6JfyXr0IFZdv/h2ZC4JZs5UkLUcRvGLGVDqqwGA9mqKxR9+q3YEVM+Js y/MXZP0RC2lIUxSV4A+gzJsU= X-Received: by 127.0.0.2 with SMTP id f5ZkYY7687511xRcAm6lBCeu; Fri, 12 Jan 2024 00:31:56 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mx.groups.io with SMTP id smtpd.web10.3183.1705048315090948230 for ; Fri, 12 Jan 2024 00:31:55 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10950"; a="5878632" X-IronPort-AV: E=Sophos;i="6.04,188,1695711600"; d="scan'208";a="5878632" X-Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 00:31:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,188,1695711600"; d="scan'208";a="24933978" X-Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2024 00:31:53 -0800 From: "duntan" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [Patch V4] UefiCpuPkg:Limit PhysicalAddressBits in special case Date: Fri, 12 Jan 2024 16:31:42 +0800 Message-Id: <20240112083142.230-1-dun.tan@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dun.tan@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: gj4qOWRGUptdQqaKewf5fXMwx7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=m8DA2QDv; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io When creating smm page table, limit maximum supported physical addresses bits returned by CalculateMaximumSupportAddress() to 47 if 5-Level Paging is disabled. This commit is to avoid issue that more than 47-bit physical addresses are requested in smm page table when 5-level paging is disabled. 4-level paging supports translating 48-bit linear addresses to 52-bit physical addresses. Since linear addresses are sign-extended, linear-address space of 4-level paging is: [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff]. So only [0, 2^47-1] linear-address range maps to the identical physical-address range when 5-Level paging is disabled. Signed-off-by: Dun Tan Reviewed-by: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index ddd9be66b5..5964884762 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -137,11 +137,13 @@ GetSubEntriesNum ( /** Calculate the maximum support address. + @param[in] Is5LevelPagingNeeded If 5-level paging enabling is needed. + @return the maximum support address. **/ UINT8 CalculateMaximumSupportAddress ( - VOID + BOOLEAN Is5LevelPagingNeeded ) { UINT32 RegEax; @@ -164,6 +166,18 @@ CalculateMaximumSupportAddress ( } } + // + // 4-level paging supports translating 48-bit linear addresses to 52-bit physical addresses. + // Since linear addresses are sign-extended, the linear-address space of 4-level paging is: + // [0, 2^47-1] and [0xffff8000_00000000, 0xffffffff_ffffffff]. + // So only [0, 2^47-1] linear-address range maps to the identical physical-address range when + // 5-Level paging is disabled. + // + ASSERT (PhysicalAddressBits <= 52); + if (!Is5LevelPagingNeeded && (PhysicalAddressBits > 47)) { + PhysicalAddressBits = 47; + } + return PhysicalAddressBits; } @@ -197,7 +211,7 @@ SmmInitPageTable ( mCpuSmmRestrictedMemoryAccess = PcdGetBool (PcdCpuSmmRestrictedMemoryAccess); m1GPageTableSupport = Is1GPageSupport (); m5LevelPagingNeeded = Is5LevelPagingNeeded (); - mPhysicalAddressBits = CalculateMaximumSupportAddress (); + mPhysicalAddressBits = CalculateMaximumSupportAddress (m5LevelPagingNeeded); PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); if (m5LevelPagingNeeded) { mPagingMode = m1GPageTableSupport ? Paging5Level1GB : Paging5Level; -- 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113692): https://edk2.groups.io/g/devel/message/113692 Mute This Topic: https://groups.io/mt/103679520/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-