[edk2-devel] [edk2-platforms][PATCH v3 6/6] Platform/Sgi: Extend SMBIOS support for RD-V2 platform

["Prabin CA" <prabin.ca@arm.com>]

From: Pranav Madhu <pranav.madhu@arm.com>

The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
RD-V2 platform.

Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Prabin CA <prabin.ca@arm.com>
---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c    |  7 +++++--
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |  9 ++++++---
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c     | 20 +++++++++++++++++++-
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..edf2a5f63c63 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -5,7 +5,7 @@
   Reference Design platforms. Type 1 table defines attributes of the
   overall system such as manufacturer, product name, UUID etc.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -33,7 +33,8 @@
   "RdV1Mc\0"                                            \
   "RdN2\0"                                              \
   "RdN2Cfg1\0"                                          \
-  "RdN2Cfg2\0"
+  "RdN2Cfg2\0"                                          \
+  "RdV2\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e, 0xda}},
   /* Rd-N2-Cfg2    */
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 0x60}},
+  /* Rd-V2         */
+  {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 0x45}},
 };
 
 /* System information */
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..ee269f707714 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -6,7 +6,7 @@
   family, processor id, maximum operating frequency, and other information
   related to the processor.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -27,7 +27,7 @@
 #define SOCKET_TYPE_BASE        3
 #define SOCKET_TYPE_NUM         1
 #define PROCESSOR_VERSION_BASE  (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM   10
+#define PROCESSOR_VERSION_NUM   11
 #define SERIAL_NUMBER_BASE      (PROCESSOR_VERSION_BASE + PROCESSOR_VERSION_NUM)
 #define TYPE4_STRINGS                                   \
   "0x000\0"                     /* Part Number */       \
@@ -43,6 +43,7 @@
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
   "Neoverse-N2\0"                                       \
+  "Neoverse-V2\0"                                       \
   "000-0\0"                     /* Serial number */     \
   "783-3\0"                                             \
   "786-1\0"                                             \
@@ -52,7 +53,8 @@
   "78A-2\0"                                             \
   "7B7-1\0"                                             \
   "7B6-1\0"                                             \
-  "7B7-1\0"
+  "7B7-1\0"                                             \
+  "7F2-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
     break;
   case RdN2:
   case RdN2Cfg1:
+  case RdV2:
     mArmRdSmbiosType4.Base.CoreCount = CoreCount;
     mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
     mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..4af72919a3f1 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -6,7 +6,7 @@
   implemented, cache configuration, ways of associativity and other
   information related to cache memory installed.
 
-  Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+  Copyright (c) 2021 - 2024, Arm Limited. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
@@ -334,6 +334,24 @@ InstallType7CacheInformation (
     mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192;     // 8MB SLC
     mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
     break;
+  case RdV2:
+    /* L1 instruction cache */
+    mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+    /* L1 data cache */
+    mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;    // 64KB
+    mArmRdSmbiosType7[1].Base.InstalledSize2 = 64;       // 64KB
+    mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+    /* L2 cache */
+    mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 2048;  // 2MB
+    mArmRdSmbiosType7[2].Base.InstalledSize2 = 2048;     // 2MB
+    mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+    /* System level cache */
+    mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768; // 32MB SLC
+    mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768;    // 32MB SLC
+    mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
+    break;
   }
 
   /* Install valid cache information tables */
-- 
2.34.1



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