From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id E328C941093 for ; Tue, 16 Jan 2024 07:48:49 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=hBYs5kOsfRYljPOQUpjquh+t6Mmex3WF989Bk1l0w1Y=; c=relaxed/simple; d=groups.io; h=From:Date:Subject:MIME-Version:Message-Id:References:In-Reply-To:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1705391328; v=1; b=w9ZJAJZ81ypfAMtr1+pO88wiwtwe0DGaPEbHpEUoQGXXiQspX5J2q6S4sFkt5FKUZX5XKpWF 5uVolIPBU6i9UvJcxtQd4SBvueBtr/2vYSa+IBsmJNDd9Fs/s1nF48ZKQ6av38ckR+G6AK953T0 7Nm/w0T8oeMdkd45XyTEYy/w= X-Received: by 127.0.0.2 with SMTP id qIVvYY7687511xKn1aeeUxFj; Mon, 15 Jan 2024 23:48:48 -0800 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web11.7760.1705391327690146774 for ; Mon, 15 Jan 2024 23:48:48 -0800 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 4B4BA2602C9; Tue, 16 Jan 2024 08:48:45 +0100 (CET) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id zv57Qo2SJgyw; Tue, 16 Jan 2024 08:48:43 +0100 (CET) X-Received: from [192.168.210.114] (83.11.14.94.ipv4.supernova.orange.pl [83.11.14.94]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id BCC84260720; Tue, 16 Jan 2024 08:48:42 +0100 (CET) From: "Marcin Juszkiewicz" Date: Tue, 16 Jan 2024 08:48:32 +0100 Subject: [edk2-devel] [PATCH edk2-platforms v2 1/4] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib MIME-Version: 1.0 Message-Id: <20240116-no-dt-for-cpu-v2-1-6cf078d9ab76@linaro.org> References: <20240116-no-dt-for-cpu-v2-0-6cf078d9ab76@linaro.org> In-Reply-To: <20240116-no-dt-for-cpu-v2-0-6cf078d9ab76@linaro.org> To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Marcin Juszkiewicz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 2TowjZxSu3ZBcYIn2ucExK7Px7686176AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=w9ZJAJZ8; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io This library provides functions to check for hardware information. For now it covers CPU ones: - amount of cpu cores - MPIDR value for cpu core - NUMA node id for cpu core Values are read from TF-A using platform specific SMC calls. Signed-off-by: Marcin Juszkiewicz --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- .../SbsaQemuHardwareInfoLib.inf | 32 +++++++ .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 2 + .../Include/Library/SbsaQemuHardwareInfoLib.h | 45 +++++++++ .../SbsaQemuHardwareInfoLib.c | 100 ++++++++++++++++= ++++ 5 files changed, 181 insertions(+), 1 deletion(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/S= bsaQemu.dsc index 378600050df9..07cb3490f4cf 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -1,6 +1,6 @@ # # Copyright (c) 2021, NUVIA Inc. All rights reserved. -# Copyright (c) 2019, Linaro Limited. All rights reserved. +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -128,6 +128,7 @@ [LibraryClasses.common] =20 FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf + SbsaQemuHardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareIn= foLib/SbsaQemuHardwareInfoLib.inf =20 # Debug Support PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib= /SbsaQemuHardwareInfoLib.inf new file mode 100644 index 000000000000..8c2def1878e6 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.inf @@ -0,0 +1,32 @@ +#/* @file +# +# Copyright (c) Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001c + BASE_NAME =3D SbsaQemuHardwareInfoLib + FILE_GUID =3D 6454006f-6502-46e2-9be4-4bba8d4b29fb + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Sources] + SbsaQemuHardwareInfoLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Silicon/Qemu/SbsaQemu/SbsaQemu.dec + +[LibraryClasses] + ArmSmcLib + BaseMemoryLib + DebugLib + + [Pcd] + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b= /Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7934875e4aba..e33648ee1462 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -14,5 +14,7 @@ #define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) #define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) =20 #endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.= h b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h new file mode 100644 index 000000000000..45262baf3511 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuHardwareInfoLib.h @@ -0,0 +1,45 @@ +/** @file +* +* Copyright (c) Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef SBSA_QEMU_HARDWARE_INFO_ +#define SBSA_QEMU_HARDWARE_INFO_ + +/** + Get CPU count from information passed by Qemu. + +**/ +VOID +SbsaQemuGetCpuCount ( + VOID + ); + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +SbsaQemuGetMpidr ( + IN UINTN CpuId + ); + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +SbsaQemuGetCpuNumaNode ( + IN UINTN CpuId + ); + +#endif /* SBSA_QEMU_HARDWARE_INFO_ */ diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemu= HardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/S= bsaQemuHardwareInfoLib.c new file mode 100644 index 000000000000..4df973fda75e --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwar= eInfoLib.c @@ -0,0 +1,100 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include + +/** + Get CPU count from information passed by Qemu. + +**/ +VOID +SbsaQemuGetCpuCount ( + VOID + ) +{ + UINTN Arg0; + UINTN SmcResult; + RETURN_STATUS Result; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { + DEBUG ((DEBUG_INFO, "Too old TF-A. We have to get cpu info from DT.\n"= )); + Arg0 =3D FdtHelperCountCpus(); + } + + Result =3D PcdSet32S (PcdCoreCount, Arg0); + ASSERT_RETURN_ERROR (Result); + + Arg0 =3D PcdGet32 (PcdCoreCount); + + DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0)); +} + +/** + Get MPIDR for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve MPIDR value for. + + @retval MPIDR value of CPU at index +**/ +UINT64 +SbsaQemuGetMpidr ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { + DEBUG ((DEBUG_INFO, "Too old TF-A. We have to get cpu info from DT.\n"= )); + Arg1 =3D FdtHelperGetMpidr(CpuId); +} + + DEBUG ((DEBUG_ERROR, "MPIDR for CPU:%d =3D %d\n", CpuId, Arg1)); + + return Arg1; +} + +/** + Get NUMA node id for a given cpu from device tree passed by Qemu. + + @param [in] CpuId Index of cpu to retrieve NUMA node id for. + + @retval NUMA node id for CPU at index +**/ +UINT64 +SbsaQemuGetCpuNumaNode ( + IN UINTN CpuId + ) +{ + UINTN SmcResult; + UINTN Arg0; + UINTN Arg1; + + Arg0 =3D CpuId; + + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { + /* No fallback to DeviceTree as we did not had that info earlier. */ + DEBUG ((DEBUG_ERROR, "Couldn't find information for CPU:%d\n", CpuId))= ; + return 0; + } + + DEBUG ((DEBUG_ERROR, "NUMA node for CPU:%d =3D %d\n", CpuId, Arg0)); + + return Arg0; +} --=20 2.43.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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