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Thu, 18 Jan 2024 00:50:50 -0600 From: "duke.zhai via groups.io" To: CC: Duke Zhai , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH 02/33] AMD/VanGoghBoard: Check in ACPI tables Date: Thu, 18 Jan 2024 14:50:15 +0800 Message-ID: <20240118065046.961-3-duke.zhai@amd.com> In-Reply-To: <20240118065046.961-1-duke.zhai@amd.com> References: <20240118065046.961-1-duke.zhai@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|CH3PR12MB9145:EE_ X-MS-Office365-Filtering-Correlation-Id: 30f8ca91-4dc3-40e7-4004-08dc17f1d0dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: 18Ska+DIeniivkysrTG/3LHQRZCP9YczRufBh0Oq7W0oTh0J9Vd1gbB9lzHcg8yFrYfNC6ogsSzLZneXIO/xxhB1VR/kou7bbsOz98byO8Nj4LdGq7zUSu7y3XQqAWHr0Gfe5C8JdIdlVEFrWaf2PVsApl1UjBWrKF8pnsgreu1r+uTdgUSKMf85QaufEXdWNUnCWkyolaq8jLztSt79+JnQLBOcquQ84/QSV7d0GlCL74OzKp92OBHn49dKTZn3N+wTWQaolWJh3WoEyRCTDI/JzpuQN1QP8hR6IUVt9NA0OQi8kK1xRJPu7/ylkCk8/MxXqQjjZdP9X4FB1LZcZvXfwa7s/v2orpnMEHfJGtiTqS/4EzjPz7knk9lceJmWqyc9F1DI+Fb8zRpZ9OYB8qmrXtBhYVHHpqpZatfaugFyeR4YjNulX6Q2603N/RJIvrDYZUPhBqK4IDADld0odj278ohLHh1dqIEJ73nCTIm1zmTKFLQZjbN3M5wXMIEYH5R43QbOWBPRun0P4JNdyI66YUPF8ePPgQJIs10xbUPhuNO2d3eQ2pSjWPgWZg59wVuvI72OVfp7AFnyThq/Bs79rkxrHWc7QtVEPjajhxR9+XKTr9kIrOXVGPRhySokgm/Sp7UUyZBUyueHdlmIrudYZ5WBxHmDgjm819/vLRbkJTMmhYa3a4CTqpj6sv8eGT1SfC4+wpL7PwzlRkZBC1fRf/2clxPljvqu1PZaZLdp9jZ9j5sENVB4dfmpGB0HeBGh96vBJPzsXwIbyz3hFxBSU0/319Sn3E9ZVG2qR5bP3ednYLzBC+mCzwKRNP7Cf/jGcEWEuuXFPZ1C32WeTA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2024 06:50:53.7170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30f8ca91-4dc3-40e7-4004-08dc17f1d0dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9145 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 28L7R4NQFIpBMRHNo1suNdpcx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=rOQoHXvr; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Duke Zhai BZ #:4640 This module creates ACPI trunk tables for Chachani board, e.g.: DSDT table,= FADT table. Signed-off-by: Eric Xing Cc: Duke Zhai Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Acpi/AcpiTables/AcpiTables.inf | 33 + .../Acpi/AcpiTables/Dsdt/CPU.asl | 22 + .../Acpi/AcpiTables/Dsdt/Dsdt.asl | 36 + .../Acpi/AcpiTables/Dsdt/FchShang.asi | 927 ++++++++++++++++++ .../Acpi/AcpiTables/Dsdt/GloblNvs.asl | 17 + .../Acpi/AcpiTables/Dsdt/HOST_BUS.ASL | 209 ++++ .../Acpi/AcpiTables/Dsdt/LINK.ASL | 481 +++++++++ .../Acpi/AcpiTables/Dsdt/Lpc0.asl | 168 ++++ .../Acpi/AcpiTables/Dsdt/PciTree.asl | 776 +++++++++++++++ .../Acpi/AcpiTables/Dsdt/Platform.asl | 135 +++ .../Acpi/AcpiTables/Dsdt/_PR.asl | 36 + .../Acpi/AcpiTables/Facs/Facs.h | 45 + .../Acpi/AcpiTables/Facs/Facs50.aslc | 68 ++ .../Acpi/AcpiTables/Fadt/Fadt.h | 65 ++ .../Acpi/AcpiTables/Fadt/Fadt50.aslc | 159 +++ .../Acpi/AcpiTables/Hpet/Hpet.h | 71 ++ .../Acpi/AcpiTables/Hpet/Hpet50.aslc | 58 ++ .../Acpi/AcpiTables/Madt/Madt.h | 138 +++ .../Acpi/AcpiTables/Madt/Madt50.aslc | 327 ++++++ .../Acpi/AcpiTables/Mcfg/Mcfg.h | 75 ++ .../Acpi/AcpiTables/Mcfg/Mcfg50.aslc | 61 ++ 21 files changed, 3907 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/AcpiTables.inf create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/CPU.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/Dsdt.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/FchShang.asi create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/GloblNvs.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/HOST_BUS.ASL create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/LINK.ASL create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/Lpc0.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/PciTree.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/Platform.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Dsdt/_PR.asl create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Facs/Facs.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Facs/Facs50.aslc create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Fadt/Fadt.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Fadt/Fadt50.aslc create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Hpet/Hpet.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Hpet/Hpet50.aslc create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Madt/Madt.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Madt/Madt50.aslc create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Mcfg/Mcfg.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTab= les/Mcfg/Mcfg50.aslc diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Acp= iTables.inf b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Ac= piTables.inf new file mode 100644 index 0000000000..082422420e --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/AcpiTables= .inf @@ -0,0 +1,33 @@ +## @file +# Acpi Platform Dxe driver +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D AcpiTables + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + Fadt/Fadt50.aslc + Facs/Facs50.aslc + Hpet/Hpet50.aslc + Madt/Madt50.aslc + Mcfg/Mcfg50.aslc + Dsdt/Dsdt.asl + +[Packages] + MdePkg/MdePkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress \ No newline at end of file diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/CPU.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt= /CPU.asl new file mode 100644 index 0000000000..485fb4ec40 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/CPU.a= sl @@ -0,0 +1,22 @@ +// /** @file +// Acpi CPU.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +Scope(\_PR) +{ + // Operator 'Processor(){}' is deprecated, and may be required for compa= tibility with some legacy OSes. + // Unique Name, ID, P_BLK Add, P_BLK Length + Processor(C000, 0x00, 0x00000410, 0x06) {} + Processor(C001, 0x01, 0x00000410, 0x06) {} + Processor(C002, 0x02, 0x00000410, 0x06) {} + Processor(C003, 0x03, 0x00000410, 0x06) {} + Processor(C004, 0x04, 0x00000410, 0x06) {} + Processor(C005, 0x05, 0x00000410, 0x06) {} + Processor(C006, 0x06, 0x00000410, 0x06) {} + Processor(C007, 0x07, 0x00000410, 0x06) {} +} // End _PR diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/Dsdt.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/Dsdt.asl new file mode 100644 index 0000000000..75e2339d52 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.= asl @@ -0,0 +1,36 @@ +// /** @file +// Acpi Dsdt.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + "AMD ", // OEM ID (6 byte string) + "EDK2 ", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + // Miscellaneous services enabled in Project + include ("GloblNvs.asl") + include ("PciTree.asl") + include ("Platform.asl") + include ("FchShang.asi") + // + // Processor Objects + // + include("_PR.asl") + // System \_Sx states + Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state + Name(\_S1, Package(4) {0x1,0x0,0,0}) + Name(\_S3, Package(4) {0x3,0x0,0,0}) + Name(\_S4, Package(4) {0x4,0x0,0,0}) + Name(\_S5, Package(4) {0x5,0x0,0,0}) // mandatory System state +}// End of ASL File diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/FchShang.asi b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables= /Dsdt/FchShang.asi new file mode 100644 index 0000000000..13968e05fd --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/FchSh= ang.asi @@ -0,0 +1,927 @@ +// /** @file +// Acpi FchShang.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ +Name (TSOS, 0x75) + +If(CondRefOf(\_OSI)) +{ + If(\_OSI("Windows 2009")) + { + Store(0x50, TSOS) + } + If(\_OSI("Windows 2015")) + { + Store(0x70, TSOS) + } +} + +Scope(\_SB) { +OperationRegion(ECMC, SystemIo, 0x72, 0x02) +Field(ECMC, AnyAcc, NoLock, Preserve) +{ + ECMI, 8, + ECMD, 8, +} +IndexField(ECMI, ECMD, ByteAcc, NoLock, Preserve) { + Offset (0x08), + FRTB, 32, +} +OperationRegion(FRTP, SystemMemory, FRTB, 0x100) +Field(FRTP, AnyAcc, NoLock, Preserve) +{ + PEBA, 32, + Offset (0x04), + , 5, + IC0E, 1, //I2C0, 5 + IC1E, 1, //I2C1, 6 + IC2E, 1, //I2C2, 7 + IC3E, 1, //I2C3, 8 + IC4E, 1, //I2C3, 9 + IC5E, 1, //I2C3, 10 + UT0E, 1, //UART0, 11 + UT1E, 1, //UART1, 12 + , 1, // 13 + , 1, //, 14 + ST_E, 1, //SATA, 15 + UT2E, 1, //UART2, 16 + , 1, + EMMD, 2, //18-19, EMMC Driver type, 0:AMD eMMC Driver (AMDI0040) 1:MS = SD Driver (PNP0D40) 2:0:MS eMMC Driver (AMDI0040) + UT4E, 1, //UART4, 20 + , 2, + XHCE, 1, //XCHI, 23 + , 1, //24 + , 1, + UT3E, 1, //UART3, 26 + ESPI, 1, //ESPI 27 + EMME, 1, //EMMC 28 + Offset (0x08), + PCEF, 1, // Post Code Enable Flag + , 4, + IC0D, 1, //I2C0, 5 + IC1D, 1, + IC2D, 1, + IC3D, 1, //I2C3, 8 + IC4D, 1, //I2C3, 9 + IC5D, 1, //I2C3, 10 + UT0D, 1, //UART0, 11 + UT1D, 1, //UART1, 12 + , 1, //, 13 + , 1, //, 14 + ST_D, 1, //SATA, 15 + UT2D, 1, //UART2, 16 + , 1, + EHCD, 1, //EHCI, 18 + , 1, + UT4D, 1, //UART4, 20 + , 2, + XHCD, 1, //XCHI, 23 + SD_D, 1, //SD, 24 + , 1, + UT3D, 1, //UART1, 26 + , 1, + EMD3, 1, //EMMC D3 28 + , 2, + S03D, 1, //S0I3 flag, 31 + Offset (0x0C), + FW00, 16, + FW01, 32, + FW02, 16, + FW03, 32, + SDS0, 8, //SataDevSlpPort0S5Pin + SDS1, 8, //SataDevSlpPort1S5Pin + CZFG, 1, //Carrizo Serials + Offset (0x20), + SD10, 32, + EH10, 32, + XH10, 32, + STBA, 32, +} +OperationRegion(FCFG, SystemMemory, PEBA, 0x01000000) +Field(FCFG, DwordAcc, NoLock, Preserve) +{ + Offset(0x000A3044), + IPDE, 32, //IO Port Decode Enable + Offset(0x000A3048), + IMPE, 32, //IO Memory Port decode Enable + Offset(0x000A3078), + , 2, + LDQ0, 1, // + Offset(0x000A30CB), + , 7, + AUSS, 1, //AutoSizeStart +} +OperationRegion(IOMX, SystemMemory, 0xFED80D00, 0x100) +Field(IOMX, AnyAcc, NoLock, Preserve) +{ + Offset (0x15), + IM15, 8, // + Offset (0x16), + IM16, 8, // + Offset (0x1F), + IM1F, 8, // + Offset (0x20), + IM20, 8, // + Offset (0x44), + IM44, 8, // + Offset (0x46), + IM46, 8, // + Offset (0x4A), + IM4A, 8, // + Offset (0x4B), + IM4B, 8, // + Offset (0x57), + IM57, 8, // + Offset (0x58), + IM58, 8, // + Offset (0x68), + IM68, 8, // + Offset (0x69), + IM69, 8, // + Offset (0x6A), + IM6A, 8, // + Offset (0x6B), + IM6B, 8, // + Offset (0x6D), + IM6D, 8, // +} +OperationRegion(FACR, SystemMemory, 0xFED81E00, 0x100) //Fch AoaC Registe= r +Field(FACR, AnyAcc, NoLock, Preserve) +{ + Offset (0x80), + ,28, + RD28, 1, //Request of Device 28, MAP + , 1, + RQTY, 1, //ReQuestTYpe + Offset (0x84), + ,28, + SD28, 1, //Status of Device 28, MAP + , 1, + Offset (0xA0), //AOACx0000A0 [PwrGood Control] (PwrGoodCtl) + PG1A, 1, +} +OperationRegion(EMMX, SystemMemory, 0xFEDD5800, 0x130) +Field(EMMX, AnyAcc, NoLock, Preserve) +{ + Offset (0xD0), + , 17, + FC18, 1, //Force1.8v + FC33, 1, //Force3.3v + , 7, // + CD_T, 1, //CD_TIE, 26 + WP_T, 1, //WP_TIE, 27 +} +OperationRegion(EMMB, SystemMemory, 0xFEDD5800, 0x130) +Field(EMMB, AnyAcc, NoLock, Preserve) +{ + Offset (0xA4), + E0A4, 32, + Offset (0xA8), + E0A8, 32, + Offset (0xB0), + E0B0, 32, + Offset (0xD0), + E0D0, 32, + Offset (0x116), + E116, 32, +} +Name (SVBF, Buffer (0x100) {0}) +CreateDWordField(SVBF, 0x000, S0A4) +CreateDWordField(SVBF, 0x004, S0A8) +CreateDWordField(SVBF, 0x008, S0B0) +CreateDWordField(SVBF, 0x00C, S0D0) +CreateDWordField(SVBF, 0x010, S116) +Method(SECR,0, Serialized) //Save Emmc Configure Register +{ +// store (E0A4, S0A4) +// store (E0A8, S0A8) +// store (E0B0, S0B0) +// store (E0D0, S0D0) + store (E116, S116) + //Do hareware save first + store (zero, RQTY) + store (one, RD28) + store (SD28, Local0) + while (Local0) {store (SD28, Local0)} +} +Method(RECR,0, Serialized) //Restore Emmc Configure Register +{ +// store (S0A4, E0A4) +// store (S0A8, E0A8) +// store (S0B0, E0B0) +// store (S0D0, E0D0) + store (S116, E116) +} + +OperationRegion(LUIE, SystemMemory, 0xFEDC0020, 0x4) //Legacy Uart Io Enab= le +Field(LUIE, AnyAcc, NoLock, Preserve) +{ + IER0, 1, //2E8 + IER1, 1, //2F8 + IER2, 1, //3E8 + IER3, 1, //3F8 + UOL0, 1, //UART0 on legacy + UOL1, 1, //UART1 on legacy + UOL2, 1, //UART2 on legacy + UOL3, 1, //UART3 on legacy + WUR0, 2, // + WUR1, 2, // + WUR2, 2, // + WUR3, 2, // +} +Method(FRUI,2, Serialized) //Fch Return Uart Interrupt +{ + if (LEqual(Arg0, 0)) {store (IUA0, Arg1)} + if (LEqual(Arg0, 1)) {store (IUA1, Arg1)} + if (LEqual(Arg0, 2)) {store (IUA2, Arg1)} + if (LEqual(Arg0, 3)) {store (IUA3, Arg1)} +} + +Method(SRAD,2, Serialized) //SoftResetAoacDevice, Arg0:Device ID, Arg1:re= set period in micro seconds +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + store (one, ADIS) // IsSwControl =3D 1 + store (zero, ADSR) // SwRstB =3D 0 + stall (Arg1) + store (one, ADSR) // SwRstB =3D 1 + store (zero, ADIS) // IsSwControl =3D 0 + stall (Arg1) +} +Method(DSAD,2, Serialized) //DxSequenceAoacDevice, Arg0:Device ID, Arg1:3= =3DD3, 0=3DD0 +{ + ShiftLeft(Arg0, 1, Local0) + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg0, ADTD)) { + if (LEqual(Arg1, 0)) { + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + } + if (LEqual(Arg1, 3)) { + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + } + } +} +Method(HSAD,2, Serialized) //Hardware dx Sequence Aoac Device, Arg0:Devic= e ID, Arg1:3=3DD3, 0=3DD0 +{ + ShiftLeft(1, Arg0, Local3) //caculate bit map location + ShiftLeft(Arg0, 1, Local0) //Caculate device register location + Add (Local0, 0xfed81e40, Local0) + OperationRegion( ADCR, SystemMemory, Local0, 0x02) + Field( ADCR, ByteAcc, NoLock, Preserve) { //AoacD3ControlRegister + ADTD, 2, + ADPS, 1, + ADPD, 1, + ADSO, 1, + ADSC, 1, + ADSR, 1, + ADIS, 1, + ADDS, 3, + } + if (LNotEqual(Arg1, ADTD)) { + if (LEqual(Arg1, 0)) { + store (One, PG1A) //power up + //D0 + store(0x00, ADTD) + store(one, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x7)) {store(ADDS, Local0)} + //Do hareware restore now + // Set RequestType to restore + store (one, RQTY) + store (one, RD28) + // Wait for restore complete + store (SD28, Local0) + while (LNot(Local0)) {store (SD28, Local0)} + } + if (LEqual(Arg1, 3)) { + //Do hareware save first + store (zero, RQTY) + store (one, RD28) + store (SD28, Local0) + while (Local0) {store (SD28, Local0)} + //D3 + store(zero, ADPD) + store(ADDS, Local0) + while (LNotEqual(Local0,0x0)) {store(ADDS, Local0)} + store(0x03, ADTD) + store (Zero, PG1A) //power down + } + } +} +OperationRegion(FPIC, SystemIo, 0xc00, 0x02)//Fch Pci Interrupt Connector +Field(ECMC, AnyAcc, NoLock, Preserve) +{ + FPII, 8, + FPID, 8, +} +IndexField(FPII, FPID, ByteAcc, NoLock, Preserve) { + Offset (0xF4), //Interrupt for UArt0 + IUA0, 8, + Offset (0xF5), + IUA1, 8, + Offset (0xF8), + IUA2, 8, + Offset (0xF9), + IUA3, 8, +} + Device(GPIO) { + Name (_HID, "AMDI0030") + Name (_CID, "AMDI0030") + Name(_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () { + // + // Interrupt resource. In this example, banks 0 & 1 share the same + // interrupt to the parent controller and similarly banks 2 & 3. + // + // N.B. The definition below is chosen for an arbitrary + // test platform. It needs to be changed to reflect the hardw= are + // configuration of the actual platform + // + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7} + + // + // Memory resource. The definition below is chosen for an arbitrar= y + // test platform. It needs to be changed to reflect the hardware + // configuration of the actual platform. + // + Memory32Fixed(ReadWrite, 0xFED81500, 0x400) + }) + + Return (RBUF) + } + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } // End Device GPIO + + + Device(FUR0) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC7000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT0E, one)) { + if (IER0) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR0 + + Device(FUR1) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDC8000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT1E, one)) { + if (UOL1) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR1 + + Device(FUR2) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,0x2) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {3} + Memory32Fixed(ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCC000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT2E, one)) { + if (UOL2) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR2 + + Device(FUR3) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,0x3) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDCD000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT3E, one)) { + if (UOL3) {Return (0)} + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR3 + + Device(FUR4) { + Name(_HID,"AMDI0020") // UART Hardware Device ID + Name(_UID,0x4) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {15} // UART4 INTR to replace I2C5 + Memory32Fixed(ReadWrite, 0xFEDD1000, 0x1000) + Memory32Fixed(ReadWrite, 0xFEDD0000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(UT4E, one)) { + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + } // End Device FUR4 + + Device(I2CA) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x0) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {10} + Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) + }) + + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC0E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (5, 200)} + } // End Device I2CA + + Device(I2CB) + { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x1) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {11} + Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000) + }) + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC1E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (6, 200)} + } // End Device I2CB + + Device(I2CC) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x2) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {4} + Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000) + }) + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC2E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (7, 200)} + } // End Device I2CC + + Device(I2CD) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x3) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {6} + Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + }) + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC3E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (8, 200)} + } // End Device I2CD + + Device(I2CE) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x4) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {14} + Memory32Fixed(ReadWrite, 0xFEDC6000, 0x1000) + }) + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC4E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (9, 200)} + } // End Device I2CE + + Device(I2CF) { + Name(_HID,"AMDI0010") // Hardware Device ID + Name(_UID,0x5) + Name(_CRS, ResourceTemplate() { + IRQ(Edge, ActiveHigh, Exclusive) {15} + Memory32Fixed(ReadWrite, 0xFEDCB000, 0x1000) + }) + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (LEqual(IC5E, one)) { Return (0x0F)} + Return (0x00) + } Else { + Return (0x00) + } + } + + Method(RSET,0) { SRAD (10, 200)} + } // End Device I2CF + + Method(EPIN, 0, NotSerialized) { //eMMC Pin Configure + //clear all LPC claim + store (zero, IPDE) + store (zero, IMPE) + //switch all pins to EMMC from LPC + store (one, IM15) + store (one, IM16) + store (one, IM20) + store (one, IM44) + store (one, IM46) + store (one, IM68) + store (one, IM69) + store (one, IM6A) + store (one, IM6B) + store (one, IM4A) + store (one, IM58) + store (one, IM4B) + store (one, IM57) + store (one, IM6D) + store (one, IM1F) + SECR () // Save Emmc Configure Register + } + + Name(NCRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} + Memory32Fixed(ReadWrite, 0xFEDD5000, 0x1000) + }) + Name(DCRS, ResourceTemplate() { + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {5} + Memory32Fixed(ReadWrite, 0xFEDD5000, 0x1000) +// GpioInt (Level, ActiveBoth, ExclusiveAndWake, PullNone, 0x0000, "\= \_SB.GPIO", 0x00, ResourceConsumer, , ) {68} // AGPIO68 for SD_CD + GpioInt(Edge, ActiveBoth, SharedAndWake, PullUp, 3000, "\\_SB.GPIO",= ,) {68} + Gpioio(Shared, PullUp, 0, 0, , "\\_SB.GPIO", ,) {68} + + }) + + Name(AHID,"AMDI0040") // Hardware Device ID + Name(ACID,"AMDI0040") // Hardware Device ID + Name(SHID,EISAID ("PNP0D40")) //SD device + Name(SCID, "PCI\\CC_080501") // _Reduce_ASL_Compiler_Warning_ = Note double \\, i.e. escape the backslash + Device(EMM0) { + Method(_HID,0, Serialized) + { + if (EMMD) + { Return (SHID) } + else + { Return (AHID) } + } + Method(_CID,0, Serialized) + { + if (EMMD) + { Return (SCID) } + else + { Return (ACID) } + } + Name(_UID,0x0) + Method(_CRS,0, Serialized) + { + if (EMD3) + { Return (DCRS) } + else + { Return (NCRS) } + } + Method(_STA, 0, NotSerialized) { + If (LGreaterEqual(TSOS, 0x70)) { + if (EMME) { + Return (0x0F) + } + Return (0x00) + } Else { + Return (0x00) + } + } + Method(_INI, 0, NotSerialized) { + if (EMME) { + EPIN () + } + } + Method(_S0W,0) { + if (LAnd(EMD3, EMME)) { Return(4) } + else { Return(0)} + } + Method(_PS0,0) { + if (LAnd(EMD3, EMME)) { + HSAD (28, 0) + RECR () // Restore Emmc Configure Register + } + } + Method(_PS3,0) { + if (LAnd(EMD3, EMME)) { + HSAD (28, 3) + } + } + } // End Device EMMC + +Device(UAR1) { // COM Port + Name(_HID, EISAID("PNP0500")) +// Name(_CID, EISAID("PNP0500")) +// Name(_HID, EISAID("PNP0501")) +// Name(_CID, EISAID("PNP0500")) + Name(_DDN, "COM1") + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER0) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x2E8, 0x2E8, 0x01, 0x08) + IRQNoFlags() {3} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + CreateByteField (BUF0, 0x04, IORL) // IO Port Low + CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // Enter Configuration Mode + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the Descriptor byte. + // + //ShiftLeft (Local0, CR70, IRQL) + FRUI (WUR0,IRQL) //get Uart interrupt number + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART1 + +Device(UAR2) { // COM Port + Name(_HID, EISAID("PNP0500")) +// Name(_CID, EISAID("PNP0500")) +// Name(_HID, EISAID("PNP0501")) +// Name(_CID, EISAID("PNP0500")) + Name(_DDN, "COM2") + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER1) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08) + IRQNoFlags() {4} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + CreateByteField (BUF0, 0x04, IORL) // IO Port Low + CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // Enter Configuration Mode + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the Descriptor byte. + // + //ShiftLeft (Local0, CR70, IRQL) + FRUI (WUR1,IRQL) //get Uart interrupt number + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART2 + +Device(UAR3) { // COM Port + Name(_HID, EISAID("PNP0500")) +// Name(_CID, EISAID("PNP0500")) +// Name(_HID, EISAID("PNP0501")) +// Name(_CID, EISAID("PNP0500")) + Name(_DDN, "COM3") + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER2) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x3E8, 0x3E8, 0x01, 0x08) + IRQNoFlags() {3} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + CreateByteField (BUF0, 0x04, IORL) // IO Port Low + CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // Enter Configuration Mode + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the Descriptor byte. + // + //ShiftLeft (Local0, CR70, IRQL) + FRUI (WUR2,IRQL) //get Uart interrupt number + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART3 + +Device(UAR4) { // COM Port + Name(_HID, EISAID("PNP0500")) +// Name(_CID, EISAID("PNP0500")) +// Name(_HID, EISAID("PNP0501")) +// Name(_CID, EISAID("PNP0500")) + Name(_DDN, "COM4") + //***************************************************** + // Method _STA: Return Status + //***************************************************** + Method (_STA, 0, NotSerialized) { // Return Status of the UART + if (IER3) {Return (0x0f)} + Return (0x00) + } // end of Method _STA + //***************************************************** + // Method _CRS: Return Current Resource Settings + //***************************************************** + Method (_CRS, 0, NotSerialized) { + Name (BUF0, ResourceTemplate() { + IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08) + IRQNoFlags() {4} + }) + // + // Create some ByteFields in the Buffer in order to + // permit saving values into the data portions of + // each of the descriptors above. + // + CreateByteField (BUF0, 0x02, IOLO) // IO Port Low + CreateByteField (BUF0, 0x03, IOHI) // IO Port Hi + CreateByteField (BUF0, 0x04, IORL) // IO Port Low + CreateByteField (BUF0, 0x05, IORH) // IO Port High + CreateWordField (BUF0, 0x09, IRQL) // IRQ + // Enter Configuration Mode + // + // Get the IO setting from the chip, and copy it + // to both the min & max for the IO descriptor. + // + // Low Bytes: + //Store (CR61, IOLO) // min. + //Store (CR61, IORL) // max. + // High Bytes: + //Store (CR60, IOHI) // min. + //Store (CR60, IORH) // max. + // + // Get the IRQ setting from the chip, and shift + // it into the Descriptor byte. + // + //ShiftLeft (Local0, CR70, IRQL) + FRUI (WUR3,IRQL) //get Uart interrupt number + Return(BUF0) // return the result + } // end _CRS Method +} // end of Device UART4 +} // Scope SB + diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/GloblNvs.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables= /Dsdt/GloblNvs.asl new file mode 100644 index 0000000000..981994651f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/Globl= Nvs.asl @@ -0,0 +1,17 @@ +// /** @file +// Acpi GloblNvs.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +OperationRegion(GNVS, SystemMemory, 0xFFFF0000, 0xAA55) +Field(GNVS, AnyAcc, NoLock, Preserve) { + Offset(0), + TOPM, 32, // Top Of Memory + NAPC, 8, // NbIoApic + PCBA, 32, // PcieBaseAddress + PCBL, 32, // PcieBaseLimit +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/HOST_BUS.ASL b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables= /Dsdt/HOST_BUS.ASL new file mode 100644 index 0000000000..ca54fbf31f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/HOST_= BUS.ASL @@ -0,0 +1,209 @@ +// /** @file +// Acpi HOST_BUS.ASL +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +// +// BUS, I/O, and MMIO resources +// +Method(_CRS, 0, Serialized) +{ + CreateDWordField(RES0, ^PM01._MIN, PMMN) + CreateDWordField(RES0, ^PM01._MAX, PMMX) + CreateDWordField(RES0, ^PM01._LEN, PMLN) + + Store(TOPM, PMMN) + Subtract(PCBA, 1, PMMX) + Subtract(PCBA, PMMN, PMLN) + + Return(RES0) +} + +Name( RES0,ResourceTemplate() +{ + // Bus + WORDBusNumber ( // Bus number resource (0); the bridge produces= bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x00FF, // Max + 0x0000, // Translation + 0x0100 // Range Length =3D Max-Min+1 + ) + + // IO + IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource (0xCF8= -0xCFF) + IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8= -0xCFF) + + WORDIO ( // Consumed-and-produced resource (all I/O belo= w CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x006F, // Max + 0x0000, // Translation + 0x0070 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0078, // Min + 0x0CF7, // Max + 0x0000, // Translation + 0x0C80 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource (all I/O abov= e CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0D00, // Min + 0xFFFF, // Max + 0x0000, // Translation + 0xF300 // Range Length + ) + + // MMIO + DWORDMEMORY ( // Descriptor for legacy VGA video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Min + 0x000BFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy OptionRom + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000C0000, // Min + 0x000DFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for BIOS Area + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000E0000, // Min + 0x000FFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for PCI MMIO + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min + 0xDFFFFFFF, // Max + 0x00000000, // Translation + 0x60000000 // Range Length + ,,, + PM01 + ) +}) + +//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) +Name(GUID, Buffer() +{ + 0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66 +}) + + +Name(SUPP, 0) // PCI _OSC Support Field value +Name(CTRL, 0) // PCI _OSC Control Field value + +Method(_OSC, 4, Serialized) +{ + // Check for proper UUID + // Save the capabilities buffer + Store(Arg3, Local0) + + // Create DWord-adressable fields from the Capabilties Buffer + CreateDWordField(Local0, 0, CDW1) + CreateDWordField(Local0, 4, CDW2) + CreateDWordField(Local0, 8, CDW3) + + // Check for proper UUID + If(LEqual(Arg0, GUID)) + { + // Save Capabilities DWord2 & 3 + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + If(Not(And(CDW1, 1))) // Query flag clear? + { + // Disable GPEs for features granted native control. + If(And(CTRL, 0x02)) + { + NHPG() + } + If(And(CTRL, 0x04)) // PME control granted? + { + NPME() + } + } + + If(LNotEqual(Arg1, One)) + { + // Unknown revision + Or(CDW1, 0x08, CDW1) + } + + If(LNotEqual(CDW3, CTRL)) + { + // Capabilities bits were masked + Or(CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + And(CTRL, 0xFE, CTRL) + Store(CTRL, CDW3) + Return(Local0) + } Else { + Or(CDW1, 4, CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/LINK.ASL b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/LINK.ASL new file mode 100644 index 0000000000..ada6a400fd --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/LINK.= ASL @@ -0,0 +1,481 @@ +// /** @file +// Acpi LINK.ASL +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 =3D System Timer +// 2 =3D 8259 PIC +// 8 =3D RTC +// 9 =3D SCI Interrupt (It may be used, we choose not to) +// 13 =3D Co-processor Error +// +// The following may be in use by legacy devices: +// 1 =3D If using PS/2 Keyboard +// 3 =3D If COMx Port Enabled and IRQ =3D 3 +// 4 =3D If COMx Port Enabled and IRQ =3D 4 +// 5 =3D If LPT Port Enabled and IRQ =3D 5 +// 6 =3D If FDC Enabled +// 7 =3D If LPT Port Enabled and IRQ =3D 7 +// 12 =3D If using PS/2 Mouse +// 14 =3D Primary IDE (If populated and in Compatibility Mode= ) +// 15 =3D Secondary IDE (If populated and in Compatibility Mo= de) +// +// The following will never be in use by legacy devices: +// 10 =3D Assign to PARC, PCRC, PERC, PGRC +// 11 =3D Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) // PCI Interrupt Link Device + Name(_UID, 1) // Unique to other Link Devices + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PARC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PARC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PARC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PARC, LNotEqual(PARC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PBRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PBRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PBRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PBRC, LNotEqual(PBRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PCRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PCRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PCRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PCRC, LNotEqual(PCRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PDRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PDRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PDRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PDRC, LNotEqual(PDRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PERC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + Method(_CRS,0,Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PERC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PERC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PERC, LNotEqual(PERC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PFRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PFRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PFRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PFRC, LNotEqual(PFRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PGRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PGRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PGRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PGRC, LNotEqual(PGRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + // Disable the PCI IRQ. + Method(_DIS, 0, Serialized) + { + Store(0x1F, PHRC) + } + + // Possible IRQ Resource Setting. + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + + // Point to specific byte. + CreateWordField(RTLA, 1, IRQ0) + // Zero out IRQ mask bits 0-15 + Store(Zero, IRQ0) + ShiftLeft(1, PHRC, IRQ0) + Return(RTLA) + } + + // Set IRQ Resource Setting. + Method(_SRS, 1, Serialized) + { + // Point to the specific byte passed in + CreateWordField(Arg0, 1, IRQ0) + // Determine the IRQ bit to set and store it + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PHRC) + } + + // PCI IRQ Status. + Method(_STA, 0, Serialized) + { + If(LAnd(PHRC, LNotEqual(PHRC, 0x1F))) + { + Return(0x000B) + } Else { + Return(0x0009) + } + } +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/Lpc0.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/Lpc0.asl new file mode 100644 index 0000000000..8af8a92631 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/Lpc0.= asl @@ -0,0 +1,168 @@ +// /** @file +// Acpi Lpc0.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +External(\_SB.ALIB, MethodObj) +#define CpmReadTable M049 +#define CpmMainTable M128 +#define CpmEcSupport 0x77 +External(CpmReadTable, MethodObj) +External(CpmMainTable) + +// Define the needed LPC registers used by ASL. + +Device(LPC0) +{ + Name(_ADR,0x140003) + + OperationRegion(ILBR, SystemMemory, 0xC00, 0x2) + Field(ILBR, AnyAcc, NoLock, Preserve) { + PIDX, 8, + PDAT, 8 + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PARC, 8, // INT A + PBRC, 8, // INT B + PCRC, 8, // INT C + PDRC, 8, // INT D + PERC, 8, // INT E + PFRC, 8, // INT F + PGRC, 8, // INT G + PHRC, 8, // INT H + } + + OperationRegion(DBG0, SystemIO, 0x80, 0x2) + Field(DBG0, WordAcc, NoLock, Preserve) { + P80H, 16 + } + + Include ("LINK.ASL") + // + // Super I/O + // +Device(EC0) +{ + Name(_HID, EISAID("PNP0C09")) // PNP ID + Mutex(Z009,0) + // Name(RHGP, 3) // To be patched to Name(_GPE, 3) if HW_Reduced_ACPI = is false + Name(_GPE, 5) // GPIO21 to be configured as EC_SCI#, it maps to Gevent#5 + Method(_STA,0,NotSerialized) { + If (LEqual (CpmReadTable (CpmMainTable, CpmEcSupport), 1)) + { + Return(0x0F) + } + else + { + Return(0) + } + } + Name(OKEC, Zero) + + // EC resources + Method(_CRS, 0, NotSerialized) { + Name(BUF0,ResourceTemplate() { + IO (Decode16, 0x662, 0x662, 0x1, 0x1) + IO (Decode16, 0x666, 0x666, 0x1, 0x1) + }) + Name(BUF1,ResourceTemplate() { + IO(Decode16,0x662,0x662,0x1,0x1) + IO(Decode16,0x666,0x666,0x1,0x1) + GpioInt ( + Edge, + ActiveLow, + ExclusiveAndWake, + PullUp, + 0, + "\\_SB.GPIO", + 0x00, + ResourceConsumer, + , + ) {22} // GPIO Interrupt Connection resource for LPC_PME_L/GEVENT= 3 + }) + +/* +//- If(LEqual(RDHW, 0x0)) { // HW_REDUCED_ACPI enabled? +//- Return(BUF0) +//- } Else { +//- Return(BUF1) +//- } +*/ + Return(BUF0) + } + + /* ---------------------------------------------------------------------= ---*/ + // Name: _REG - This method is called by drivers to register installatio= n + // and removal. For example; OS calls _REG(3,1) to indicat= e + // to the ACPI BIOS that the Embedded Controller Driver is + // present and functional. + // + // ARG0: 0=3DMemory + // 1=3DI/O + // 2=3DPCI Config + // 3=3DEmbedded Controller + // 4=3DSMBus + // + // ARG1: 0=3DHandler Not Connected + // 1=3DHandler Connected + // + Method(_REG, 2) { + If (LEqual(Arg0, 0x03)) { + // EC EnableAcpi + if (LNot(Acquire(\_SB.PCI0.LPC0.EC0.Z009,300))) { + Store(\_SB.PCI0.LPC0.EC0.STAS, Local0) + Or(Local0, 0x04, Local1) + Store(Local1, \_SB.PCI0.LPC0.EC0.STAS) + Release(\_SB.PCI0.LPC0.EC0.Z009) + } + + Store(Arg1, OKEC) + } + } // end of _REG + + +Mutex(QEVT,0) + +OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0xCF), // Miscellaneous Status and Control + STAS,8, // Bit[1] - 1, BIOS enable AC/DC switch + // 0, BIOS disable AC/DC switch + // Bit[2] - 1, BIOS enable ACPI mode + // 0, BIOS disable ACPI mode +} + +}// END device EC0 + +} // End of \_SB.PCI0.LPC0 + +scope(\_SB) +{ + OperationRegion(ILBR, SystemMemory, 0xC00, 0x2) + Field(ILBR, AnyAcc, NoLock, Preserve) { + PIDX, 8, + PDAT, 8 + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PARC, 8, // INT A + PBRC, 8, // INT B + PCRC, 8, // INT C + PDRC, 8, // INT D + PERC, 8, // INT E + PFRC, 8, // INT F + PGRC, 8, // INT G + PHRC, 8, // INT H + } + + OperationRegion(DBG0, SystemIO, 0x80, 0x2) + Field(DBG0, WordAcc, NoLock, Preserve) { + P80H, 16 + } + + Include ("LINK.ASL") +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/PciTree.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Dsdt/PciTree.asl new file mode 100644 index 0000000000..32fcaf0c52 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/PciTr= ee.asl @@ -0,0 +1,776 @@ +// /** @file +// Acpi PciTree.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +Scope(\_SB) +{ + //RTC + Device(RTC) + { + Name(_HID, EISAID("PNP0B00")) + + Name(_CRS, ResourceTemplate() // if HPET enabled + { + IO(Decode16, 0x70, 0x70, 0x01, 0x02) + }) + + Method(_STA,0,Serialized) { + // Report RTC Battery is Prensent or Not Present. + Return (0xF) + } + } + + // Thermal Zone + Device(THMZ) + { + Name (_HID, "AMDI0065") + Name (_UID, 0x00) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device(TMZ2) + { + Name (_HID, "AMDI0066") + Name (_UID, 0x00) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device(TMZ3) + { + Name (_HID, "AMDI0067") + Name (_UID, 0x00) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + Device(TMZ4) + { + Name (_HID, "AMDI0068") + Name (_UID, 0x00) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + // HPET - High Performance Event Timer + Device(HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_UID, 0x00) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + Return (RBUF) + } + } + + Name(PR00, Package() { + // Device 1 Func 1:7 --GPP [0:6] + Package(){ 0x0001FFFF, 0, LNKA, 0 }, + Package(){ 0x0001FFFF, 1, LNKB, 0 }, + Package(){ 0x0001FFFF, 2, LNKC, 0 }, + Package(){ 0x0001FFFF, 3, LNKD, 0 }, + + // Device 8 Func 1:3 --Internal GPP [0:2] + Package(){ 0x0008FFFF, 0, LNKE, 0 }, + Package(){ 0x0008FFFF, 1, LNKF, 0 }, + Package(){ 0x0008FFFF, 2, LNKG, 0 }, + + // FCH On-Chip + Package(){ 0x0014FFFF, 0, LNKA, 0 }, + Package(){ 0x0014FFFF, 1, LNKB, 0 }, + Package(){ 0x0014FFFF, 2, LNKC, 0 }, + Package(){ 0x0014FFFF, 3, LNKD, 0 }, + }) + Name(AR00, Package() { + // Device 1 Func 1:7 --GPP [0:6] + Package(){ 0x0001FFFF, 0, 0, 16 }, + Package(){ 0x0001FFFF, 1, 0, 17 }, + Package(){ 0x0001FFFF, 2, 0, 18 }, + Package(){ 0x0001FFFF, 3, 0, 19 }, + + // Device 8 Func 1:3 --Internal GPP [0:2] + Package(){ 0x0008FFFF, 0, 0, 20 }, + Package(){ 0x0008FFFF, 1, 0, 21 }, + Package(){ 0x0008FFFF, 2, 0, 22 }, + + // FCH On-Chip + Package(){ 0x0014FFFF, 0, 0, 16 }, + Package(){ 0x0014FFFF, 1, 0, 17 }, + Package(){ 0x0014FFFF, 2, 0, 18 }, + Package(){ 0x0014FFFF, 3, 0, 19 }, + }) + Name(NR00, Package() { + // Device 1 Func 1:7 --GPP [0:6] + Package(){ 0x0001FFFF, 0, 0, 32 }, + Package(){ 0x0001FFFF, 1, 0, 33 }, + Package(){ 0x0001FFFF, 2, 0, 34 }, + Package(){ 0x0001FFFF, 3, 0, 35 }, + + // Device 8 Func 1:3 --Internal GPP [0:2] + Package(){ 0x0008FFFF, 0, 0, 36 }, + Package(){ 0x0008FFFF, 1, 0, 37 }, + Package(){ 0x0008FFFF, 2, 0, 38 }, + + // FCH On-Chip + Package(){ 0x0014FFFF, 0, 0, 16 }, + Package(){ 0x0014FFFF, 1, 0, 17 }, + Package(){ 0x0014FFFF, 2, 0, 18 }, + Package(){ 0x0014FFFF, 3, 0, 19 }, + }) + + Name(PR01, Package() { + Package(){ 0x0000FFFF, 0, LNKA, 0 }, + Package(){ 0x0000FFFF, 1, LNKB, 0 }, + Package(){ 0x0000FFFF, 2, LNKC, 0 }, + Package(){ 0x0000FFFF, 3, LNKD, 0 }, + }) + Name(AR01, Package() { + Package(){ 0x0000FFFF, 0, 0, 16 }, + Package(){ 0x0000FFFF, 1, 0, 17 }, + Package(){ 0x0000FFFF, 2, 0, 18 }, + Package(){ 0x0000FFFF, 3, 0, 19 }, + }) + Name(NR01, Package() { + Package(){ 0x0000FFFF, 0, 0, 24 }, + Package(){ 0x0000FFFF, 1, 0, 25 }, + Package(){ 0x0000FFFF, 2, 0, 26 }, + Package(){ 0x0000FFFF, 3, 0, 27 }, + }) + + Name(PR02, Package() { + Package(){ 0x0000FFFF, 0, LNKE, 0 }, + Package(){ 0x0000FFFF, 1, LNKF, 0 }, + Package(){ 0x0000FFFF, 2, LNKG, 0 }, + Package(){ 0x0000FFFF, 3, LNKH, 0 }, + }) + Name(AR02, Package() { + Package(){ 0x0000FFFF, 0, 0, 20 }, + Package(){ 0x0000FFFF, 1, 0, 21 }, + Package(){ 0x0000FFFF, 2, 0, 22 }, + Package(){ 0x0000FFFF, 3, 0, 23 }, + }) + Name(NR02, Package() { + Package(){ 0x0000FFFF, 0, 0, 28 }, + Package(){ 0x0000FFFF, 1, 0, 29 }, + Package(){ 0x0000FFFF, 2, 0, 30 }, + Package(){ 0x0000FFFF, 3, 0, 31 }, + }) + + Name(PR03, Package() { + Package(){ 0x0000FFFF, 0, LNKA, 0 }, + Package(){ 0x0000FFFF, 1, LNKB, 0 }, + Package(){ 0x0000FFFF, 2, LNKC, 0 }, + Package(){ 0x0000FFFF, 3, LNKD, 0 }, + }) + Name(AR03, Package() { + Package(){ 0x0000FFFF, 0, 0, 16 }, + Package(){ 0x0000FFFF, 1, 0, 17 }, + Package(){ 0x0000FFFF, 2, 0, 18 }, + Package(){ 0x0000FFFF, 3, 0, 19 }, + }) + Name(NR03, Package() { + Package(){ 0x0000FFFF, 0, 0, 32 }, + Package(){ 0x0000FFFF, 1, 0, 33 }, + Package(){ 0x0000FFFF, 2, 0, 34 }, + Package(){ 0x0000FFFF, 3, 0, 35 }, + }) + + Name(PR04, Package() { + Package(){ 0x0000FFFF, 0, LNKE, 0 }, + Package(){ 0x0000FFFF, 1, LNKF, 0 }, + Package(){ 0x0000FFFF, 2, LNKG, 0 }, + Package(){ 0x0000FFFF, 3, LNKH, 0 }, + }) + Name(AR04, Package() { + Package(){ 0x0000FFFF, 0, 0, 20 }, + Package(){ 0x0000FFFF, 1, 0, 21 }, + Package(){ 0x0000FFFF, 2, 0, 22 }, + Package(){ 0x0000FFFF, 3, 0, 23 }, + }) + Name(NR04, Package() { + Package(){ 0x0000FFFF, 0, 0, 36 }, + Package(){ 0x0000FFFF, 1, 0, 37 }, + Package(){ 0x0000FFFF, 2, 0, 38 }, + Package(){ 0x0000FFFF, 3, 0, 39 }, + }) + + Name(PR05, Package() { + Package(){ 0x0000FFFF, 0, LNKA, 0 }, + Package(){ 0x0000FFFF, 1, LNKB, 0 }, + Package(){ 0x0000FFFF, 2, LNKC, 0 }, + Package(){ 0x0000FFFF, 3, LNKD, 0 }, + }) + Name(AR05, Package() { + Package(){ 0x0000FFFF, 0, 0, 16 }, + Package(){ 0x0000FFFF, 1, 0, 17 }, + Package(){ 0x0000FFFF, 2, 0, 18 }, + Package(){ 0x0000FFFF, 3, 0, 19 }, + }) + Name(NR05, Package() { + Package(){ 0x0000FFFF, 0, 0, 40 }, + Package(){ 0x0000FFFF, 1, 0, 41 }, + Package(){ 0x0000FFFF, 2, 0, 42 }, + Package(){ 0x0000FFFF, 3, 0, 43 }, + }) + + Name(PR06, Package() { + Package(){ 0x0000FFFF, 0, LNKE, 0 }, + Package(){ 0x0000FFFF, 1, LNKF, 0 }, + Package(){ 0x0000FFFF, 2, LNKG, 0 }, + Package(){ 0x0000FFFF, 3, LNKH, 0 }, + }) + Name(AR06, Package() { + Package(){ 0x0000FFFF, 0, 0, 20 }, + Package(){ 0x0000FFFF, 1, 0, 21 }, + Package(){ 0x0000FFFF, 2, 0, 22 }, + Package(){ 0x0000FFFF, 3, 0, 23 }, + }) + Name(NR06, Package() { + Package(){ 0x0000FFFF, 0, 0, 44 }, + Package(){ 0x0000FFFF, 1, 0, 45 }, + Package(){ 0x0000FFFF, 2, 0, 46 }, + Package(){ 0x0000FFFF, 3, 0, 47 }, + }) + + Name(PR07, Package() { + Package(){ 0x0000FFFF, 0, LNKA, 0 }, + Package(){ 0x0000FFFF, 1, LNKB, 0 }, + Package(){ 0x0000FFFF, 2, LNKC, 0 }, + Package(){ 0x0000FFFF, 3, LNKD, 0 }, + }) + Name(AR07, Package() { + Package(){ 0x0000FFFF, 0, 0, 16 }, + Package(){ 0x0000FFFF, 1, 0, 17 }, + Package(){ 0x0000FFFF, 2, 0, 18 }, + Package(){ 0x0000FFFF, 3, 0, 19 }, + }) + Name(NR07, Package() { + Package(){ 0x0000FFFF, 0, 0, 48 }, + Package(){ 0x0000FFFF, 1, 0, 49 }, + Package(){ 0x0000FFFF, 2, 0, 50 }, + Package(){ 0x0000FFFF, 3, 0, 51 }, + }) + + Name(PR17, Package() { + // Bus A; Device 0; Function 0; Internal GPU + // Bus A; Device 0; Function 1; Display HD Audio Controller + // Bus A; Device 0; Function 2; Cryptographic Coprocessor + // Bus A; Device 0; Function 3; USB 3.1 + // Bus A; Device 0; Function 4; USB 3.1 + // Bus A; Device 0; Function 5; Audio Processor + // Bus A; Device 0; Function 6; Audio Processor - HD Audio Controller + // Bus A; Device 0; Function 7; (Non) Sensor Fusion Hub + Package(){ 0x0000FFFF, 0, LNKC, 0 }, + Package(){ 0x0000FFFF, 1, LNKD, 0 }, + Package(){ 0x0000FFFF, 2, LNKA, 0 }, + Package(){ 0x0000FFFF, 3, LNKB, 0 }, + }) + Name(AR17, Package() { + Package(){ 0x0000FFFF, 0, 0, 18 }, + Package(){ 0x0000FFFF, 1, 0, 19 }, + Package(){ 0x0000FFFF, 2, 0, 16 }, + Package(){ 0x0000FFFF, 3, 0, 17 }, + }) + Name(NR17, Package() { + Package(){ 0x0000FFFF, 0, 0, 50 }, + Package(){ 0x0000FFFF, 1, 0, 51 }, + Package(){ 0x0000FFFF, 2, 0, 48 }, + Package(){ 0x0000FFFF, 3, 0, 49 }, + }) + Name(PR18, Package() { + // Bus B; Device 0; Function 0; SATA + // Bus B; Device 0; Function 1; CVIP + Package(){ 0x0000FFFF, 0, LNKG, 0 }, + Package(){ 0x0000FFFF, 1, LNKH, 0 }, + Package(){ 0x0000FFFF, 2, LNKE, 0 }, + Package(){ 0x0000FFFF, 3, LNKF, 0 }, + }) + Name(AR18, Package() { + Package(){ 0x0000FFFF, 0, 0, 22 }, + Package(){ 0x0000FFFF, 1, 0, 23 }, + Package(){ 0x0000FFFF, 2, 0, 20 }, + Package(){ 0x0000FFFF, 3, 0, 21 }, + }) + Name(NR18, Package() { + Package(){ 0x0000FFFF, 0, 0, 46 }, + Package(){ 0x0000FFFF, 1, 0, 47 }, + Package(){ 0x0000FFFF, 2, 0, 44 }, + Package(){ 0x0000FFFF, 3, 0, 45 }, + }) + + //----------------------------------------------------------------------= ----- + // List of IRQ resource buffers compatible with _PRS return format. + //----------------------------------------------------------------------= ----- + // Naming legend: + // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, = "xy" - last two characters of IRQ Link name. + // Note. PRSy name is generated if IRQ Link name starts from "LNK". + // HLxy , LLxy - reference names, can be used to access bit mask of avai= lable IRQs. HL and LL stand for active High(Low) Level triggered Irq model. + //----------------------------------------------------------------------= ----- + Name(PRSA, ResourceTemplate() // Link name: LNKA + { + IRQ(Level, ActiveLow, Shared, LLKA) {3, 4, 5, 6, 10, 11, 12, 14, 15} + }) + Alias(PRSA, PRSB) // Link name: LNKB + Alias(PRSA, PRSC) // Link name: LNKC + Alias(PRSA, PRSD) // Link name: LNKD + Alias(PRSA, PRSE) // Link name: LNKE + Alias(PRSA, PRSF) // Link name: LNKF + Alias(PRSA, PRSG) // Link name: LNKG + Alias(PRSA, PRSH) // Link name: LNKH + + //----------------------------------------------------------------------= ----- + // Begin PCI tree object scope + //----------------------------------------------------------------------= ----- + + Device(PCI0) // PCI Bridge "Host Bridge" + { + Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mod= e2 host hierarchy + Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn= 't understand the new HID + Name(_ADR, 0x00000000) + Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for = Peer PCI busses. Name can be overriden with control method placed directly = under Device scope + Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Ro= ot PCI Bus + Name(_UID, 0x0000) // Unique Bus ID, optional + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR00) // NB IOAPIC Enabled + } Else { + Return(AR00) // NB IOAPIC Disabled + } + } Else { + Return (PR00) // PIC mode + } + } + + include("HOST_BUS.ASL") + + // Motherboard Resource + Device(PMBR) + { + Name(_HID, EISAID("PNP0C02")) + + Name(BUF0, ResourceTemplate() + { + // PCI Express BAR _BAS and _LEN. + Memory32Fixed(ReadOnly, 0, 0, PCIX) + }) + + Method(_CRS, 0, NotSerialized) { + CreateDwordField(BUF0, ^PCIX._BAS, PCXB) + CreateDwordField(BUF0, ^PCIX._LEN, PCXL) + + Store(\PCBA, PCXB) + Subtract(\PCBL, \PCBA, Local0) + Add(Local0, 1, Local0) + Store(Local0, PCXL) + + Return (BUF0) + } + } + + // GPP0 (Bus 0 Dev 1 Fn 1) + Device(GPP0) + { + Name(_ADR, 0x00010001) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR01) // NB IOAPIC Enabled + } Else { + Return(AR01) // NB IOAPIC Disabled + } + } Else { + Return (PR01) // PIC mode + } + } + } + + // GPP1 (Bus 0 Dev 1 Fn 2) + Device(GPP1) + { + Name(_ADR, 0x00010002) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR02) // NB IOAPIC Enabled + } Else { + Return(AR02) // NB IOAPIC Disabled + } + } Else { + Return (PR02) // PIC mode + } + } + } + + // GPP2 (Bus 0 Dev 1 Fn 3) + Device(GPP2) + { + Name(_ADR, 0x00010003) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR03) // NB IOAPIC Enabled + } Else { + Return(AR03) // NB IOAPIC Disabled + } + } Else { + Return (PR03) // PIC mode + } + } + } + + // GPP3 (Bus 0 Dev 1 Fn 4) + Device(GPP3) + { + Name(_ADR, 0x00010004) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR04) // NB IOAPIC Enabled + } Else { + Return(AR04) // NB IOAPIC Disabled + } + } Else { + Return (PR04) // PIC mode + } + } + } + + // GPP4 (Bus 0 Dev 1 Fn 5) + Device(GPP4) + { + Name(_ADR, 0x00010005) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR05) // NB IOAPIC Enabled + } Else { + Return(AR05) // NB IOAPIC Disabled + } + } Else { + Return (PR05) // PIC mode + } + } + } + + // GPP5 (Bus 0 Dev 1 Fn 6) + Device(GPP5) + { + Name(_ADR, 0x00010006) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR06) // NB IOAPIC Enabled + } Else { + Return(AR06) // NB IOAPIC Disabled + } + } Else { + Return (PR06) // PIC mode + } + } + } + + // GPP6 (Bus 0 Dev 1 Fn 7) + Device(GPP6) + { + Name(_ADR, 0x00010007) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR07) // NB IOAPIC Enabled + } Else { + Return(AR07) // NB IOAPIC Disabled + } + } Else { + Return (PR07) // PIC mode + } + } + } + + // GP17 (Bus 0 Dev 8 Fn 1) + Device(GP17) + { + Name(_ADR, 0x00080001) + Name(_PRW, Package() {0x19, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR17) // NB IOAPIC Enabled + } Else { + Return(AR17) // NB IOAPIC Disabled + } + } Else { + Return (PR17) // PIC mode + } + } + + // Bus A Dev 0 Fn 0 - Internal GPU + Device(VGA) + { + Name(_ADR, 0x00000000) + } + // Bus A Dev 0 Fn 1 - Display HD Audio Controller + Device(DHDA) + { + Name(_ADR, 0x00000001) + } + // Bus A Dev 0 Fn 2 - Cryptographic Coprocessor + Device(PCCP) + { + Name(_ADR, 0x00000002) + } + // Bus A Dev 0 Fn 3 - USB 3.1 DRD + Device(DRD0) + { + Name(_ADR, 0x00000003) + Name(_PRW, Package() {0x19, 4}) + } + // Bus A Dev 0 Fn 4 - USB 3.1 + Device(XHC1) + { + Name(_ADR, 0x00000004) + Name(_PRW, Package() {0x19, 4}) + Name(_S0W, 3) + + Device(RHUB) + { + Name(_ADR, 0x00000000) + + // HS port 0 (J5 USB-A) + Device(PRT1) { + Name(_ADR, 0x00000001) + + Name(UPC1, Package(4) { 0xFF, 0x03, 0x00000000, 0x00000000 } )= //USB 3 Standard-A connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + + Name (_PLD, Package (0x01) // _PLD: Physical Location of Devi= ce + { + Buffer(0x14) { + 0x82, // Revision 2, Ignore color; + 0x00, 0x00, 0x00, // 24-bit RGB value for the color = of the device; + 0x00, 0x00, 0x00, 0x00, // Width & Height; + 0x11, 0x0C, 0x80, 0x00, //User visible, Group Token =3D0; + // Group Position 1st; + 0x01, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF // Reserve + } + }) + } + + // HS port 1 (J33 WWAN) + Device(PRT2) { + Name(_ADR, 0x00000002) + + Name(UPC1, Package(4) { 0x00, 0xFF, 0x00000000, 0x00000000 } )= //Proprietary connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + } + + // HS port 2 (U138 WWLAN_EVB) + Device(PRT3) { + Name(_ADR, 0x00000003) + + Name(UPC1, Package(4) { 0x00, 0xFF, 0x00000000, 0x00000000 } )= //Proprietary connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + } + + // HS port 3 (J2 WLAN) + Device(PRT4) { + Name(_ADR, 0x00000004) + + Name(UPC1, Package(4) { 0x00, 0xFF, 0x00000000, 0x00000000 } )= //Proprietary connector + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + } + + // HS port 4 (J29 Bottom) + Device(PRT5) { + Name(_ADR, 0x00000005) + + Name(UPC1, Package(4) { 0xFF, 0x00, 0x00000000, 0x00000000 } )= //Standard-A connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + + Name(PLD1, Package(1) { + Buffer (0x14) + { + } + }) + + Method (_PLD,0,Serialized) + { + Return (PLD1) + } + } + + // HS port 5 (J29 Top) + Device(PRT6) { + Name(_ADR, 0x00000006) + + Name(UPC1, Package(4) { 0xFF, 0x03, 0x00000000, 0x00000000 } )= //USB 3 Standard-A connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + + Name(PLD1, Package() { + Buffer (0x14) + { + } + }) + + Method (_PLD,0,Serialized) + { + Return (PLD1) + } + } + + // SS port 1 (J5 USB-A) + Device(PRT7) { + Name(_ADR, 0x00000007) + + Name(UPC1, Package(4) { 0xFF, 0x03, 0x00000000, 0x00000000 } )= //Standard-A + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + + Name (_PLD, Package (0x01) // _PLD: Physical Location of Devi= ce + { + Buffer(0x14) { + 0x82, // Revision 2, Ignore color; + 0x00, 0x00, 0x00, // 24-bit RGB value for the color = of the device; + 0x00, 0x00, 0x00, 0x00, // Width & Height; + 0x11, 0x0C, 0x80, 0x00, //User visible, Group Token =3D0; + // Group Position 1st; + 0x01, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF // Reserve + } + }) + } + + // SS port 2 (J33 WWAN) + Device(PRT8) { + Name(_ADR, 0x00000008) + + Name(UPC1, Package(4) { 0x00, 0xFF, 0x00000000, 0x00000000 } )= //Proprietary connector + + Method (_UPC,0,Serialized) + { + Return (UPC1) + } + } + } + } + // Bus A Dev 0 Fn 5 - Audio Processor + Device(ACP) + { + Name(_ADR, 0x00000005) + } + // Bus A Dev 0 Fn 6 - Audio Processor - HD Audio Controller + Device(AZAL) + { + Name(_ADR, 0x00000006) + } + // Bus A Dev 0 Fn 7 - (Non) Sensor Fusion Hub + Device(NSFH) + { + Name(_ADR, 0x00000007) + } + } + + // GP18 (Bus 0 Dev 8 Fn 2) + Device(GP18) + { + Name(_ADR, 0x00080002) + Name(_PRW, Package() {0x8, 4}) + + Method(_PRT, 0) { + If(PICM) { + If (\NAPC) { + Return(NR18) // NB IOAPIC Enabled + } Else { + Return(AR18) // NB IOAPIC Disabled + } + } Else { + Return (PR18) // PIC mode + } + } + + // Bus B Dev 0 Fn 0 - SATA + Device(SATA) + { + Name(_ADR, 0x00000000) + } + } + include("Lpc0.asl") + + } // end PCI0 Bridge "Host Bridge" +} // end _SB scope diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/Platform.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables= /Dsdt/Platform.asl new file mode 100644 index 0000000000..f9d98258e3 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/Platf= orm.asl @@ -0,0 +1,135 @@ +// /** @file +// Acpi Platform.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +// +// Create a Global MUTEX. +// +Mutex(MUTX, 0) + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 =3D 8259 +// 1 =3D IOAPIC +Method(\_PIC, 1) +{ + Store(Arg0, PICM) +} + +// Prepare to sleep +Method(_PTS, 1) +{ + // DEBUG INFO + Or(Arg0, 0x50, Local0) // 5x means enter Sx state + Store(Local0, \_SB.P80H) + + // Todo for System Specific +} + +// System Wake +Method(_WAK, 1) +{ + // Debug Info + Or(Arg0, 0xE0, Local0) // Ex means exit Sx state + Store(Local0, \_SB.P80H) + + If (LEqual(ARG0, 0x03)) { + Notify (\_SB.PWRB, 0x2) + } + Return (Package () {0x00, 0x00}) // Should return a Package containing t= wo Integers containing status and the power supply S-state +} + +// +// System Bus +// +Scope(\_SB) +{ + Scope(PCI0) + { + Method(_INI, 0) + { + // Check for a specific OS which supports _OSI. + If(CondRefOf(\_OSI, Local0)) + { + // Use OSYS for Windows Compatibility. + If(\_OSI("Windows 2009")) // Windows 7 or Windows Server 2008 R2 + { + } + If(\_OSI("Windows 2012")) // Windows 8 or Windows Server 2012 + { + } + If(\_OSI("Windows 2013")) //Windows Blue + { + } + If(\_OSI("Windows 2015")) //Windows 10 + { + } + If (\_OSI("Linux")) //Linux + { + } + } + } + + Method(NHPG, 0, Serialized) + { + } + + Method(NPME, 0, Serialized) + { + } + } // end Scope(PCI0) + + // Power button + Device(PWRB) + { + Name(_HID, EISAID("PNP0C0C")) + Method(_STA, 0) + { // return status of device + Return(0x0B) + } + } //End of Device(PWRB) + + // SPI 1 controller that be connected to MCU (connect to PD controller). + Device(SPI1) + { + Name(_HID, "AMDI0062") + Name(_UID, Zero) + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0xFEC13000, 0x00000100) + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0x0000, "\\_SB.GP= IO", ,) {91} // AGPIO91 for MCU + }) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + // USBC port + Device(CON0) + { + Name(_ADR, Zero) + Name(_DSD, Package(){ + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package(){ + Package(){"usb-role-switch", \_SB.PCI0.GP17.DRD0}, + Package(){"power-role", "dual"}, + Package(){"data-role", "dual"}, + } + }) + } + } //End of Device(SPI1) + +} // end Scope(\_SB) + +Name(PICM, 0) // Global Name, returns current Interrupt controller mode;= updated from _PIC control method diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsd= t/_PR.asl b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt= /_PR.asl new file mode 100644 index 0000000000..d05434f9ab --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Dsdt/_PR.a= sl @@ -0,0 +1,36 @@ +// /** @file +// Acpi _PR.asl +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ +// +// Processor Objects +// +Scope(\_SB) { + Device(PLTF) { + Name(_HID, "ACPI0010") + Name(_CID, EISAID("PNP0A05")) + Name(_UID, 1) + + Device(C000) { Name(_HID, "ACPI0007") Name(_UID, 0x00) = } + Device(C001) { Name(_HID, "ACPI0007") Name(_UID, 0x01) = } + Device(C002) { Name(_HID, "ACPI0007") Name(_UID, 0x02) = } + Device(C003) { Name(_HID, "ACPI0007") Name(_UID, 0x03) = } + Device(C004) { Name(_HID, "ACPI0007") Name(_UID, 0x04) = } + Device(C005) { Name(_HID, "ACPI0007") Name(_UID, 0x05) = } + Device(C006) { Name(_HID, "ACPI0007") Name(_UID, 0x06) = } + Device(C007) { Name(_HID, "ACPI0007") Name(_UID, 0x07) = } + Device(C008) { Name(_HID, "ACPI0007") Name(_UID, 0x08) = } + Device(C009) { Name(_HID, "ACPI0007") Name(_UID, 0x09) = } + Device(C00A) { Name(_HID, "ACPI0007") Name(_UID, 0x0A) = } + Device(C00B) { Name(_HID, "ACPI0007") Name(_UID, 0x0B) = } + Device(C00C) { Name(_HID, "ACPI0007") Name(_UID, 0x0C) = } + Device(C00D) { Name(_HID, "ACPI0007") Name(_UID, 0x0D) = } + Device(C00E) { Name(_HID, "ACPI0007") Name(_UID, 0x0E) = } + Device(C00F) { Name(_HID, "ACPI0007") Name(_UID, 0x0F) = } + } +} + diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fac= s/Facs.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Facs/= Facs.h new file mode 100644 index 0000000000..daf97dd581 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Facs/Facs.= h @@ -0,0 +1,45 @@ +/** @file + Implements Facs.h + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +/* This file includes code originally published under the following licens= e. */ + +/** @file +This file describes the contents of the ACPI Firmware ACPI Control Structu= re (FACS) +. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi= 30.h +All changes to the FACS contents should be done in this file. + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD = License +which accompanies this distribution. The full text of the license may be = found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#ifndef _FACS_H_ +#define _FACS_H_ + +// +// Statements that include other files +// +#include + +// +// FACS Definitions +// +#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000 +#define EFI_ACPI_GLOBAL_LOCK 0x00000000 + +#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000 +#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000 + +#define EFI_ACPI_OSPM_FLAGS 0x00000000 + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fac= s/Facs50.aslc b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Facs/Facs50.aslc new file mode 100644 index 0000000000..810399a22a --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Facs/Facs5= 0.aslc @@ -0,0 +1,68 @@ +// /** @file +// Acpi Facs50.aslc +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ +// +// Statements that include other files +// +#include "Facs.h" + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS =3D { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // Signature 'FA= CS' + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // Legth + 0x00000000, // Hardware Sign= ature will be updated at runtime + EFI_ACPI_FIRMWARE_WAKING_VECTOR, // The 32-bit ad= dress field where OSPM puts its waking vector. + EFI_ACPI_GLOBAL_LOCK, + EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS, // Flags + EFI_ACPI_X_FIRMWARE_WAKING_VECTOR, // 64-bit physic= al address of OSPM=E2=80=99s Waking Vector. + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, + { // Reserved0[3] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + EFI_ACPI_OSPM_FLAGS, // OspmFlags + { // Reserved1[24] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&FACS; +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fad= t/Fadt.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fadt/= Fadt.h new file mode 100644 index 0000000000..968a4b0fa5 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fadt/Fadt.= h @@ -0,0 +1,65 @@ +/** @file + Implements Fadt.h + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FADT_H_ +#define _FADT_H_ + +// +// Statements that include other files +// +#include + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'A','M','D',' ',' ',' ' // OEMID 6 byt= es long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('E','D','K','2',' ',' ',' '= ,' ') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32(' ',' ',' ',' ') +#define EFI_ACPI_CREATOR_REVISION 0x01000013 + +// +// FADT Definitions +// +#define SCI_INT_VECTOR 0x0009 +#define SMI_CMD_IO_PORT 0x000000B0 // SMI Port 0xB0 +#define ACPI_ENABLE 0x0A0 +#define ACPI_DISABLE 0x0A1 + +#define PM1a_EVT_BLK 0x00000400 +#define PM1b_EVT_BLK 0x00000000 +#define PM1a_CNT_BLK 0x00000404 +#define PM1b_CNT_BLK 0x00000000 +#define PM2_CNT_BLK 0x00000800 +#define PM_TMR_BLK 0x00000408 +#define GPE0_BLK 0x00000420 +#define GPE1_BLK 0x00000000 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x01 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x08 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 + +#define RESERVED 0x00 +#define P_LVL2_LAT 0x0064 +#define P_LVL3_LAT 0x03e9 +#define FLUSH_SIZE 0x0000 +#define FLUSH_STRIDE 0x0000 +#define DUTY_OFFSET 0x01 +#define DUTY_WIDTH 0x03 +#define DAY_ALRM 0x0D +#define MON_ALRM 0x00 +#define CENTURY 0x00 +#define IAPC_BOOT_ARCH EFI_ACPI_2_0_LEGACY_DEVICES +//#define FLAG (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EF= I_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4) +#define FLAG 0x0000C5AD +#define FLAG2 (EFI_ACPI_2_0_WBINVD | EFI_ACPI_2_0_PROC_C1 | EFI_= ACPI_2_0_PWR_BUTTON | EFI_ACPI_2_0_SLP_BUTTON | EFI_ACPI_2_0_RTC_S4 | EFI_A= CPI_2_0_RESET_REG_SUP | EFI_ACPI_3_0_USE_PLATFORM_CLOCK) + + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fad= t/Fadt50.aslc b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Fadt/Fadt50.aslc new file mode 100644 index 0000000000..0d51e9f7a7 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Fadt/Fadt5= 0.aslc @@ -0,0 +1,159 @@ +// /** @file +// Acpi Fadt50.aslc +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#include + +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FADT =3D { + { // EFI_ACPI_DESCRIPTION_HEADER + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, // UINT32, Sig= nature 'FACP' + sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE), // UINT32, Leg= th + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, // UINT8, Revi= sion + 0, // UINT8, to m= ake sum of entire table =3D=3D 0 + {EFI_ACPI_OEM_ID}, // UINT8[6], OEM identification + EFI_ACPI_OEM_TABLE_ID, // UINT64, OEM table identification + EFI_ACPI_OEM_REVISION, // UINT32, OEM revision number + EFI_ACPI_CREATOR_ID, // UINT32, ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION, // UINT32, ASL compiler revision num= ber + }, + 0, // UINT32, Physical addesss of FACS + 0, // UINT32, Physical address of DSDT + RESERVED, // Reserved + EFI_ACPI_5_0_PM_PROFILE_MOBILE, // Preferred Power Management Profile + + SCI_INT_VECTOR, // UINT16, System vector of SCI inte= rrupt + SMI_CMD_IO_PORT, // UINT32, Port address of SMI comma= nd port + ACPI_ENABLE, // Value to write to port smi_cmd to= enable ACPI + ACPI_DISABLE, // Value to write to port smi_cmd to= disable ACPI + 0, // Value to write to SMI CMD port to= enter the S4BIOS state + 0, // PSTATE_CNT, + + PM1a_EVT_BLK, // Port address of Power Mgt 1a Even= t Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Even= t Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl= Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl= Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl= Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer C= trl Reg Blk + GPE0_BLK, // Port addr of General Purpose Even= t 0 Reg Blk + GPE1_BLK, // Port addr of General Purpose Even= t 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_= blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_= blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_b= lk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // Offset in gpe model where gpe1 ev= ents start + 0, // CST_CNT, + P_LVL2_LAT, // Worst case HW latency to enter/ex= it C2 state + P_LVL3_LAT, // Worst case HW latency to enter/ex= it C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // Bit location of duty cycle field = in p_cnt reg + DUTY_WIDTH, // Bit width of duty cycle field in = p_cnt reg + DAY_ALRM, // Index to day-of-month alarm in RT= C CMOS RAM + MON_ALRM, // Index to month-of-year alarm in R= TC CMOS RAM + CENTURY, // Index to century in RTC CMOS RAM + 0, // IAPC_Boot_Arch + RESERVED, // Reserved + FLAG, // UINT32, 0x0000C5AD + + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE ResetReg + EFI_ACPI_5_0_SYSTEM_IO, + 0x8, + 0, + EFI_ACPI_5_0_BYTE, + 0xCF9 + }, + 0x06, // UINT8, ResetValue + {0x00,0x00,0x00}, // Reserved2[3] + 0, // UINT64, XFirmwareCtrl + 0, // UINT64, XDsdt + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPm1aEvtBlk + EFI_ACPI_5_0_SYSTEM_IO, + (PM1_EVT_LEN * 8), + 0, + EFI_ACPI_5_0_DWORD, + PM1a_EVT_BLK + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPm1bEvtBlk + 0, + 0, + 0, + 0, + 0 + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPm1aCntBlk + EFI_ACPI_5_0_SYSTEM_IO, + (PM1_CNT_LEN * 8), + 0, + EFI_ACPI_5_0_WORD, + PM1a_CNT_BLK + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPm1bCntBlk + 0, + 0, + 0, + 0, + 0 + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPm2CntBlk + EFI_ACPI_5_0_SYSTEM_IO, + (PM2_CNT_LEN * 8), + 0, + EFI_ACPI_5_0_BYTE, + PM2_CNT_BLK + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XPmTmrBlk + EFI_ACPI_5_0_SYSTEM_IO, + (PM_TM_LEN * 8), + 0, + EFI_ACPI_5_0_DWORD, + PM_TMR_BLK + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XGpe0Blk + EFI_ACPI_5_0_SYSTEM_IO, + (GPE0_BLK_LEN * 8), + 0, + EFI_ACPI_5_0_QWORD, + GPE0_BLK + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE XGpe1Blk + 0, + 0, + 0, + 0, + 0 + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE SleepControlReg + 0, + 0, + 0, + 0, + 0 + }, + { // EFI_ACPI_5_0_GENERIC_ADDRESS_STRU= CTURE SleepStatusReg + 0, + 0, + 0, + 0, + 0 + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&FADT; +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Hpe= t/Hpet.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Hpet/= Hpet.h new file mode 100644 index 0000000000..e28a473f39 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Hpet/Hpet.= h @@ -0,0 +1,71 @@ +/** @file + Implements Hpet.h + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HPET_H_ +#define _HPET_H_ + +// +// Statements that include other files +// +#include + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'A','M','D',' ',' ',' ' // OEMID 6 byt= es long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('E','D','K','2',' ',' ',' '= ,' ') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32(' ',' ',' ',' ') +#define EFI_ACPI_CREATOR_REVISION 0x01000013 + + +// +// HPET structure +// +#define EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION 0x00 + +#define EFI_ACPI_5_0_HPET_EVENT_TIMER_BLOCK_ID 0x10228201 + // [31:16] 0x1022 - PCI Ve= ndor ID of 1st Timer Block + // [15] 0x01 - Legacy R= eplacement IRQ Routing Capable + // [14] 0x00 - Reserved + // [13] 0x00 - COUNT_SI= ZE_CAP counter size + // [12:08] 0x02 - Number o= f Comparators in 1st Timer Block + // [07:00] 0x01 - Hardware= Rev ID +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_SPACE_ID 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_WIDTH 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_OFFSET 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_LOWER_32BIT 0xFED00000 +#define EFI_ACPI_5_0_HPET_NUMBER 0x00 +#define EFI_ACPI_5_0_HPET_MIN_CLOCK_TICK 0x0080 +#define EFI_ACPI_5_0_HPET_PAGE_PROTECTION_AND_ATTRIBUTE 0x00 + +// +// Ensure proper structure formats +// +#pragma pack (1) +// +// ACPI 5.0 Table structure +// +typedef struct { + // ACPI Common header + EFI_ACPI_DESCRIPTION_HEADER Header; + // HPET + UINT32 EventTimerBlockID; // Offset 0x= 24 + UINT8 BaseAddress_SpaceID; + UINT8 BaseAddress_RegisterBitWidth; + UINT8 BaseAddress_RegisterBitOffset; + UINT8 Reserved0[1]; + UINT32 BaseAddressLower32bit; // Offset 0x= 28 + UINT32 Reserved1[1]; + UINT8 HpetNumber; // Offset 0x= 34 + UINT16 MinClockTick; // Offset 0x= 35 + UINT8 PageProtectionAndOemAttribute;// Offset 0x= 37 +} EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE; + +#pragma pack () + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Hpe= t/Hpet50.aslc b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Hpet/Hpet50.aslc new file mode 100644 index 0000000000..0284a88b5a --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Hpet/Hpet5= 0.aslc @@ -0,0 +1,58 @@ +// /** @file +// Acpi Hpet50.aslc +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +// +// Statements that include other files +// +#include "Hpet.h" + +EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE Hpet =3D { + { // EFI_ACPI_DESCRIPTION_HEADER + EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, // UINT32,= Signature 'HPET' + sizeof (EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE), // UINT32,= Legth + EFI_ACPI_5_0_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, // UINT8, = Revision + 0, // UINT8, to make sum of entire tabl= e =3D=3D 0 + {EFI_ACPI_OEM_ID}, // UINT8[6], OEM identification + EFI_ACPI_OEM_TABLE_ID, // UINT64, OEM table identification + EFI_ACPI_OEM_REVISION, // UINT32, OEM revision number + EFI_ACPI_CREATOR_ID, // UINT32, ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION, // UINT32, ASL compiler revision num= ber + }, + + EFI_ACPI_5_0_HPET_EVENT_TIMER_BLOCK_ID, // Event Timer Block= ID + EFI_ACPI_5_0_HPET_BASE_ADDRESS_SPACE_ID, // + EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_WIDTH, // + EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_OFFSET, // + {0x00}, // Reserved0[1] + EFI_ACPI_5_0_HPET_BASE_ADDRESS_LOWER_32BIT, // BASE_ADDRESS Lowe= r 32-bit + {0x00000000}, // Reserved1[1] + EFI_ACPI_5_0_HPET_NUMBER, // HPET Timer + EFI_ACPI_5_0_HPET_MIN_CLOCK_TICK, // Main Counter Mini= mum Clock_tick Periodic Mode + EFI_ACPI_5_0_HPET_PAGE_PROTECTION_AND_ATTRIBUTE // Page Preotection = And OEM Attribute +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&Hpet; +} + +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_SPACE_ID 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_WIDTH 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_REGISTER_BIT_OFFSET 0x00 +#define EFI_ACPI_5_0_HPET_BASE_ADDRESS_LOWER_32BIT 0xFED00000 +#define EFI_ACPI_5_0_HPET_NUMBER 0x00 +#define EFI_ACPI_5_0_HPET_MIN_CLOCK_TICK 0x0080 +#define EFI_ACPI_5_0_HPET_PAGE_PROTECTION_AND_ATTRIBUTE 0x00 diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mad= t/Madt.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Madt/= Madt.h new file mode 100644 index 0000000000..cd3e965142 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Madt/Madt.= h @@ -0,0 +1,138 @@ +/** @file + Implements Madt.h + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +/* This file includes code originally published under the following licens= e. */ + +/*++ + +Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble under + the terms and conditions of the BSD License that accompanies this distri= bution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + +Module Name: + + Madt.h + +Abstract: + + This file describes the contents of the ACPI Multiple APIC Description + Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + To make changes to the MADT, it is necessary to update the count for the + APIC structure being updated, and to modify table found in Madt.c. + +--*/ + +#ifndef _MADT_H_ +#define _MADT_H_ + +// +// Statements that include other files +// +#include +//#include +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'A','M','D',' ',' ',' ' // OEMID 6 byt= es long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('E','D','K','2',' ',' ',' '= ,' ') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32(' ',' ',' ',' ') +#define EFI_ACPI_CREATOR_REVISION 0x01000013 + +// +// Local APIC address +// +#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000 +//#define EFI_IO_APIC_ADDRESS 0xFEC00000 + +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_5_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_5_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// + + +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 16 + +#define EFI_ACPI_IO_APIC_COUNT 2 + +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 + +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 16 + +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +// +// MADT structure +// + +// +// Ensure proper structure formats +// +#pragma pack (1) +// +// ACPI 5.0 Table structure +// +typedef struct { + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI= _PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_5_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO= _APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTER= RUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI= _NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_A= CPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[= EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_5_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_I= O_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACP= I_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptS= ources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mad= t/Madt50.aslc b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Madt/Madt50.aslc new file mode 100644 index 0000000000..8d3c0de37d --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Madt/Madt5= 0.aslc @@ -0,0 +1,327 @@ +// /** @file +// Acpi Madt50.aslc +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +// +// Statements that include other files +// +#include "Madt.h" + +EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { +{ + { + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE), + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + + {EFI_ACPI_OEM_ID}, // UINT8[6], OEM identification + EFI_ACPI_OEM_TABLE_ID, // UINT64, OEM table identification + EFI_ACPI_OEM_REVISION, // UINT32, OEM revision number + EFI_ACPI_CREATOR_ID, // UINT32, ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // UINT32, ASL compiler revision num= ber + }, + // + // MADT specific fields + // + EFI_ACPI_LOCAL_APIC_ADDRESS, + EFI_ACPI_5_0_MULTIPLE_APIC_FLAGS +}, +{ + // + // Processor Local APIC Structure + // + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x00, // Processor= ID + 0x00, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor= ID + 0x01, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x02, // Processor= ID + 0x02, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x03, // Processor= ID + 0x03, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x04, // Processor= ID + 0x04, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x05, // Processor= ID + 0x05, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x06, // Processor= ID + 0x06, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x07, // Processor= ID + 0x07, // Local API= C ID + 0x00000001 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x08, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x09, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0A, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0B, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0C, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0D, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0E, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + }, + { + EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x0F, // Processor= ID + 0x00, // Local API= C ID + 0x00000000 // Flags - D= isabled (until initialized by platform driver) + } +}, +{ + // + // I/O SAPIC + // + { + EFI_ACPI_5_0_IO_APIC, // Type + sizeof (EFI_ACPI_5_0_IO_APIC_STRUCTURE), // Length + 0x21, // IO APIC I= D + EFI_ACPI_RESERVED_BYTE, // Reserved + 0xFEC00000, // IO APIC A= ddress (physical) + 0x00000000 // Global Sy= stem Interrupt Base + }, + { + EFI_ACPI_5_0_IO_APIC, // Type + sizeof (EFI_ACPI_5_0_IO_APIC_STRUCTURE), // Length + 0x22, // IO APIC I= D + EFI_ACPI_RESERVED_BYTE, // Reserved + 0xFEC01000, // IO APIC A= ddress (physical) + 0x00000018 // Global Sy= stem Interrupt Base + } +}, +{ + { + // + // IRQ0=3D>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE, // Type + sizeof (EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + 0x00, // Bus - ISA + 0x00, // Source - = IRQ0 + 0x00000002, // Global Sy= stem Interrupt - IRQ2 + 0x0000 // Flags - C= onforms to specifications of the bus + }, + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + { + EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE, // Type + sizeof (EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + 0x00, // Bus - ISA + 0x09, // Source - = IRQ0 + 0x00000009, // Global Sy= stem Interrupt - IRQ2 + 0x000F // Flags - L= evel-tiggered, Active High + } +}, +{ + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x00, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x01, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x02, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x03, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x04, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x05, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x06, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x07, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x08, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x09, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0A, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0B, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0C, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0D, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0E, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + }, + { + EFI_ACPI_5_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x0F, // ACPI Proc= essor ID + 0x0005, // Flags - L= evel-tiggered, Active High + 0x01 // Local API= C LINT# + } +} +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&Madt; +} + diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mcf= g/Mcfg.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mcfg/= Mcfg.h new file mode 100644 index 0000000000..045a84fe91 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.= h @@ -0,0 +1,75 @@ +/** @file + Implements Mcfg.h + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +/* This file includes code originally published under the following licens= e. */ + +/** @file +This file describes the contents of the ACPI Memory Mapped Configuration +Space Access Table (MCFG). Some additional ACPI values are defined in Acp= i10.h, +Acpi20.h, and Acpi30.h. + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD = License +which accompanies this distribution. The full text of the license may be = found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// +#include +#include + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'A','M','D',' ',' ',' ' // OEMID 6 byt= es long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('E','D','K','2',' ',' ',' '= ,' ') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000002 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32(' ',' ',' ',' ') +#define EFI_ACPI_CREATOR_REVISION 0x01000013 + +// +// MCFG Definitions +// + +// +// Define the number of allocation structures so that we can build the tab= le structure. +// +#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 1 + +// +// MCFG structure +// + +// +// Ensure proper structure formats +// +#pragma pack (1) + +// +// MCFG Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER = Header; + UINT64 = Reserved; + #if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOC= ATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT]; + #endif +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +#pragma pack () + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mcf= g/Mcfg50.aslc b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/= Mcfg/Mcfg50.aslc new file mode 100644 index 0000000000..ab5144db13 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg5= 0.aslc @@ -0,0 +1,61 @@ +// /** @file +// Acpi Mcfg50.aslc +// +// Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +// +// Statements that include other files +// +#include "Mcfg.h" + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = =3D { + { + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRES= S_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_= TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + + {EFI_ACPI_OEM_ID}, // UINT8[6], OEM identification + EFI_ACPI_OEM_TABLE_ID, // UINT64, OEM table identification + EFI_ACPI_OEM_REVISION, // UINT32, OEM revision number + EFI_ACPI_CREATOR_ID, // UINT32, ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION, // UINT32, ASL compiler revision num= ber + }, + + // + // Reserved + // + 0x0000000000000000, + + // + // MCFG specific fields + // + { + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // BaseAddress + 0x0000, // PciSegmentGroupNumber + 0x00, // StartBusNumber + 0xFF, // EndBusNumber + 0x00000000 // Reserved + } + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&Mcfg; +} -- 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114051): https://edk2.groups.io/g/devel/message/114051 Mute This Topic: https://groups.io/mt/103831163/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-