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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C X-Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1PEPF000044F4.mail.protection.outlook.com (10.167.241.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Thu, 18 Jan 2024 06:52:52 +0000 X-Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 18 Jan 2024 00:52:49 -0600 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Thu, 18 Jan 2024 00:52:48 -0600 From: "duke.zhai via groups.io" To: CC: Eric Xing , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH 31/33] AMD/VanGoghBoard: Check in AMD SmmControlPei module Date: Thu, 18 Jan 2024 14:50:44 +0800 Message-ID: <20240118065046.961-32-duke.zhai@amd.com> In-Reply-To: <20240118065046.961-1-duke.zhai@amd.com> References: <20240118065046.961-1-duke.zhai@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F4:EE_|DM4PR12MB6303:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b34ad00-fd5a-41a1-ed4e-08dc17f2179d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: jLATWy+mrrvwyuNeuujiyUjZdPZT0Pu3TwsOXEjlK/GcDAwM9aO9uv/r3K8Rn1TMhJYY+5cXQxtLX3douLfs8QWB9y0UXA6m3G/WfTmhcL6//xXZenTQFZTk02FH0hIT2R5EVH4oN1Z3/5TFw+6AP6y+YhUlstkI3WLeMPBTZUg5ghtyQ2+Ia89DMe4+80c1CxkXb5FsQaPzg0nD34aPcHDJX5Cwnv3NmwGhH2fjuWU2zQ6Gwu3O7/fjupR450Mpnjy93cw0rQo5SqZJlU18bOwUxRqeklcbs7ZfxOf+gLF6z70wlJit0LTuugOTgDmuJt4yYJmN8/Lm7hqqZ+lxEJY4irT5Uhy8wUQSSRTBvJVUCbsbLby/KB5rDn0yjBMET0iiqAzNeTHAUD3H4c3NaBwWtHrpliK95ukiQQBLdpvWvtwjLhQ6b/JEvVe8BVXH8GyaC9rF19s9kbk8v9WjYzVNbBLP22IiXhShIq7h72VDaq7UvhiQ0EjSx9vfqtuPvIWhgxWHjvS4btAIczpNtHx/orjfNpdBhK1/Bifi5K5JDTsP3/O7NvgP070Lz3d2wMvsQMR2lcRReIRbICoP40UmimRxymlUz9/Oi03MJJY/yNBYGRJ8mjiFC80U0Y07J3pH85liJfzlntqhYDe+F1hBqRUmXVgF1t8m0ATalyxuQQKdAiB9dxTEL5BpJpisHOE+EA6l9OflFdnIE1vjn3jILB/C6hUfoCJpcbCkRj80glCnJyq31oEgpaVVCjPN8id4ZF7LrB1X0W18NT+Tfw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2024 06:52:52.4111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b34ad00-fd5a-41a1-ed4e-08dc17f2179d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6303 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: scs0JFKbEqL2bxzm0LMBpYbqx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=b2N2+JpD; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Duke Zhai BZ #:4640 Initial AMD SmmControlPei module in Silicon folder. This module initializes SMM-related registers, and installs gPeiSmmControlP= pi. Signed-off-by: Duke Zhai Cc: Eric Xing Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Smm/SmmControlPei/SmmControlPei.c | 307 ++++++++++++++++++ .../Smm/SmmControlPei/SmmControlPei.inf | 40 +++ 2 files changed, 347 insertions(+) create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPe= i.c create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPe= i.inf diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c b/S= ilicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c new file mode 100644 index 0000000000..4752aede9c --- /dev/null +++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c @@ -0,0 +1,307 @@ +/** @file + Implements SmmControlPei.c + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + This routine generates an SMI + + @param[in] PeiServices Describes the list of possible PE= I Services. + @param[in] This The pointer to this instance of t= his PPI. + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic TRUE to indicate a periodical SMI + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI_SUCCESS SMI generated. + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +PeiTrigger ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + Clear SMI related chipset status. + + @param[in] PeiServices Describes the list of possible PEI Ser= vices. + @param[in] This The pointer to this instance of this P= PI. + @param[in] Periodic TRUE to indicate a periodical SMI. + + @return Return value from ClearSmi() +**/ +EFI_STATUS +EFIAPI +PeiClear ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ); + +STATIC PEI_SMM_CONTROL_PPI mSmmControlPpi =3D { + PeiTrigger, + PeiClear +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiSmmControlPpiGuid, + &mSmmControlPpi +}; + +/** + Init related registers + + @param [in] None + + @retval EFI_LOAD_ERROR Get ACPI MMIO base error. + @retval EFI_SUCCESS The function completed successfully.. +*/ +EFI_STATUS +SmmControlPeiPreInit ( + VOID + ) +{ + UINT16 SmmControlData16; + UINT16 SmmControlMask16; + UINT32 SmmControlData32; + UINT8 SmmControlIndex; + UINT16 AcpiPmBase; + + // + // Get ACPI MMIO base and AcpiPm1EvtBlk address + // + AcpiPmBase =3D MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60)= ; + + if (0 =3D=3D AcpiPmBase) { + return EFI_LOAD_ERROR; + } + + // + // Clean up all SMI status and enable bits + // + // Clear all SmiControl registers + SmmControlData32 =3D 0; + for (SmmControlIndex =3D FCH_SMI_REGA0; SmmControlIndex <=3D FCH_SMI_REG= C4; SmmControlIndex +=3D 4) { + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + SmmControlIndex, SmmControlDa= ta32); + } + + // Clear all SmiStatus registers (SmiStatus0-4) + SmmControlData32 =3D 0xFFFFFFFF; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG80, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG84, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG8C, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG90, SmmControlData32= ); + + // + // If SCI is not enabled, clean up all ACPI PM status/enable registers + // + SmmControlData16 =3D IoRead16 (AcpiPmBase + R_FCH_ACPI_PM_CONTROL); + if (!(SmmControlData16 & BIT0)) { + // Clear WAKE_EN, RTC_EN, SLPBTN_EN, GBL_EN and TMR_EN + SmmControlData16 =3D 0; + SmmControlMask16 =3D (UINT16) ~(BIT15 + BIT10 + BIT9 + BIT5 + BIT0); + IoAndThenOr16 (AcpiPmBase + R_FCH_ACPI_PM1_ENABLE, SmmControlMask16, S= mmControlData16); + + // Clear WAKE_STS, RTC_STS, SLPBTN_STS, GBL_STS and TMR_STS + SmmControlData16 =3D BIT15 + BIT10 + BIT9 + BIT5 + BIT0; + IoWrite16 (AcpiPmBase + R_FCH_ACPI_PM1_STATUS, SmmControlData16); + } + + // + // Set the EOS Bit + // Clear SmiEnB to enable SMI function + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= G98); + SmmControlData32 |=3D BIT28; + SmmControlData32 &=3D ~BIT31; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98, SmmControlData32= ); + + // + // Enable CmdPort SMI + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= GB0); + SmmControlData32 &=3D ~(BIT22 + BIT23); + SmmControlData32 |=3D BIT22; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, SmmControlData32= ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully +**/ +EFI_STATUS +ClearSmi ( + VOID + ) +{ + UINT32 SmmControlData32; + + // + // Clear SmiCmdPort Status Bit + // + SmmControlData32 =3D BIT11; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32= ); + + // + // Set the EOS Bit if it is currently cleared so we can get an SMI other= wise + // leave the register alone + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG= 98); + if ((SmmControlData32 & BIT28) =3D=3D 0) { + SmmControlData32 |=3D BIT28; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98, SmmControlData= 32); + } + + return EFI_SUCCESS; +} + +/** + This routine generates an SMI + + @param[in] PeiServices Describes the list of possible PE= I Services. + @param[in] This The pointer to this instance of t= his PPI. + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic TRUE to indicate a periodical SMI + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI_SUCCESS SMI generated. + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +PeiTrigger ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + UINT8 bIndex; + UINT8 bData; + UINT32 SmmControlData32; + UINT16 SmiCmdPort; + + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + if (NULL =3D=3D ArgumentBuffer) { + bIndex =3D 0xff; + } else { + bIndex =3D *ArgumentBuffer; + } + + if (NULL =3D=3D ArgumentBufferSize) { + bData =3D 0xff; + } else { + bData =3D (UINT8)*ArgumentBufferSize; + } + + // + // Enable CmdPort SMI + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= GB0); + SmmControlData32 &=3D ~(BIT22 + BIT23); + SmmControlData32 |=3D BIT22; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, SmmControlData32= ); + + SmiCmdPort =3D PcdGet16 (PcdAmdFchCfgSmiCmdPortAddr); + + // + // Issue command port SMI + // + IoWrite16 (SmiCmdPort, (bData << 8) + bIndex); + return EFI_SUCCESS; +} + +/** + Clear SMI related chipset status. + + @param[in] PeiServices Describes the list of possible PEI Ser= vices. + @param[in] This The pointer to this instance of this P= PI. + @param[in] Periodic TRUE to indicate a periodical SMI. + + @return Return value from ClearSmi() +**/ +EFI_STATUS +EFIAPI +PeiClear ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return ClearSmi (); +} + +/** + This is the constructor for the SMM Control Ppi. + + This function installs PEI_SMM_CONTROL_PPI. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_UNSUPPORTED There's no Intel ICH on this platform + @return The status returned from PeiServicesInstallPpi(). + +--*/ +EFI_STATUS +SmmControlPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "PeiSmmControl Enter\n")); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + return EFI_UNSUPPORTED; + } + + // + // Initialize EFI library + // + Status =3D SmmControlPeiPreInit (); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D PeiServicesInstallPpi (&mPpiList); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf b= /Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf new file mode 100644 index 0000000000..d6c984f02a --- /dev/null +++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf @@ -0,0 +1,40 @@ +## @file +# AMD Smm Contro lPei +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSmmControl + FILE_GUID =3D EC9519B1-E788-4C45-B695-244457442D64 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlPeiEntry + +[Sources.common] + SmmControlPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AgesaPublic/AgesaPublic.dec + +[LibraryClasses] + IoLib + DebugLib + PeiServicesLib + PeimEntryPoint + +[Guids] + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr ## CONSUME= S + +[Ppis] + gPeiSmmControlPpiGuid #PRODUCED + +[Depex] + gEfiPeiMasterBootModePpiGuid -- 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114078): https://edk2.groups.io/g/devel/message/114078 Mute This Topic: https://groups.io/mt/103831201/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-