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From: "Gerd Hoffmann" <kraxel@redhat.com>
To: devel@edk2.groups.io
Cc: Oliver Steffen <osteffen@redhat.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Gerd Hoffmann <kraxel@redhat.com>
Subject: [edk2-devel] [PATCH 1/1] MdeModulePkg/VirtualMemory: drop 5-level paging assert
Date: Wed, 24 Jan 2024 16:49:29 +0100	[thread overview]
Message-ID: <20240124154929.2146147-1-kraxel@redhat.com> (raw)

The ResetVector decides at runtime (depending in CPU capabilities)
whenever it uses 5-level paging or not.  Firmware builds with 5-level
paging enabled (PcdUse5LevelPageTable=TRUE) may run run in 4-level
paging mode.  The code handles that just fine, by looking at the la57
bit in cr4 instead of checking PcdUse5LevelPageTable.

The ASSERT is not correct, remove it.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 980c2002d4f5..575e396eeffd 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -745,7 +745,6 @@ CreateIdentityMappingPageTables (
     //
     Cr4.UintN         = AsmReadCr4 ();
     Page5LevelSupport = (Cr4.Bits.LA57 != 0);
-    ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport);
   } else {
     //
     // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.
-- 
2.43.0



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             reply	other threads:[~2024-01-24 15:49 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-24 15:49 Gerd Hoffmann [this message]
2024-01-24 16:37 ` [edk2-devel] [PATCH 1/1] MdeModulePkg/VirtualMemory: drop 5-level paging assert Laszlo Ersek

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