[edk2-devel] [PATCH v2 0/4] OvmfPkg/Sec: Setup MTRR early in the boot process.

[edk2-devel] [PATCH v2 0/4] OvmfPkg/Sec: Setup MTRR early in the boot process.

[Gerd Hoffmann]

Also add #defines for MTRR cache types to ArchitecturalMsr.h
and followup patches to use these #defines.

Gerd Hoffmann (4):
  OvmfPkg/Sec: Setup MTRR early in the boot process.
  MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types
  UefiCpuPkg/MtrrLib.h: use cache type #defines from ArchitecturalMsr.h
  OvmfPkg/Sec: use cache type #defines from ArchitecturalMsr.h

 .../Include/Register/Intel/ArchitecturalMsr.h |  7 ++++
 UefiCpuPkg/Include/Library/MtrrLib.h          | 14 ++++----
 OvmfPkg/IntelTdx/Sec/SecMain.c                | 32 +++++++++++++++++++
 OvmfPkg/Library/PlatformInitLib/MemDetect.c   | 10 +++---
 OvmfPkg/Sec/SecMain.c                         | 32 +++++++++++++++++++
 5 files changed, 84 insertions(+), 11 deletions(-)

-- 
2.43.0



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[edk2-devel] [PATCH v2 1/4] OvmfPkg/Sec: Setup MTRR early in the boot process.

[Gerd Hoffmann]

Specifically before running lzma uncompress of the main firmware volume.
This is needed to make sure caching is enabled, otherwise the uncompress
can be extremely slow.

Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes.

Background:  Depending on virtual machine configuration kvm may uses EPT
memory types to apply guest MTRR settings.  In case MTRRs are disabled
kvm will use the uncachable memory type for all mappings.  Here is the
linux kernel function handling this:

static u8 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
{
	/* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
	 * memory aliases with conflicting memory types and sometimes MCEs.
	 * We have to be careful as to what are honored and when.
	 *
	 * For MMIO, guest CD/MTRR are ignored.  The EPT memory type is set to
	 * UC.  The effective memory type is UC or WC depending on guest PAT.
	 * This was historically the source of MCEs and we want to be
	 * conservative.
	 *
	 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
	 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored.  The
	 * EPT memory type is set to WB.  The effective memory type is forced
	 * WB.
	 *
	 * Otherwise, we trust guest.  Guest CD/MTRR/PAT are all honored.  The
	 * EPT memory type is used to emulate guest CD/MTRR.
	 */

	if (is_mmio)
		return MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;

	if (!kvm_arch_has_noncoherent_dma(vcpu->kvm))
		return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT;

	if (kvm_read_cr0_bits(vcpu, X86_CR0_CD)) {
		if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
			return MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT;
		else
			return (MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT) |
				VMX_EPT_IPAT_BIT;
	}

	return kvm_mtrr_get_guest_memory_type(vcpu, gfn) << VMX_EPT_MT_EPTE_SHIFT;
}

In most VM configurations kvm_arch_has_noncoherent_dma() evaluate to
false, so kvm uses MTRR_TYPE_WRBACK.  In case the VM has a mdev device
assigned that is not the case though.

Before commit e8aa4c6546ad ("UefiCpuPkg/ResetVector: Cache Disable
should not be set by default in CR0") the function also ended up using
MTRR_TYPE_WRBACK thanks to KVM_X86_QUIRK_CD_NW_CLEARED.  After that
commit kvm actually evaluates mtrr settings via
kvm_mtrr_get_guest_memory_type().

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 OvmfPkg/IntelTdx/Sec/SecMain.c              | 32 +++++++++++++++++++++
 OvmfPkg/Library/PlatformInitLib/MemDetect.c | 10 +++----
 OvmfPkg/Sec/SecMain.c                       | 32 +++++++++++++++++++++
 3 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c b/OvmfPkg/IntelTdx/Sec/SecMain.c
index 42a587adfa57..e8ff0e9081d1 100644
--- a/OvmfPkg/IntelTdx/Sec/SecMain.c
+++ b/OvmfPkg/IntelTdx/Sec/SecMain.c
@@ -27,6 +27,8 @@
 #include <Library/TdxHelperLib.h>
 #include <Library/CcProbeLib.h>
 #include <Library/PeilessStartupLib.h>
+#include <Register/Intel/ArchitecturalMsr.h>
+#include <Register/Intel/Cpuid.h>
 
 #define SEC_IDT_ENTRY_COUNT  34
 
@@ -48,6 +50,31 @@ IA32_IDT_GATE_DESCRIPTOR  mIdtEntryTemplate = {
   }
 };
 
+//
+// Enable MTRR early, set default type to write back.
+// Needed to make sure caching is enabled,
+// without this lzma decompress can be very slow.
+//
+STATIC
+VOID
+SecMtrrSetup (
+  VOID
+  )
+{
+  CPUID_VERSION_INFO_EDX           Edx;
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;
+
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);
+  if (!Edx.Bits.MTRR) {
+    return;
+  }
+
+  DefType.Uint64    = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);;
+  DefType.Bits.Type = 6; /* write back */
+  DefType.Bits.E    = 1; /* enable */
+  AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
+}
+
 VOID
 EFIAPI
 SecCoreStartupWithStack (
@@ -204,6 +231,11 @@ SecCoreStartupWithStack (
   InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
   DisableApicTimerInterrupt ();
 
+  //
+  // Initialize MTRR
+  //
+  SecMtrrSetup ();
+
   PeilessStartup (&SecCoreData);
 
   ASSERT (FALSE);
diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index f042517bb64a..e89f63eee054 100644
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -1082,18 +1082,18 @@ PlatformQemuInitializeRam (
     MtrrGetAllMtrrs (&MtrrSettings);
 
     //
-    // MTRRs disabled, fixed MTRRs disabled, default type is uncached
+    // See SecMtrrSetup(), default type should be write back
     //
-    ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);
+    ASSERT ((MtrrSettings.MtrrDefType & BIT11) != 0);
     ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);
-    ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);
+    ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == MTRR_CACHE_WRITE_BACK);
 
     //
     // flip default type to writeback
     //
-    SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);
+    SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, MTRR_CACHE_WRITE_BACK);
     ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);
-    MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;
+    MtrrSettings.MtrrDefType |= BIT10;
     MtrrSetAllMtrrs (&MtrrSettings);
 
     //
diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c
index 31da5d0ace51..a066db34997c 100644
--- a/OvmfPkg/Sec/SecMain.c
+++ b/OvmfPkg/Sec/SecMain.c
@@ -30,6 +30,8 @@
 #include <Ppi/MpInitLibDep.h>
 #include <Library/TdxHelperLib.h>
 #include <Library/CcProbeLib.h>
+#include <Register/Intel/ArchitecturalMsr.h>
+#include <Register/Intel/Cpuid.h>
 #include "AmdSev.h"
 
 #define SEC_IDT_ENTRY_COUNT  34
@@ -744,6 +746,31 @@ FindAndReportEntryPoints (
   return;
 }
 
+//
+// Enable MTRR early, set default type to write back.
+// Needed to make sure caching is enabled,
+// without this lzma decompress can be very slow.
+//
+STATIC
+VOID
+SecMtrrSetup (
+  VOID
+  )
+{
+  CPUID_VERSION_INFO_EDX           Edx;
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;
+
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);
+  if (!Edx.Bits.MTRR) {
+    return;
+  }
+
+  DefType.Uint64    = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);;
+  DefType.Bits.Type = 6; /* write back */
+  DefType.Bits.E    = 1; /* enable */
+  AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
+}
+
 VOID
 EFIAPI
 SecCoreStartupWithStack (
@@ -942,6 +969,11 @@ SecCoreStartupWithStack (
   InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
   DisableApicTimerInterrupt ();
 
+  //
+  // Initialize MTRR
+  //
+  SecMtrrSetup ();
+
   //
   // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
   //
-- 
2.43.0



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[edk2-devel] [PATCH v2 2/4] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
index 756e7c86ec31..2b2e34b08c8b 100644
--- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -2103,6 +2103,13 @@ typedef union {
 #define MSR_IA32_MTRR_PHYSBASE9  0x00000212
 /// @}
 
+#define MSR_IA32_MTRR_CACHE_UNCACHEABLE      0
+#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING  1
+#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH    4
+#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED  5
+#define MSR_IA32_MTRR_CACHE_WRITE_BACK       6
+#define MSR_IA32_MTRR_CACHE_INVALID_TYPE     7
+
 /**
   MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
   #MSR_IA32_MTRR_PHYSBASE9
-- 
2.43.0



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[edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache type #defines from ArchitecturalMsr.h

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h
index 86cc1aab3b8e..c7d505ac06ed 100644
--- a/UefiCpuPkg/Include/Library/MtrrLib.h
+++ b/UefiCpuPkg/Include/Library/MtrrLib.h
@@ -9,6 +9,8 @@
 #ifndef  _MTRR_LIB_H_
 #define  _MTRR_LIB_H_
 
+#include <Register/Intel/ArchitecturalMsr.h>
+
 //
 // According to IA32 SDM, MTRRs number and MSR offset are always consistent
 // for IA32 processor family
@@ -90,12 +92,12 @@ typedef enum {
   CacheInvalid        = 7
 } MTRR_MEMORY_CACHE_TYPE;
 
-#define  MTRR_CACHE_UNCACHEABLE      0
-#define  MTRR_CACHE_WRITE_COMBINING  1
-#define  MTRR_CACHE_WRITE_THROUGH    4
-#define  MTRR_CACHE_WRITE_PROTECTED  5
-#define  MTRR_CACHE_WRITE_BACK       6
-#define  MTRR_CACHE_INVALID_TYPE     7
+#define  MTRR_CACHE_UNCACHEABLE      MSR_IA32_MTRR_CACHE_UNCACHEABLE
+#define  MTRR_CACHE_WRITE_COMBINING  MSR_IA32_MTRR_CACHE_WRITE_COMBINING
+#define  MTRR_CACHE_WRITE_THROUGH    MSR_IA32_MTRR_CACHE_WRITE_THROUGH
+#define  MTRR_CACHE_WRITE_PROTECTED  MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
+#define  MTRR_CACHE_WRITE_BACK       MSR_IA32_MTRR_CACHE_WRITE_BACK
+#define  MTRR_CACHE_INVALID_TYPE     MSR_IA32_MTRR_CACHE_INVALID_TYPE
 
 typedef struct {
   UINT64                    BaseAddress;
-- 
2.43.0



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[edk2-devel] [PATCH v2 4/4] OvmfPkg/Sec: use cache type #defines from ArchitecturalMsr.h

[Gerd Hoffmann]

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 OvmfPkg/IntelTdx/Sec/SecMain.c | 2 +-
 OvmfPkg/Sec/SecMain.c          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c b/OvmfPkg/IntelTdx/Sec/SecMain.c
index e8ff0e9081d1..6ad2214293b2 100644
--- a/OvmfPkg/IntelTdx/Sec/SecMain.c
+++ b/OvmfPkg/IntelTdx/Sec/SecMain.c
@@ -70,7 +70,7 @@ SecMtrrSetup (
   }
 
   DefType.Uint64    = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);;
-  DefType.Bits.Type = 6; /* write back */
+  DefType.Bits.Type = MSR_IA32_MTRR_CACHE_WRITE_BACK;
   DefType.Bits.E    = 1; /* enable */
   AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
 }
diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c
index a066db34997c..92cf510ea68f 100644
--- a/OvmfPkg/Sec/SecMain.c
+++ b/OvmfPkg/Sec/SecMain.c
@@ -766,7 +766,7 @@ SecMtrrSetup (
   }
 
   DefType.Uint64    = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);;
-  DefType.Bits.Type = 6; /* write back */
+  DefType.Bits.Type = MSR_IA32_MTRR_CACHE_WRITE_BACK;
   DefType.Bits.E    = 1; /* enable */
   AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
 }
-- 
2.43.0



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Re: [edk2-devel] [PATCH v2 1/4] OvmfPkg/Sec: Setup MTRR early in the boot process.

[Pedro Falcato]

On Thu, Jan 25, 2024 at 8:23 AM Gerd Hoffmann <kraxel@redhat.com> wrote:
>
> Specifically before running lzma uncompress of the main firmware volume.
> This is needed to make sure caching is enabled, otherwise the uncompress
> can be extremely slow.
>
> Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes.
>
> Background:  Depending on virtual machine configuration kvm may uses EPT
> memory types to apply guest MTRR settings.  In case MTRRs are disabled
> kvm will use the uncachable memory type for all mappings.  Here is the
> linux kernel function handling this:

It might not be wise to blat out GPLv2 source code in a commit message
:) Not that it's a violation of the GPL (we're not linking against it,
neither can the patch be considered a derivative work), but it might
just be a little too grey-area for a !GPL project.

-- 
Pedro


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Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache type #defines from ArchitecturalMsr.h

[Michael D Kinney]

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd
> Hoffmann
> Sent: Thursday, January 25, 2024 12:23 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Laszlo Ersek
> <lersek@redhat.com>; Aktas, Erdem <erdemaktas@google.com>; Michael Roth
> <michael.roth@amd.com>; Xu, Min M <min.m.xu@intel.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Yao, Jiewen <jiewen.yao@intel.com>; Tom Lendacky
> <thomas.lendacky@amd.com>; Oliver Steffen <osteffen@redhat.com>
> Subject: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache
> type #defines from ArchitecturalMsr.h
> 
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
>  UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h
> b/UefiCpuPkg/Include/Library/MtrrLib.h
> index 86cc1aab3b8e..c7d505ac06ed 100644
> --- a/UefiCpuPkg/Include/Library/MtrrLib.h
> +++ b/UefiCpuPkg/Include/Library/MtrrLib.h
> @@ -9,6 +9,8 @@
>  #ifndef  _MTRR_LIB_H_
>  #define  _MTRR_LIB_H_
> 
> +#include <Register/Intel/ArchitecturalMsr.h>
> +
>  //
>  // According to IA32 SDM, MTRRs number and MSR offset are always
> consistent
>  // for IA32 processor family
> @@ -90,12 +92,12 @@ typedef enum {
>    CacheInvalid        = 7
>  } MTRR_MEMORY_CACHE_TYPE;


I think the values in the above enum should also use the
MSR_IA32_MTRR_CACHE values.

> 
> -#define  MTRR_CACHE_UNCACHEABLE      0
> -#define  MTRR_CACHE_WRITE_COMBINING  1
> -#define  MTRR_CACHE_WRITE_THROUGH    4
> -#define  MTRR_CACHE_WRITE_PROTECTED  5
> -#define  MTRR_CACHE_WRITE_BACK       6
> -#define  MTRR_CACHE_INVALID_TYPE     7
> +#define  MTRR_CACHE_UNCACHEABLE      MSR_IA32_MTRR_CACHE_UNCACHEABLE
> +#define  MTRR_CACHE_WRITE_COMBINING
> MSR_IA32_MTRR_CACHE_WRITE_COMBINING
> +#define  MTRR_CACHE_WRITE_THROUGH    MSR_IA32_MTRR_CACHE_WRITE_THROUGH
> +#define  MTRR_CACHE_WRITE_PROTECTED
> MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
> +#define  MTRR_CACHE_WRITE_BACK       MSR_IA32_MTRR_CACHE_WRITE_BACK
> +#define  MTRR_CACHE_INVALID_TYPE     MSR_IA32_MTRR_CACHE_INVALID_TYPE
> 
>  typedef struct {
>    UINT64                    BaseAddress;
> --
> 2.43.0
> 
> 
> 
> 
> 



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Re: [edk2-devel] [PATCH v2 1/4] OvmfPkg/Sec: Setup MTRR early in the boot process.

[Laszlo Ersek]

On 1/25/24 11:52, Pedro Falcato wrote:
> On Thu, Jan 25, 2024 at 8:23 AM Gerd Hoffmann <kraxel@redhat.com> wrote:
>>
>> Specifically before running lzma uncompress of the main firmware volume.
>> This is needed to make sure caching is enabled, otherwise the uncompress
>> can be extremely slow.
>>
>> Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes.
>>
>> Background:  Depending on virtual machine configuration kvm may uses EPT
>> memory types to apply guest MTRR settings.  In case MTRRs are disabled
>> kvm will use the uncachable memory type for all mappings.  Here is the
>> linux kernel function handling this:
> 
> It might not be wise to blat out GPLv2 source code in a commit message
> :) Not that it's a violation of the GPL (we're not linking against it,
> neither can the patch be considered a derivative work), but it might
> just be a little too grey-area for a !GPL project.
> 

I think you are right.

How incredibly annoying.

Perhaps we should replace the vmx_get_mt_mask() quote with a link like...

https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/x86/kvm/vmx/vmx.c?h=v6.7.1#n7580

This link (including a line number) is stable, because it references a tag.

"all problems in computer science can be solved by another layer of
indirection"

https://en.wikipedia.org/wiki/David_Wheeler_(computer_scientist)#Quotes

Funnily enough, Linus would yell at us for this; IIRC he strongly
prefers embedding information over linking information, in commit
messages. :/

Laszlo



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