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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CE.mail.protection.outlook.com (10.167.241.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 13:12:59 +0000 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 07:12:25 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Eric Xing , Duke Zhai , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V3 16/32] AMD/VanGoghBoard: Check in BaseTscTimerLib Date: Fri, 26 Jan 2024 21:11:09 +0800 Message-ID: <20240126131125.1881-17-duke.zhai@amd.com> In-Reply-To: <20240126131125.1881-1-duke.zhai@amd.com> References: <20240126131125.1881-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CH3PR12MB9281:EE_ X-MS-Office365-Filtering-Correlation-Id: ee9159cb-6285-4296-868d-08dc1e708514 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: t8xh3niPribAazyhYKNaYnCvtlL08PYj8kD19CNjfBW5Ql9yKVphI2JD4ccbIjXMuwbWJ+Yl59UMH1rOLd41zwX/bLybl469J9g7zxWHq3t7wGMZsJKF+N29VAnUXNQdytocXjE+hVmYNCypj09UOxlFlJbRGaIqsHXUME6RCGsIy7nj10hXm1f4CS5xoqWu5NHRgZp4JQ2AcECi6wvhULQe4WJMX6i43YfpnpiLmMEcTwHrWU1lLrdI7KX52hE/VBaLHT0E+MwwBWemuCkxxbxUg5r0MxygvxwJHbXWtVkgIXXOsF9GJ7GfHGa+PWW+MzO306lKoH7CQ06pjr93IIkkPFIdX5Hg1o6eMJAv7ugMguZQ7W5cxmlNgX6gfR0EQt/ttu5L/A4wTYLCpTCRWhND2gCuMHPaO3L6U8nq9WQIy08Ns0iVCrtWZHfipEhmMX/vszWEW23t0awDrEwO3J8/0k17/ZdbFU388aiaQOQA5xNmYN3M/7xu32hsXkID5Opr5QPURU+X86ZgwzbTx3NmTsFj6+DDfFLl+3zSu6d5U+Mw1/e14dfuU2pCv2xbnHrhycJsWjaGwNwlU/f9Dg1ins/p2LZ5cIhWic/XBrnCwhn2te924Ev1WlQTBtyBruzEeR8I7KnKUh+MR5hf9YAUfBbJ6UtbgQwz6hM/68Oao3mmeOPqwz5G94LzYvMd4zxn1Epjk8hoBFj7EK2kz2nPHAAFyP0mvrshnrHyn//p03TqeokIVS2vO9eMOy2WQ0KeZrHx2ileV97qPKGs2ndP6ma1H+GLolLB0Vua6rwM6aORy6UuZFE/44qVNtsG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 13:12:59.6559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee9159cb-6285-4296-868d-08dc1e708514 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9281 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: LzzXq6v7YzYhmCc7l2YMiqnZx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=LB8DSvib; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") From: Duke Zhai BZ #:4640 In V3: Improve coding style follow edk2 C coding standard. 1.Remove macro definition extra underscores. 2.Putting some AMD copyright in the right place. In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Provides basic TSC timer calibration based on the ACPI timer hardware. The performance counter features are provided by the processors time stam= p counter. Signed-off-by: Ken Yao Cc: Eric Xing Cc: Duke Zhai Cc: Igniculus Fu Cc: Abner Chang --- .../Library/TscTimerLib/BaseTscTimerLib.c | 23 ++ .../Library/TscTimerLib/BaseTscTimerLib.inf | 43 +++ .../Library/TscTimerLib/DxeTscTimerLib.c | 80 ++++++ .../Library/TscTimerLib/DxeTscTimerLib.inf | 55 ++++ .../Library/TscTimerLib/PeiTscTimerLib.c | 53 ++++ .../Library/TscTimerLib/PeiTscTimerLib.inf | 49 ++++ .../Library/TscTimerLib/TscTimerLibInternal.h | 53 ++++ .../Library/TscTimerLib/TscTimerLibShare.c | 255 ++++++++++++++++++ 8 files changed, 611 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/BaseTscTimerLib.c create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/BaseTscTimerLib.inf create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/DxeTscTimerLib.c create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/DxeTscTimerLib.inf create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/PeiTscTimerLib.c create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/PeiTscTimerLib.inf create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/TscTimerLibInternal.h create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/TscTimerLibShare.c diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /BaseTscTimerLib.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/Tsc= TimerLib/BaseTscTimerLib.c new file mode 100644 index 0000000000..7dfef490e9 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTs= cTimerLib.c @@ -0,0 +1,23 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "TscTimerLibInternal.h" + +/** Get TSC frequency. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalGetTscFrequency ( + VOID + ) +{ + return InternalCalculateTscFrequency (); +} diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /BaseTscTimerLib.inf b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/T= scTimerLib/BaseTscTimerLib.inf new file mode 100644 index 0000000000..d6c4e2e1d6 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/BaseTs= cTimerLib.inf @@ -0,0 +1,43 @@ +## @file +# BaseTscTimerLib +# Provides basic timer support using the ACPI timer hardware. The perfor= mance +# counter features are provided by the processors time stamp counter. +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseTscTimerLib + FILE_GUID =3D D29338B9-50FE-4e4f-B7D4-A150A2C1F4FB + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib + + +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.common] + TscTimerLibShare.c + BaseTscTimerLib.c + TscTimerLibInternal.h + + +[Packages] + MdePkg/MdePkg.dec + AgesaPublic/AgesaPublic.dec + + +[LibraryClasses] + PcdLib + PciLib + IoLib + BaseLib + +[Pcd.common] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /DxeTscTimerLib.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/DxeTscTimerLib.c new file mode 100644 index 0000000000..5a374665c3 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTsc= TimerLib.c @@ -0,0 +1,80 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include "TscTimerLibInternal.h" + +UINT64 mTscFrequency; + +/** The constructor function determines the actual TSC frequency. + + First, Get TSC frequency from system configuration table with TSC freque= ncy GUID, + if the table is not found, install it. + This function will always return EFI_SUCCESS. + + @param ImageHandle The firmware allocated handle for the EFI imag= e. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +DxeTscTimerLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT64 *TscFrequency; + + TscFrequency =3D NULL; + // + // Get TSC frequency from system configuration table with TSC frequency = GUID. + // + Status =3D EfiGetSystemConfigurationTable (&gAmdCommonPkgTscFrequencyGui= d, (VOID **)&TscFrequency); + if (Status =3D=3D EFI_SUCCESS) { + ASSERT (TscFrequency !=3D NULL); + mTscFrequency =3D *TscFrequency; + return EFI_SUCCESS; + } + + // + // TSC frequency GUID system configuration table is not found, install i= t. + // + + Status =3D gBS->AllocatePool (EfiBootServicesData, sizeof (UINT64), (VOI= D **)&TscFrequency); + ASSERT_EFI_ERROR (Status); + + *TscFrequency =3D InternalCalculateTscFrequency (); + // + // TscFrequency now points to the number of TSC counts per second, insta= ll system configuration table for it. + // + gBS->InstallConfigurationTable (&gAmdCommonPkgTscFrequencyGuid, TscFrequ= ency); + + mTscFrequency =3D *TscFrequency; + return EFI_SUCCESS; +} + +/** Get TSC frequency. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalGetTscFrequency ( + VOID + ) +{ + return mTscFrequency; +} diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /DxeTscTimerLib.inf b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/Ts= cTimerLib/DxeTscTimerLib.inf new file mode 100644 index 0000000000..a9caae59a5 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/DxeTsc= TimerLib.inf @@ -0,0 +1,55 @@ +## @file +# DXE ACPI Timer Library +# +# Provides basic timer support using the ACPI timer hardware. The perfor= mance +# counter features are provided by the processors time stamp counter. +# +# Note: The implementation uses the lower 24-bits of the ACPI timer and +# is compatible with both 24-bit and 32-bit ACPI timers. +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeTscTimerLib + FILE_GUID =3D 95ab030f-b4fd-4ee4-92a5-9e04e87634d9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib|DXE_CORE DXE_DRIVER DXE_RUNT= IME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE + + CONSTRUCTOR =3D DxeTscTimerLibConstructor + + +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.common] + TscTimerLibShare.c + DxeTscTimerLib.c + TscTimerLibInternal.h + + +[Packages] + MdePkg/MdePkg.dec + VanGoghCommonPkg/AmdCommonPkg.dec + AgesaPublic/AgesaPublic.dec + +[LibraryClasses] + UefiBootServicesTableLib + PcdLib + PciLib + IoLib + BaseLib + UefiLib + DebugLib + +[Guids] + gAmdCommonPkgTscFrequencyGuid ## CONSUMES ## Sy= stem Configuration Table + +[Pcd.common] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /PeiTscTimerLib.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscT= imerLib/PeiTscTimerLib.c new file mode 100644 index 0000000000..338821b5d7 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTsc= TimerLib.c @@ -0,0 +1,53 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "TscTimerLibInternal.h" + +/** Get TSC frequency from TSC frequency GUID HOB, if the HOB is not foun= d, build it. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalGetTscFrequency ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + VOID *DataInHob; + UINT64 TscFrequency; + + // + // Get TSC frequency from TSC frequency GUID HOB. + // + GuidHob =3D GetFirstGuidHob (&gAmdCommonPkgTscFrequencyGuid); + if (GuidHob !=3D NULL) { + DataInHob =3D GET_GUID_HOB_DATA (GuidHob); + TscFrequency =3D *(UINT64 *)DataInHob; + return TscFrequency; + } + + // + // TSC frequency GUID HOB is not found, build it. + // + + TscFrequency =3D InternalCalculateTscFrequency (); + // + // TscFrequency is now equal to the number of TSC counts per second, bui= ld GUID HOB for it. + // + BuildGuidDataHob ( + &gAmdCommonPkgTscFrequencyGuid, + &TscFrequency, + sizeof (UINT64) + ); + + return TscFrequency; +} diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /PeiTscTimerLib.inf b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/Ts= cTimerLib/PeiTscTimerLib.inf new file mode 100644 index 0000000000..0af33ada5f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/PeiTsc= TimerLib.inf @@ -0,0 +1,49 @@ +## @file +# PEI ACPI Timer Library +# +# Provides basic timer support using the ACPI timer hardware. The perfor= mance +# counter features are provided by the processors time stamp counter. +# +# Note: The implementation uses the lower 24-bits of the ACPI timer and +# is compatible with both 24-bit and 32-bit ACPI timers. +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiTscTimerLib + FILE_GUID =3D 342C36C0-15DF-43b4-9EC9-FBF748BFB3D1 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.common] + TscTimerLibShare.c + PeiTscTimerLib.c + TscTimerLibInternal.h + +[Packages] + MdePkg/MdePkg.dec + AgesaPublic/AgesaPublic.dec + VanGoghCommonPkg/AmdCommonPkg.dec + +[LibraryClasses] + PcdLib + PciLib + IoLib + BaseLib + HobLib + +[Guids] + gAmdCommonPkgTscFrequencyGuid ## PRODUCES ## HO= B + +[Pcd.common] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /TscTimerLibInternal.h b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library= /TscTimerLib/TscTimerLibInternal.h new file mode 100644 index 0000000000..619100ef0e --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTim= erLibInternal.h @@ -0,0 +1,53 @@ +/** @file + Header file internal to ACPI TimerLib. + +Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) Microsoft Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TSC_TIMER_LIB_INTERNAL_H_ +#define TSC_TIMER_LIB_INTERNAL_H_ + +#include +#include +#include +#include +#include + +#include +#define ACPI_MMIO_BASE 0xFED80000ul +#define PMIO_BASE 0x300 // DWORD +#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk + +/** Get TSC frequency. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalGetTscFrequency ( + VOID + ); + +/** Calculate TSC frequency. + + The TSC counting frequency is determined by comparing how far it counts + during a 1ms period as determined by the ACPI timer. The ACPI timer is + used because it counts at a known frequency. + If ACPI I/O space not enabled, this function will enable it. Then the + TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, o= r 1ms. + The TSC is then sampled again. The difference multiplied by 1000 is the = TSC + frequency. There will be a small error because of the overhead of readin= g + the ACPI timer. An attempt is made to determine and compensate for this = error. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalCalculateTscFrequency ( + VOID + ); + +#endif diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib= /TscTimerLibShare.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/Ts= cTimerLib/TscTimerLibShare.c new file mode 100644 index 0000000000..a49a2db2b3 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Library/TscTimerLib/TscTim= erLibShare.c @@ -0,0 +1,255 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "TscTimerLibInternal.h" + +/** Calculate TSC frequency. + + The TSC counting frequency is determined by comparing how far it counts + during a 1ms period as determined by the ACPI timer. The ACPI timer is + used because it counts at a known frequency. + If ACPI I/O space not enabled, this function will enable it. Then the + TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, o= r 1ms. + The TSC is then sampled again. The difference multiplied by 1000 is the = TSC + frequency. There will be a small error because of the overhead of readin= g + the ACPI timer. An attempt is made to determine and compensate for this = error. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalCalculateTscFrequency ( + VOID + ) +{ + UINT64 StartTSC; + UINT64 EndTSC; + UINT16 TimerAddr; + UINT32 Ticks; + UINT64 TscFrequency; + + TimerAddr =3D MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64); + if (TimerAddr =3D=3D 0) { + TimerAddr =3D PcdGet16 (PcdAmdFchCfgAcpiPmTmrBlkAddr); + MmioWrite16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, TimerAddr); + } + + // + // ACPI I/O space should be enabled now, locate the ACPI Timer. + // ACPI I/O base address maybe have be initialized by other driver with = different value, + // So get it from PCI space directly. + // + Ticks =3D IoRead32 (TimerAddr) + (3579); // Set Ticks to 1ms in the= future + StartTSC =3D AsmReadTsc (); // Get base value for the = TSC + // + // Wait until the ACPI timer has counted 1ms. + // Timer wrap-arounds are handled correctly by this function. + // When the current ACPI timer value is greater than 'Ticks', the while = loop will exit. + // + while (((Ticks - IoRead32 (TimerAddr)) & BIT23) =3D=3D 0) { + CpuPause (); + } + + EndTSC =3D AsmReadTsc (); // TSC value 1ms later + + TscFrequency =3D MultU64x32 ( + (EndTSC - StartTSC), // Number of TSC counts in 1= ms + 1000 // Number of ms in a second + ); + + return TscFrequency; +} + +/** Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param[in] Delay A period of time to delay in ticks. + +**/ +VOID +InternalX86Delay ( + IN UINT64 Delay + ) +{ + UINT64 Ticks; + + // + // The target timer count is calculated here + // + Ticks =3D AsmReadTsc () + Delay; + + // + // Wait until time out + // Timer wrap-arounds are NOT handled correctly by this function. + // Thus, this function must be called within 10 years of reset since + // Intel ensures a minimum of 10 years before the TSC wraps. + // + while (AsmReadTsc () <=3D Ticks) { + CpuPause (); + } +} + +/** Stalls the CPU for at least the specified number of MicroSeconds. + + @param[in] MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds input. + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalX86Delay ( + DivU64x32 ( + MultU64x64 ( + InternalGetTscFrequency (), + MicroSeconds + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** Stalls the CPU for at least the specified number of NanoSeconds. + + @param[in] NanoSeconds The minimum number of nanoseconds to delay. + + @return The value of NanoSeconds input. + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalX86Delay ( + DivU64x32 ( + MultU64x32 ( + InternalGetTscFrequency (), + (UINT32)NanoSeconds + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** Retrieves the current value of the 64-bit free running Time-Stamp cou= nter. + + The time-stamp counter (as implemented in the P6 family, Pentium, Pentiu= m M, + Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and + later processors) is a 64-bit counter that is set to 0 following a RESET= of + the processor. Following a RESET, the counter increments even when the + processor is halted by the HLT instruction or the external STPCLK# pin. = Note + that the assertion of the external DPSLP# pin may cause the time-stamp + counter to stop. + + The properties of the counter can be retrieved by the + GetPerformanceCounterProperties() function. + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return AsmReadTsc (); +} + +/** Retrieves the 64-bit frequency in Hz and the range of performance cou= nter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with, 0x0, is returned in StartValue. If EndValue is not NULL, then the = value + that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned i= n + EndValue. + + The 64-bit frequency of the performance counter, in Hz, is always return= ed. + To determine average processor clock frequency, Intel recommends the use= of + EMON logic to count processor core clocks over the period of time for wh= ich + the average is required. + + + @param[out] StartValue Pointer to where the performance counter's sta= rting value is saved, or NULL. + @param[out] EndValue Pointer to where the performance counter's end= ing value is saved, or NULL. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 0xFFFFFFFFFFFFFFFFull; + } + + return InternalGetTscFrequency (); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 Frequency; + UINT64 NanoSeconds; + UINT64 Remainder; + INTN Shift; + + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remai= nder), 1000000000u); + + // + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should < = 2^(64-30) =3D 2^34, + // i.e. highest bit set in Remainder should <=3D 33. + // + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); + Remainder =3D RShiftU64 (Remainder, (UINTN)Shift); + Frequency =3D RShiftU64 (Frequency, (UINTN)Shift); + NanoSeconds +=3D DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u)= , Frequency, NULL); + + return NanoSeconds; +} --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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