[edk2-devel] [PATCH v1 0/1] Add cache operations support for CPU Arch proto

[edk2-devel] [PATCH v1 0/1] Add cache operations support for CPU Arch proto

[Dhaval Sharma]

With CMO operations available for RISC-V, utilize them in CPU
Architecture protocol.

Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Gerd Hoffmann <kraxel@redhat.com>
Laszlo Ersek <lersek@redhat.com>
Rahul Kumar <rahul1.kumar@intel.com>
Ray Ni <ray.ni@intel.com>
Sunil VL <sunilvl@ventanamicro.com>
Andrei Warkentin <andrei.warkentin@intel.com>
devel@edk2.groups.io

Dhaval (1):
  UefiCpuPkg: Add cache operations support for Arch proto

 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h |  1 +
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

-- 
2.39.2



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[edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for Arch proto

[Dhaval Sharma]

With CMO operations available for RISC-V, utilize them in CPU
Architecture protocol.

Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Gerd Hoffmann <kraxel@redhat.com>
Laszlo Ersek <lersek@redhat.com>
Rahul Kumar <rahul1.kumar@intel.com>
Ray Ni <ray.ni@intel.com>
Sunil VL <sunilvl@ventanamicro.com>
Andrei Warkentin <andrei.warkentin@intel.com>
devel@edk2.groups.io
---
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h |  1 +
 UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
index 68e6d038b66e..d4d67778eb1c 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
@@ -17,6 +17,7 @@
 #include <Library/BaseRiscVSbiLib.h>
 #include <Library/BaseRiscVMmuLib.h>
 #include <Library/BaseLib.h>
+#include <Library/CacheMaintenanceLib.h>
 #include <Library/CpuExceptionHandlerLib.h>
 #include <Library/DebugLib.h>
 #include <Library/UefiBootServicesTableLib.h>
diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
index 2af3b6223450..c6bae100a9e4 100644
--- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
@@ -90,6 +90,20 @@ CpuFlushCpuDataCache (
   IN EFI_CPU_FLUSH_TYPE     FlushType
   )
 {
+  switch (FlushType) {
+    case EfiCpuFlushTypeWriteBack:
+      WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+      break;
+    case EfiCpuFlushTypeInvalidate:
+      InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+      break;
+    case EfiCpuFlushTypeWriteBackInvalidate:
+      WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
+      break;
+    default:
+      return EFI_INVALID_PARAMETER;
+  }
+
   return EFI_SUCCESS;
 }
 
-- 
2.39.2



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Re: [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for Arch proto

[Sunil V L]

Hi Dhaval,

Thank you very much for the patch!.

On Mon, Jan 29, 2024 at 09:31:16AM +0530, Dhaval Sharma wrote:
> With CMO operations available for RISC-V, utilize them in CPU
> Architecture protocol.
> 
> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
> Gerd Hoffmann <kraxel@redhat.com>
> Laszlo Ersek <lersek@redhat.com>
> Rahul Kumar <rahul1.kumar@intel.com>
> Ray Ni <ray.ni@intel.com>
> Sunil VL <sunilvl@ventanamicro.com>
> Andrei Warkentin <andrei.warkentin@intel.com>
> devel@edk2.groups.io

You have missed adding "Cc:". Without this tag, they will not
be copied explicitly. I am copying them in this reply and I will update
the commit message during merge to fix it.

> ---
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h |  1 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> index 68e6d038b66e..d4d67778eb1c 100644
> --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
> @@ -17,6 +17,7 @@
>  #include <Library/BaseRiscVSbiLib.h>
>  #include <Library/BaseRiscVMmuLib.h>
>  #include <Library/BaseLib.h>
> +#include <Library/CacheMaintenanceLib.h>
>  #include <Library/CpuExceptionHandlerLib.h>
>  #include <Library/DebugLib.h>
>  #include <Library/UefiBootServicesTableLib.h>
> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> index 2af3b6223450..c6bae100a9e4 100644
> --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c
> @@ -90,6 +90,20 @@ CpuFlushCpuDataCache (
>    IN EFI_CPU_FLUSH_TYPE     FlushType
>    )
>  {
> +  switch (FlushType) {
> +    case EfiCpuFlushTypeWriteBack:
> +      WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
> +      break;
> +    case EfiCpuFlushTypeInvalidate:
> +      InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
> +      break;
> +    case EfiCpuFlushTypeWriteBackInvalidate:
> +      WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
> +      break;
> +    default:
> +      return EFI_INVALID_PARAMETER;
> +  }
> +
>    return EFI_SUCCESS;
>  }
>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>  


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