From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <bounce+27952+114777+7686176+12367111@groups.io>
Received: from mail02.groups.io (mail02.groups.io [66.175.222.108])
by spool.mail.gandi.net (Postfix) with ESMTPS id 9F41B740045
for <rebecca@openfw.io>; Tue, 30 Jan 2024 12:32:19 +0000 (UTC)
DKIM-Signature: a=rsa-sha256; bh=F/5rj8cK9N1lmY+cZR3bpxzOEc7IHxQI5Zezkmut5eY=;
c=relaxed/simple; d=groups.io;
h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type;
s=20140610; t=1706617938; v=1;
b=MPHs2vKXuGnBs7EeTMP/RPhPHChjQaZJ+q2xakoarR/8LMjHBgbMxsun4+lq+E/OgZKdYWr2
xPYAWv29bGeToPDsW9L1dmNcM3jM4xbrKYjAjgkVpI/kb7MIAw99DrOs6YpY4TMJzqmPGy9SUeB
tgk4l6ANmA/jf0xqKeqMO39Y=
X-Received: by 127.0.0.2 with SMTP id rZMoYY7687511xIrNWIw11Ou; Tue, 30 Jan 2024 04:32:18 -0800
X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124])
by mx.groups.io with SMTP id smtpd.web11.16937.1706617937556699776
for <devel@edk2.groups.io>;
Tue, 30 Jan 2024 04:32:17 -0800
X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com
[66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS
(version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id
us-mta-215-AADEV5toMU2KqMHjYdNgSw-1; Tue, 30 Jan 2024 07:32:12 -0500
X-MC-Unique: AADEV5toMU2KqMHjYdNgSw-1
X-Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8])
(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)
key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256)
(No client certificate requested)
by mimecast-mx02.redhat.com (Postfix) with ESMTPS id BA6EA8630C6;
Tue, 30 Jan 2024 12:32:11 +0000 (UTC)
X-Received: from sirius.home.kraxel.org (unknown [10.39.192.180])
by smtp.corp.redhat.com (Postfix) with ESMTPS id 88B1AC2E0EA;
Tue, 30 Jan 2024 12:32:11 +0000 (UTC)
X-Received: by sirius.home.kraxel.org (Postfix, from userid 1000)
id 97B1D1800DC6; Tue, 30 Jan 2024 13:32:04 +0100 (CET)
From: "Gerd Hoffmann" <kraxel@redhat.com>
To: devel@edk2.groups.io
Cc: Erdem Aktas <erdemaktas@google.com>,
Oliver Steffen <osteffen@redhat.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Min Xu <min.m.xu@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Gerd Hoffmann <kraxel@redhat.com>,
Michael Roth <michael.roth@amd.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Laszlo Ersek <lersek@redhat.com>
Subject: [edk2-devel] [PATCH v2 5/5] OvmfPkg/PlatformInitLib: add 5-level paging support
Date: Tue, 30 Jan 2024 13:32:04 +0100
Message-ID: <20240130123204.764453-6-kraxel@redhat.com>
In-Reply-To: <20240130123204.764453-1-kraxel@redhat.com>
References: <20240130123204.764453-1-kraxel@redhat.com>
MIME-Version: 1.0
X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8
X-Mimecast-Spam-Score: 0
X-Mimecast-Originator: redhat.com
Precedence: Bulk
List-Subscribe: <mailto:devel+subscribe@edk2.groups.io>
List-Help: <mailto:devel+help@edk2.groups.io>
Sender: devel@edk2.groups.io
List-Id: <devel.edk2.groups.io>
Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io
Reply-To: devel@edk2.groups.io,kraxel@redhat.com
List-Unsubscribe-Post: List-Unsubscribe=One-Click
List-Unsubscribe: <https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/plugh>
X-Gm-Message-State: z6jBFRIz67grxfIQD57m9nwLx7686176AA=
Content-Transfer-Encoding: 8bit
Content-Type: text/plain; charset="US-ASCII"; x-default=true
X-GND-Status: LEGIT
Authentication-Results: spool.mail.gandi.net;
dkim=pass header.d=groups.io header.s=20140610 header.b=MPHs2vKX;
dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none);
spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io
Adjust physical address space logic for la57 mode (5-level paging).
With a larger logical address space we can identity-map a larger
physical address space.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
---
OvmfPkg/Library/PlatformInitLib/MemDetect.c | 57 ++++++++++++++-------
1 file changed, 38 insertions(+), 19 deletions(-)
diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index f042517bb64a..0f9658fc34fa 100644
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -628,11 +628,12 @@ PlatformAddressWidthFromCpuid (
IN BOOLEAN QemuQuirk
)
{
- UINT32 RegEax, RegEbx, RegEcx, RegEdx, Max;
- UINT8 PhysBits;
- CHAR8 Signature[13];
- BOOLEAN Valid = FALSE;
- BOOLEAN Page1GSupport = FALSE;
+ UINT32 RegEax, RegEbx, RegEcx, RegEdx, Max;
+ UINT8 PhysBits;
+ CHAR8 Signature[13];
+ IA32_CR4 Cr4;
+ BOOLEAN Valid = FALSE;
+ BOOLEAN Page1GSupport = FALSE;
ZeroMem (Signature, sizeof (Signature));
@@ -670,30 +671,48 @@ PlatformAddressWidthFromCpuid (
}
}
+ Cr4.UintN = AsmReadCr4 ();
+
DEBUG ((
DEBUG_INFO,
- "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n",
+ "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, la57: %a, Valid: %a\n",
__func__,
Signature,
PhysBits,
QemuQuirk ? "On" : "Off",
+ Cr4.Bits.LA57 ? "On" : "Off",
Valid ? "Yes" : "No"
));
if (Valid) {
- if (PhysBits > 46) {
- /*
- * Avoid 5-level paging altogether for now, which limits
- * PhysBits to 48. Also avoid using address bit 48, due to sign
- * extension we can't identity-map these addresses (and lots of
- * places in edk2 assume we have everything identity-mapped).
- * So the actual limit is 47.
- *
- * Also some older linux kernels apparently have problems handling
- * phys-bits > 46 correctly, so use that as limit.
- */
- DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 46 (avoid 5-level paging)\n", __func__));
- PhysBits = 46;
+ /*
+ * Due to the sign extension we can use only the lower half of the
+ * virtual address space to identity-map physical address space,
+ * which gives us a 47 bit wide address space with 4 paging levels
+ * and a 56 bit wide address space with 5 paging levels.
+ */
+ if (Cr4.Bits.LA57) {
+ if (PhysBits > 48) {
+ /*
+ * Some Intel CPUs support 5-level paging, have more than 48
+ * phys-bits but support only 4-level EPT, which effectively
+ * limits guest phys-bits to 48. Until we have some way to
+ * communicate that limitation from hypervisor to guest, limit
+ * phys-bits to 48 unconditionally.
+ */
+ DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 48 (5-level paging)\n", __func__));
+ PhysBits = 48;
+ }
+ } else {
+ if (PhysBits > 46) {
+ /*
+ * Some older linux kernels apparently have problems handling
+ * phys-bits > 46 correctly, so use that instead of 47 as
+ * limit.
+ */
+ DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 46 (4-level paging)\n", __func__));
+ PhysBits = 46;
+ }
}
if (!Page1GSupport && (PhysBits > 40)) {
--
2.43.0
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#114777): https://edk2.groups.io/g/devel/message/114777
Mute This Topic: https://groups.io/mt/104052209/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-