[edk2-devel] [PATCH 2/3] OvmfPkg/PlatformPei: rewrite page table calculation

["Gerd Hoffmann" <kraxel@redhat.com>]

Consider 5-level paging.  Simplify calculation to make it easier to
understand.  The new calculation is not 100% exact, but we only need
a rough estimate to reserve enough memory.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 OvmfPkg/PlatformPei/MemDetect.c | 42 ++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c
index 338798b54171..e22743b4bfaa 100644
--- a/OvmfPkg/PlatformPei/MemDetect.c
+++ b/OvmfPkg/PlatformPei/MemDetect.c
@@ -184,8 +184,10 @@ GetPeiMemoryCap (
   BOOLEAN  Page1GSupport;
   UINT32   RegEax;
   UINT32   RegEdx;
-  UINT32   Pml4Entries;
-  UINT32   PdpEntries;
+  UINT32   Level5Pages;
+  UINT32   Level4Pages;
+  UINT32   Level3Pages;
+  UINT32   Level2Pages;
   UINTN    TotalPages;
   UINTN    ApStacks;
   UINTN    MemoryCap;
@@ -203,8 +205,7 @@ GetPeiMemoryCap (
   //
   // Dependent on physical address width, PEI memory allocations can be
   // dominated by the page tables built for 64-bit DXE. So we key the cap off
-  // of those. The code below is based on CreateIdentityMappingPageTables() in
-  // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
+  // of those.
   //
   Page1GSupport = FALSE;
   if (PcdGetBool (PcdUse1GPageTable)) {
@@ -217,23 +218,26 @@ GetPeiMemoryCap (
     }
   }
 
-  if (PlatformInfoHob->PhysMemAddressWidth <= 39) {
-    Pml4Entries = 1;
-    PdpEntries  = 1 << (PlatformInfoHob->PhysMemAddressWidth - 30);
-    ASSERT (PdpEntries <= 0x200);
-  } else {
-    if (PlatformInfoHob->PhysMemAddressWidth > 48) {
-      Pml4Entries = 0x200;
-    } else {
-      Pml4Entries = 1 << (PlatformInfoHob->PhysMemAddressWidth - 39);
-    }
-
-    ASSERT (Pml4Entries <= 0x200);
-    PdpEntries = 512;
+  //
+  // This calculation doesn't return the *exact* number of page table
+  // pages needed.  But we only need a rough estimate to reserve
+  // enough memory, being off by a few pages isn't much of problem.
+  // So keep the calculation simple and easy to understand.
+  //
+  // Page size is 4k, which needs 12 address bits.
+  // Page tables on all levels have 512 entries, mapping to 9 address bits.
+  // We use large pages (2M or 1G), so level 1 never exists.
+  // Start with level 2, where a page covers 12 + 9 + 9 = 30 address bits.
+  //
+  Level2Pages = (1 << (PlatformInfoHob->PhysMemAddressWidth - 30)) + 1;
+  Level3Pages = (Level2Pages >> 9) + 1;
+  Level4Pages = (Level3Pages >> 9) + 1;
+  Level5Pages = (Level4Pages >> 9) + 1;
+  if (Page1GSupport) {
+    Level2Pages = 0;
   }
 
-  TotalPages = Page1GSupport ? Pml4Entries + 1 :
-               (PdpEntries + 1) * Pml4Entries + 1;
+  TotalPages = Level5Pages + Level4Pages + Level3Pages + Level2Pages;
   ASSERT (TotalPages <= 0x40201);
 
   ApStacks  = PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber * PcdGet32 (PcdCpuApStackSize);
-- 
2.43.0



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